2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
37 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 * Helper function for handling mirror image blits.
42 * If coord0 > coord1, swap them and invert the "mirror" boolean.
45 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
47 if (coord0
> coord1
) {
57 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
58 * destination coordinates.
60 * Return true if there is still blitting to do, false if all pixels got
61 * rejected by the clip and/or scissor.
63 * For clarity, the nomenclature of this function assumes we are clipping and
64 * scissoring the X coordinate; the exact same logic applies for Y
67 * Note: this function may also be used to account for clipping of source
68 * coordinates, by swapping the roles of src and dst.
71 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
72 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
74 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
75 /* If we are going to scissor everything away, stop. */
76 if (!(fb_xmin
< fb_xmax
&&
83 /* Clip the destination rectangle, and keep track of how many pixels we
84 * clipped off of the left and right sides of it.
86 GLint pixels_clipped_left
= 0;
87 GLint pixels_clipped_right
= 0;
88 if (dst_x0
< fb_xmin
) {
89 pixels_clipped_left
= fb_xmin
- dst_x0
;
92 if (fb_xmax
< dst_x1
) {
93 pixels_clipped_right
= dst_x1
- fb_xmax
;
97 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
98 * the source coordinates, we need to flip them to account for the
102 GLint tmp
= pixels_clipped_left
;
103 pixels_clipped_left
= pixels_clipped_right
;
104 pixels_clipped_right
= tmp
;
107 /* Adjust the source rectangle to remove the pixels corresponding to those
108 * that were clipped/scissored out of the destination rectangle.
110 src_x0
+= pixels_clipped_left
* scale
;
111 src_x1
-= pixels_clipped_right
* scale
;
117 static struct intel_mipmap_tree
*
118 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
120 struct intel_mipmap_tree
*mt
= irb
->mt
;
121 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
127 brw_blorp_blit_miptrees(struct brw_context
*brw
,
128 struct intel_mipmap_tree
*src_mt
,
129 unsigned src_level
, unsigned src_layer
,
130 struct intel_mipmap_tree
*dst_mt
,
131 unsigned dst_level
, unsigned dst_layer
,
132 float src_x0
, float src_y0
,
133 float src_x1
, float src_y1
,
134 float dst_x0
, float dst_y0
,
135 float dst_x1
, float dst_y1
,
136 GLenum filter
, bool mirror_x
, bool mirror_y
)
138 /* Get ready to blit. This includes depth resolving the src and dst
139 * buffers if necessary. Note: it's not necessary to do a color resolve on
140 * the destination buffer because we use the standard render path to render
141 * to destination color buffers, and the standard render path is
144 intel_miptree_resolve_color(brw
, src_mt
);
145 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
146 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
148 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
149 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
151 _mesa_get_format_name(src_mt
->format
), src_mt
,
152 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
153 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
154 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
157 brw_blorp_blit_params
params(brw
,
158 src_mt
, src_level
, src_layer
,
159 dst_mt
, dst_level
, dst_layer
,
164 filter
, mirror_x
, mirror_y
);
165 brw_blorp_exec(brw
, ¶ms
);
167 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
171 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
172 struct intel_renderbuffer
*src_irb
,
173 struct intel_renderbuffer
*dst_irb
,
174 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
175 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
176 GLenum filter
, bool mirror_x
, bool mirror_y
)
178 /* Find source/dst miptrees */
179 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
180 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
183 brw_blorp_blit_miptrees(brw
,
184 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
185 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
186 srcX0
, srcY0
, srcX1
, srcY1
,
187 dstX0
, dstY0
, dstX1
, dstY1
,
188 filter
, mirror_x
, mirror_y
);
190 intel_renderbuffer_set_needs_downsample(dst_irb
);
194 color_formats_match(gl_format src_format
, gl_format dst_format
)
196 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
197 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
199 /* Normally, we require the formats to be equal. However, we also support
200 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
201 * (overriding alpha to 1.0 via blending).
203 return linear_src_format
== linear_dst_format
||
204 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
205 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
206 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
207 linear_dst_format
== MESA_FORMAT_XRGB8888
);
211 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
212 struct intel_renderbuffer
*dst_irb
)
214 /* Note: don't just check gl_renderbuffer::Format, because in some cases
215 * multiple gl_formats resolve to the same native type in the miptree (for
216 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
217 * between those formats.
219 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
220 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
222 return color_formats_match(src_format
, dst_format
);
226 try_blorp_blit(struct brw_context
*brw
,
227 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
228 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
229 GLenum filter
, GLbitfield buffer_bit
)
231 struct gl_context
*ctx
= &brw
->ctx
;
233 /* Sync up the state of window system buffers. We need to do this before
234 * we go looking for the buffers.
236 intel_prepare_render(brw
);
238 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
239 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
241 /* Detect if the blit needs to be mirrored */
242 bool mirror_x
= false, mirror_y
= false;
243 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
244 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
245 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
246 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
248 /* If the destination rectangle needs to be clipped or scissored, do so.
250 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
251 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
252 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
253 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
254 /* Everything got clipped/scissored away, so the blit was successful. */
258 /* If the source rectangle needs to be clipped or scissored, do so. */
259 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
260 0, read_fb
->Width
) &&
261 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
262 0, read_fb
->Height
))) {
263 /* Everything got clipped/scissored away, so the blit was successful. */
267 /* Account for the fact that in the system framebuffer, the origin is at
270 if (_mesa_is_winsys_fbo(read_fb
)) {
271 GLint tmp
= read_fb
->Height
- srcY0
;
272 srcY0
= read_fb
->Height
- srcY1
;
274 mirror_y
= !mirror_y
;
276 if (_mesa_is_winsys_fbo(draw_fb
)) {
277 GLint tmp
= draw_fb
->Height
- dstY0
;
278 dstY0
= draw_fb
->Height
- dstY1
;
280 mirror_y
= !mirror_y
;
284 struct intel_renderbuffer
*src_irb
;
285 struct intel_renderbuffer
*dst_irb
;
286 switch (buffer_bit
) {
287 case GL_COLOR_BUFFER_BIT
:
288 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
289 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
290 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
291 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
294 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
295 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
297 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
298 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
299 filter
, mirror_x
, mirror_y
);
302 case GL_DEPTH_BUFFER_BIT
:
304 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
306 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
307 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
309 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
310 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
311 filter
, mirror_x
, mirror_y
);
313 case GL_STENCIL_BUFFER_BIT
:
315 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
317 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
318 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
320 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
321 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
322 filter
, mirror_x
, mirror_y
);
332 brw_blorp_copytexsubimage(struct brw_context
*brw
,
333 struct gl_renderbuffer
*src_rb
,
334 struct gl_texture_image
*dst_image
,
336 int srcX0
, int srcY0
,
337 int dstX0
, int dstY0
,
338 int width
, int height
)
340 struct gl_context
*ctx
= &brw
->ctx
;
341 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
342 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
344 /* Sync up the state of window system buffers. We need to do this before
345 * we go looking at the src renderbuffer's miptree.
347 intel_prepare_render(brw
);
349 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
350 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
352 /* BLORP is not supported before Gen6. */
353 if (brw
->gen
< 6 || brw
->gen
>= 8)
356 if (_mesa_get_format_base_format(src_mt
->format
) !=
357 _mesa_get_format_base_format(dst_mt
->format
)) {
361 /* We can't handle format conversions between Z24 and other formats since
362 * we have to lie about the surface format. See the comments in
363 * brw_blorp_surface_info::set().
365 if ((src_mt
->format
== MESA_FORMAT_X8_Z24
) !=
366 (dst_mt
->format
== MESA_FORMAT_X8_Z24
)) {
370 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
373 /* Source clipping shouldn't be necessary, since copytexsubimage (in
374 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
377 * Destination clipping shouldn't be necessary since the restrictions on
378 * glCopyTexSubImage prevent the user from specifying a destination rectangle
379 * that falls outside the bounds of the destination texture.
380 * See error_check_subtexture_dimensions().
383 int srcY1
= srcY0
+ height
;
384 int srcX1
= srcX0
+ width
;
385 int dstX1
= dstX0
+ width
;
386 int dstY1
= dstY0
+ height
;
388 /* Account for the fact that in the system framebuffer, the origin is at
391 bool mirror_y
= false;
392 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
393 GLint tmp
= src_rb
->Height
- srcY0
;
394 srcY0
= src_rb
->Height
- srcY1
;
399 brw_blorp_blit_miptrees(brw
,
400 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
401 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
402 srcX0
, srcY0
, srcX1
, srcY1
,
403 dstX0
, dstY0
, dstX1
, dstY1
,
404 GL_NEAREST
, false, mirror_y
);
406 /* If we're copying to a packed depth stencil texture and the source
407 * framebuffer has separate stencil, we need to also copy the stencil data
410 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
411 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
413 src_irb
= intel_renderbuffer(src_rb
);
414 src_mt
= src_irb
->mt
;
416 if (src_mt
->stencil_mt
)
417 src_mt
= src_mt
->stencil_mt
;
418 if (dst_mt
->stencil_mt
)
419 dst_mt
= dst_mt
->stencil_mt
;
421 if (src_mt
!= dst_mt
) {
422 brw_blorp_blit_miptrees(brw
,
423 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
424 dst_mt
, dst_image
->Level
,
425 dst_image
->Face
+ slice
,
426 srcX0
, srcY0
, srcX1
, srcY1
,
427 dstX0
, dstY0
, dstX1
, dstY1
,
428 GL_NEAREST
, false, mirror_y
);
437 brw_blorp_framebuffer(struct brw_context
*brw
,
438 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
439 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
440 GLbitfield mask
, GLenum filter
)
442 /* BLORP is not supported before Gen6. */
443 if (brw
->gen
< 6 || brw
->gen
>= 8)
446 static GLbitfield buffer_bits
[] = {
449 GL_STENCIL_BUFFER_BIT
,
452 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
453 if ((mask
& buffer_bits
[i
]) &&
455 srcX0
, srcY0
, srcX1
, srcY1
,
456 dstX0
, dstY0
, dstX1
, dstY1
,
457 filter
, buffer_bits
[i
])) {
458 mask
&= ~buffer_bits
[i
];
467 * Enum to specify the order of arguments in a sampler message
469 enum sampler_message_arg
471 SAMPLER_MESSAGE_ARG_U_FLOAT
,
472 SAMPLER_MESSAGE_ARG_V_FLOAT
,
473 SAMPLER_MESSAGE_ARG_U_INT
,
474 SAMPLER_MESSAGE_ARG_V_INT
,
475 SAMPLER_MESSAGE_ARG_SI_INT
,
476 SAMPLER_MESSAGE_ARG_MCS_INT
,
477 SAMPLER_MESSAGE_ARG_ZERO_INT
,
481 * Generator for WM programs used in BLORP blits.
483 * The bulk of the work done by the WM program is to wrap and unwrap the
484 * coordinate transformations used by the hardware to store surfaces in
485 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
486 * sample index for a multisampled surface) to a memory offset by the
487 * following formulas:
489 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
490 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
492 * For a single-sampled surface, or for a multisampled surface using
493 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
496 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
497 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
498 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
499 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
501 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
502 * embeds the sample number into bit 1 of the X and Y coordinates:
504 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
505 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
506 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
507 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
508 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
509 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
510 * S = (Y & 0b10) | (X & 0b10) >> 1
512 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
513 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
516 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
517 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
518 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
519 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
520 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
521 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
522 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
524 * For X tiling, tile() combines together the low-order bits of the X and Y
525 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
526 * bytes wide and 8 rows high:
528 * tile(x_tiled, X, Y, S) = A
529 * where A = tile_num << 12 | offset
530 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
531 * offset = (Y' & 0b111) << 9
532 * | (X & 0b111111111)
534 * Y' = Y + S * qpitch
535 * detile(x_tiled, A) = (X, Y, S)
539 * Y' = (tile_num / tile_pitch) << 3
540 * | (A & 0b111000000000) >> 9
541 * X' = (tile_num % tile_pitch) << 9
542 * | (A & 0b111111111)
544 * (In all tiling formulas, cpp is the number of bytes occupied by a single
545 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
546 * to fill the width of the surface, and qpitch is the spacing (in rows)
547 * between array slices).
549 * For Y tiling, tile() combines together the low-order bits of the X and Y
550 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
551 * bytes wide and 32 rows high:
553 * tile(y_tiled, X, Y, S) = A
554 * where A = tile_num << 12 | offset
555 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
556 * offset = (X' & 0b1110000) << 5
557 * | (Y' & 0b11111) << 4
560 * Y' = Y + S * qpitch
561 * detile(y_tiled, A) = (X, Y, S)
565 * Y' = (tile_num / tile_pitch) << 5
566 * | (A & 0b111110000) >> 4
567 * X' = (tile_num % tile_pitch) << 7
568 * | (A & 0b111000000000) >> 5
571 * For W tiling, tile() combines together the low-order bits of the X and Y
572 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
573 * bytes wide and 64 rows high (note that W tiling is only used for stencil
574 * buffers, which always have cpp = 1 and S=0):
576 * tile(w_tiled, X, Y, S) = A
577 * where A = tile_num << 12 | offset
578 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
579 * offset = (X' & 0b111000) << 6
580 * | (Y' & 0b111100) << 3
581 * | (X' & 0b100) << 2
587 * Y' = Y + S * qpitch
588 * detile(w_tiled, A) = (X, Y, S)
589 * where X = X' / cpp = X'
590 * Y = Y' % qpitch = Y'
592 * Y' = (tile_num / tile_pitch) << 6
593 * | (A & 0b111100000) >> 3
594 * | (A & 0b1000) >> 2
596 * X' = (tile_num % tile_pitch) << 6
597 * | (A & 0b111000000000) >> 6
598 * | (A & 0b10000) >> 2
602 * Finally, for a non-tiled surface, tile() simply combines together the X and
603 * Y coordinates in the natural way:
605 * tile(untiled, X, Y, S) = A
606 * where A = Y * pitch + X'
608 * Y' = Y + S * qpitch
609 * detile(untiled, A) = (X, Y, S)
616 * (In these formulas, pitch is the number of bytes occupied by a single row
619 class brw_blorp_blit_program
622 brw_blorp_blit_program(struct brw_context
*brw
,
623 const brw_blorp_blit_prog_key
*key
);
624 ~brw_blorp_blit_program();
626 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
628 brw_blorp_prog_data prog_data
;
632 void alloc_push_const_regs(int base_reg
);
633 void compute_frag_coords();
634 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
635 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
636 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
637 void kill_if_outside_dst_rect();
638 void translate_dst_to_src();
639 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
640 struct brw_reg clampX0
, struct brw_reg clampY0
,
641 struct brw_reg clampX1
, struct brw_reg clampY1
);
642 void single_to_blend();
643 void manual_blend_average(unsigned num_samples
);
644 void manual_blend_bilinear(unsigned num_samples
);
645 void sample(struct brw_reg dst
);
646 void texel_fetch(struct brw_reg dst
);
648 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
649 const sampler_message_arg
*args
, int num_args
);
650 void render_target_write();
653 * Base-2 logarithm of the maximum number of samples that can be blended.
655 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
658 struct brw_context
*brw
;
659 const brw_blorp_blit_prog_key
*key
;
660 struct brw_compile func
;
662 /* Thread dispatch header */
665 /* Pixel X/Y coordinates (always in R1). */
669 struct brw_reg dst_x0
;
670 struct brw_reg dst_x1
;
671 struct brw_reg dst_y0
;
672 struct brw_reg dst_y1
;
673 /* Top right coordinates of the rectangular grid used for scaled blitting */
674 struct brw_reg rect_grid_x1
;
675 struct brw_reg rect_grid_y1
;
677 struct brw_reg multiplier
;
678 struct brw_reg offset
;
679 } x_transform
, y_transform
;
681 /* Data read from texture (4 vec16's per array element) */
682 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
684 /* Auxiliary storage for the contents of the MCS surface.
686 * Since the sampler always returns 8 registers worth of data, this is 8
687 * registers wide, even though we only use the first 2 registers of it.
689 struct brw_reg mcs_data
;
691 /* X coordinates. We have two of them so that we can perform coordinate
692 * transformations easily.
694 struct brw_reg x_coords
[2];
696 /* Y coordinates. We have two of them so that we can perform coordinate
697 * transformations easily.
699 struct brw_reg y_coords
[2];
701 /* X, Y coordinates of the pixel from which we need to fetch the specific
702 * sample. These are used for multisample scaled blitting.
704 struct brw_reg x_sample_coords
;
705 struct brw_reg y_sample_coords
;
707 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
708 struct brw_reg x_frac
;
709 struct brw_reg y_frac
;
711 /* Which element of x_coords and y_coords is currently in use.
715 /* True if, at the point in the program currently being compiled, the
716 * sample index is known to be zero.
720 /* Register storing the sample index when s_is_zero is false. */
721 struct brw_reg sample_index
;
727 /* MRF used for sampling and render target writes */
731 brw_blorp_blit_program::brw_blorp_blit_program(
732 struct brw_context
*brw
,
733 const brw_blorp_blit_prog_key
*key
)
734 : mem_ctx(ralloc_context(NULL
)),
738 brw_init_compile(brw
, &func
, mem_ctx
);
741 brw_blorp_blit_program::~brw_blorp_blit_program()
743 ralloc_free(mem_ctx
);
747 brw_blorp_blit_program::compile(struct brw_context
*brw
,
748 GLuint
*program_size
)
751 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
752 /* If the destination image is W tiled and multisampled, then the thread
753 * must be dispatched once per sample, not once per pixel. This is
754 * necessary because after conversion between W and Y tiling, there's no
755 * guarantee that all samples corresponding to a single pixel will still
758 assert(key
->persample_msaa_dispatch
);
762 /* We are blending, which means we won't have an opportunity to
763 * translate the tiling and sample count for the texture surface. So
764 * the surface state for the texture must be configured with the correct
765 * tiling and sample count.
767 assert(!key
->src_tiled_w
);
768 assert(key
->tex_samples
== key
->src_samples
);
769 assert(key
->tex_layout
== key
->src_layout
);
770 assert(key
->tex_samples
> 0);
773 if (key
->persample_msaa_dispatch
) {
774 /* It only makes sense to do persample dispatch if the render target is
775 * configured as multisampled.
777 assert(key
->rt_samples
> 0);
780 /* Make sure layout is consistent with sample count */
781 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
782 (key
->tex_samples
== 0));
783 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
784 (key
->rt_samples
== 0));
785 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
786 (key
->src_samples
== 0));
787 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
788 (key
->dst_samples
== 0));
790 /* Set up prog_data */
791 memset(&prog_data
, 0, sizeof(prog_data
));
792 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
794 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
797 compute_frag_coords();
799 /* Render target and texture hardware don't support W tiling. */
800 const bool rt_tiled_w
= false;
801 const bool tex_tiled_w
= false;
803 /* The address that data will be written to is determined by the
804 * coordinates supplied to the WM thread and the tiling and sample count of
805 * the render target, according to the formula:
807 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
809 * If the actual tiling and sample count of the destination surface are not
810 * the same as the configuration of the render target, then these
811 * coordinates are wrong and we have to adjust them to compensate for the
814 if (rt_tiled_w
!= key
->dst_tiled_w
||
815 key
->rt_samples
!= key
->dst_samples
||
816 key
->rt_layout
!= key
->dst_layout
) {
817 encode_msaa(key
->rt_samples
, key
->rt_layout
);
818 /* Now (X, Y, S) = detile(rt_tiling, offset) */
819 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
820 /* Now (X, Y, S) = detile(dst_tiling, offset) */
821 decode_msaa(key
->dst_samples
, key
->dst_layout
);
824 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
826 * That is: X, Y and S now contain the true coordinates and sample index of
827 * the data that the WM thread should output.
829 * If we need to kill pixels that are outside the destination rectangle,
830 * now is the time to do it.
834 kill_if_outside_dst_rect();
836 /* Next, apply a translation to obtain coordinates in the source image. */
837 translate_dst_to_src();
839 /* If the source image is not multisampled, then we want to fetch sample
840 * number 0, because that's the only sample there is.
842 if (key
->src_samples
== 0)
845 /* X, Y, and S are now the coordinates of the pixel in the source image
846 * that we want to texture from. Exception: if we are blending, then S is
847 * irrelevant, because we are going to fetch all samples.
849 if (key
->blend
&& !key
->blit_scaled
) {
851 /* Gen6 hardware an automatically blend using the SAMPLE message */
853 sample(texture_data
[0]);
855 /* Gen7+ hardware doesn't automaticaly blend. */
856 manual_blend_average(key
->src_samples
);
858 } else if(key
->blend
&& key
->blit_scaled
) {
859 manual_blend_bilinear(key
->src_samples
);
861 /* We aren't blending, which means we just want to fetch a single sample
862 * from the source surface. The address that we want to fetch from is
863 * related to the X, Y and S values according to the formula:
865 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
867 * If the actual tiling and sample count of the source surface are not
868 * the same as the configuration of the texture, then we need to adjust
869 * the coordinates to compensate for the difference.
871 if ((tex_tiled_w
!= key
->src_tiled_w
||
872 key
->tex_samples
!= key
->src_samples
||
873 key
->tex_layout
!= key
->src_layout
) &&
874 !key
->bilinear_filter
) {
875 encode_msaa(key
->src_samples
, key
->src_layout
);
876 /* Now (X, Y, S) = detile(src_tiling, offset) */
877 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
878 /* Now (X, Y, S) = detile(tex_tiling, offset) */
879 decode_msaa(key
->tex_samples
, key
->tex_layout
);
882 if (key
->bilinear_filter
) {
883 sample(texture_data
[0]);
886 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
888 * In other words: X, Y, and S now contain values which, when passed to
889 * the texturing unit, will cause data to be read from the correct
890 * memory location. So we can fetch the texel now.
892 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
894 texel_fetch(texture_data
[0]);
898 /* Finally, write the fetched (or blended) value to the render target and
899 * terminate the thread.
901 render_target_write();
903 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
904 printf("Native code for BLORP blit:\n");
905 brw_dump_compile(&func
, stdout
, 0, func
.next_insn_offset
);
908 return brw_get_program(&func
, program_size
);
912 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
914 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
915 #define ALLOC_REG(name, type) \
917 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
918 base_reg + CONST_LOC(name) / 32, \
919 (CONST_LOC(name) % 32) / 4), type)
921 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
922 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
923 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
924 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
925 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
926 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
927 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
928 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
929 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
930 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
936 brw_blorp_blit_program::alloc_regs()
939 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
940 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
941 prog_data
.first_curbe_grf
= reg
;
942 alloc_push_const_regs(reg
);
943 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
944 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
945 this->texture_data
[i
] =
946 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
950 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
952 for (int i
= 0; i
< 2; ++i
) {
954 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
957 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
961 if (key
->blit_scaled
&& key
->blend
) {
962 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
964 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
966 this->x_frac
= brw_vec8_grf(reg
, 0);
968 this->y_frac
= brw_vec8_grf(reg
, 0);
972 this->xy_coord_index
= 0;
974 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
976 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
978 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
981 /* Make sure we didn't run out of registers */
982 assert(reg
<= GEN7_MRF_HACK_START
);
985 this->base_mrf
= mrf
;
988 /* In the code that follows, X and Y can be used to quickly refer to the
989 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
990 * prime") to the inactive elements.
992 * S can be used to quickly refer to sample_index.
994 #define X x_coords[xy_coord_index]
995 #define Y y_coords[xy_coord_index]
996 #define Xp x_coords[!xy_coord_index]
997 #define Yp y_coords[!xy_coord_index]
998 #define S sample_index
1000 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
1001 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
1003 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
1006 * Emit code to compute the X and Y coordinates of the pixels being rendered
1007 * by this WM invocation.
1009 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1010 * related to the address offset where outputs will be written by the formula:
1012 * (X, Y, S) = decode_msaa(detile(offset)).
1014 * (See brw_blorp_blit_program).
1017 brw_blorp_blit_program::compute_frag_coords()
1019 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1020 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1021 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1022 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1024 * Pixels within a subspan are laid out in this arrangement:
1028 * So, to compute the coordinates of each pixel, we need to read every 2nd
1029 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1030 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1031 * In other words, the data we want to access is R1.4<2;4,0>UW.
1033 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1034 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1036 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1037 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1039 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1040 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1041 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1044 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1045 * pixels n+2 and n+3 are in the bottom half of the subspan.
1047 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1048 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1050 /* Move the coordinates to UD registers. */
1051 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1052 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1055 if (key
->persample_msaa_dispatch
) {
1056 switch (key
->rt_samples
) {
1058 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1059 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1060 * represent sample 1, and so on.
1062 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1063 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1064 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1065 * then copy from it using vstride=1, width=4, hstride=0.
1067 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1068 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1069 /* Move to UD sample_index register. */
1070 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1071 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1075 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1076 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1077 * subspan 1 will represent sample 1, and so on. We can find the
1078 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1079 * Index") and multiplying by two (since samples are always delivered
1080 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1083 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1084 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1085 * variable with the sequence (0, 1, 2, 3), and then reading from it
1086 * using vstride=1, width=4, hstride=0.
1088 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1089 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1090 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1091 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1092 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1093 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1094 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1095 stride(t2_uw1
, 1, 4, 0));
1096 brw_ADD(&func
, offset(S
, 1),
1097 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1098 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1102 assert(!"Unrecognized sample count in "
1103 "brw_blorp_blit_program::compute_frag_coords()");
1108 /* Either the destination surface is single-sampled, or the WM will be
1109 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1110 * per pixel). In either case, it's not meaningful to compute a sample
1111 * value. Just set it to 0.
1118 * Emit code to compensate for the difference between Y and W tiling.
1120 * This code modifies the X and Y coordinates according to the formula:
1122 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1124 * (See brw_blorp_blit_program).
1126 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1127 * are booleans where true represents W tiling and false represents Y tiling.
1130 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1132 if (old_tiled_w
== new_tiled_w
)
1135 /* In the code that follows, we can safely assume that S = 0, because W
1136 * tiling formats always use IMS layout.
1140 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1142 /* Given X and Y coordinates that describe an address using Y tiling,
1143 * translate to the X and Y coordinates that describe the same address
1146 * If we break down the low order bits of X and Y, using a
1147 * single letter to represent each low-order bit:
1149 * X = A << 7 | 0bBCDEFGH
1150 * Y = J << 5 | 0bKLMNP (1)
1152 * Then we can apply the Y tiling formula to see the memory offset being
1155 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1157 * If we apply the W detiling formula to this memory location, that the
1158 * corresponding X' and Y' coordinates are:
1160 * X' = A << 6 | 0bBCDPFH (3)
1161 * Y' = J << 6 | 0bKLMNEG
1163 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1164 * we need to make the following computation:
1166 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1167 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1169 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1170 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1171 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1172 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1173 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1174 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1175 brw_OR(&func
, Xp
, t1
, t2
);
1176 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1177 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1178 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1179 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1180 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1181 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1182 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1183 brw_OR(&func
, Yp
, t1
, t2
);
1186 /* Applying the same logic as above, but in reverse, we obtain the
1189 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1190 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1192 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1193 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1194 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1195 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1196 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1197 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1198 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1199 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1201 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1202 brw_OR(&func
, Xp
, t1
, t2
);
1203 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1204 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1205 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1206 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1207 brw_OR(&func
, Yp
, t1
, t2
);
1210 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1214 * Emit code to compensate for the difference between MSAA and non-MSAA
1217 * This code modifies the X and Y coordinates according to the formula:
1219 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1221 * (See brw_blorp_blit_program).
1224 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1225 intel_msaa_layout layout
)
1227 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1229 case INTEL_MSAA_LAYOUT_NONE
:
1230 /* No translation necessary, and S should already be zero. */
1233 case INTEL_MSAA_LAYOUT_CMS
:
1234 /* We can't compensate for compressed layout since at this point in the
1235 * program we haven't read from the MCS buffer.
1237 assert(!"Bad layout in encode_msaa");
1239 case INTEL_MSAA_LAYOUT_UMS
:
1240 /* No translation necessary. */
1242 case INTEL_MSAA_LAYOUT_IMS
:
1243 switch (num_samples
) {
1245 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1246 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1247 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1249 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1251 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1252 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1254 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1256 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1257 brw_OR(&func
, Xp
, t1
, t2
);
1258 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1259 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1261 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1262 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1264 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1265 brw_OR(&func
, Yp
, t1
, t2
);
1268 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1269 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1271 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1273 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1274 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1276 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1277 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1278 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1279 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1280 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1283 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1284 brw_OR(&func
, Xp
, t1
, t2
);
1285 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1286 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1288 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1289 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1291 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1292 brw_OR(&func
, Yp
, t1
, t2
);
1299 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1303 * Emit code to compensate for the difference between MSAA and non-MSAA
1306 * This code modifies the X and Y coordinates according to the formula:
1308 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1310 * (See brw_blorp_blit_program).
1313 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1314 intel_msaa_layout layout
)
1316 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1318 case INTEL_MSAA_LAYOUT_NONE
:
1319 /* No translation necessary, and S should already be zero. */
1322 case INTEL_MSAA_LAYOUT_CMS
:
1323 /* We can't compensate for compressed layout since at this point in the
1324 * program we don't have access to the MCS buffer.
1326 assert(!"Bad layout in encode_msaa");
1328 case INTEL_MSAA_LAYOUT_UMS
:
1329 /* No translation necessary. */
1331 case INTEL_MSAA_LAYOUT_IMS
:
1333 switch (num_samples
) {
1335 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1336 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1337 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1338 * S = (Y & 0b10) | (X & 0b10) >> 1
1340 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1341 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1342 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1343 brw_OR(&func
, Xp
, t1
, t2
);
1344 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1345 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1346 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1347 brw_OR(&func
, Yp
, t1
, t2
);
1348 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1349 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1350 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1351 brw_OR(&func
, S
, t1
, t2
);
1354 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1355 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1356 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1357 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1359 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1360 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1361 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1362 brw_OR(&func
, Xp
, t1
, t2
);
1363 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1364 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1365 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1366 brw_OR(&func
, Yp
, t1
, t2
);
1367 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1368 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1369 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1370 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1371 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1372 brw_OR(&func
, S
, t1
, t2
);
1379 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1383 * Emit code that kills pixels whose X and Y coordinates are outside the
1384 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1388 brw_blorp_blit_program::kill_if_outside_dst_rect()
1390 struct brw_reg f0
= brw_flag_reg(0, 0);
1391 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1392 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1394 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1395 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1396 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1397 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1399 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1400 brw_push_insn_state(&func
);
1401 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1402 brw_AND(&func
, g1
, f0
, g1
);
1403 brw_pop_insn_state(&func
);
1407 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1411 brw_blorp_blit_program::translate_dst_to_src()
1413 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1414 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1415 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1416 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1418 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1419 /* Move the UD coordinates to float registers. */
1420 brw_MOV(&func
, Xp_f
, X
);
1421 brw_MOV(&func
, Yp_f
, Y
);
1422 /* Scale and offset */
1423 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1424 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1425 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1426 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1427 if (key
->blit_scaled
&& key
->blend
) {
1428 /* Translate coordinates to lay out the samples in a rectangular grid
1429 * roughly corresponding to sample locations.
1431 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1432 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1433 /* Adjust coordinates so that integers represent pixel centers rather
1436 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1437 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1439 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1440 * texels on texture edges.
1442 clamp_tex_coords(X_f
, Y_f
,
1443 brw_imm_f(0.0), brw_imm_f(0.0),
1444 rect_grid_x1
, rect_grid_y1
);
1446 /* Store the fractional parts to be used as bilinear interpolation
1449 brw_FRC(&func
, x_frac
, X_f
);
1450 brw_FRC(&func
, y_frac
, Y_f
);
1452 /* Round the float coordinates down to nearest integer */
1453 brw_RNDD(&func
, Xp_f
, X_f
);
1454 brw_RNDD(&func
, Yp_f
, Y_f
);
1455 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1456 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1458 } else if (!key
->bilinear_filter
) {
1459 /* Round the float coordinates down to nearest integer by moving to
1462 brw_MOV(&func
, Xp
, X_f
);
1463 brw_MOV(&func
, Yp
, Y_f
);
1466 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1470 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1471 struct brw_reg regY
,
1472 struct brw_reg clampX0
,
1473 struct brw_reg clampY0
,
1474 struct brw_reg clampX1
,
1475 struct brw_reg clampY1
)
1477 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regX
, clampX0
);
1478 brw_MOV(&func
, regX
, clampX0
);
1479 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1481 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regX
, clampX1
);
1482 brw_MOV(&func
, regX
, clampX1
);
1483 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1485 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regY
, clampY0
);
1486 brw_MOV(&func
, regY
, clampY0
);
1487 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1489 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regY
, clampY1
);
1490 brw_MOV(&func
, regY
, clampY1
);
1491 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1495 * Emit code to transform the X and Y coordinates as needed for blending
1496 * together the different samples in an MSAA texture.
1499 brw_blorp_blit_program::single_to_blend()
1501 /* When looking up samples in an MSAA texture using the SAMPLE message,
1502 * Gen6 requires the texture coordinates to be odd integers (so that they
1503 * correspond to the center of a 2x2 block representing the four samples
1504 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1505 * each by 2 and then add 1.
1507 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1508 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1509 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1510 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1511 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1512 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1518 * Count the number of trailing 1 bits in the given value. For example:
1520 * count_trailing_one_bits(0) == 0
1521 * count_trailing_one_bits(7) == 3
1522 * count_trailing_one_bits(11) == 2
1524 inline int count_trailing_one_bits(unsigned value
)
1526 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1527 return __builtin_ctz(~value
);
1529 return _mesa_bitcount(value
& ~(value
+ 1));
1535 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1537 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1540 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1542 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1544 * This ensures that when all samples have the same value, no numerical
1545 * precision is lost, since each addition operation always adds two equal
1546 * values, and summing two equal floating point values does not lose
1549 * We perform this computation by treating the texture_data array as a
1550 * stack and performing the following operations:
1552 * - push sample 0 onto stack
1553 * - push sample 1 onto stack
1554 * - add top two stack entries
1555 * - push sample 2 onto stack
1556 * - push sample 3 onto stack
1557 * - add top two stack entries
1558 * - add top two stack entries
1559 * - divide top stack entry by 4
1561 * Note that after pushing sample i onto the stack, the number of add
1562 * operations we do is equal to the number of trailing 1 bits in i. This
1563 * works provided the total number of samples is a power of two, which it
1564 * always is for i965.
1566 * For integer formats, we replace the add operations with average
1567 * operations and skip the final division.
1569 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1573 brw_op2_ptr combine_op
=
1574 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1575 unsigned stack_depth
= 0;
1576 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1577 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1579 /* Push sample i onto the stack */
1580 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1585 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1587 texel_fetch(texture_data
[stack_depth
++]);
1589 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1590 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1591 * suggests an optimization:
1593 * "A simple optimization with probable large return in
1594 * performance is to compare the MCS value to zero (indicating
1595 * all samples are on sample slice 0), and sample only from
1596 * sample slice 0 using ld2dss if MCS is zero."
1598 * Note that in the case where the MCS value is zero, sampling from
1599 * sample slice 0 using ld2dss and sampling from sample 0 using
1600 * ld2dms are equivalent (since all samples are on sample slice 0).
1601 * Since we have already sampled from sample 0, all we need to do is
1602 * skip the remaining fetches and averaging if MCS is zero.
1604 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1605 mcs_data
, brw_imm_ud(0));
1606 brw_IF(&func
, BRW_EXECUTE_16
);
1609 /* Do count_trailing_one_bits(i) times */
1610 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1611 assert(stack_depth
>= 2);
1614 /* TODO: should use a smaller loop bound for non_RGBA formats */
1615 for (int k
= 0; k
< 4; ++k
) {
1616 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1617 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1618 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1623 /* We should have just 1 sample on the stack now. */
1624 assert(stack_depth
== 1);
1626 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1627 /* Scale the result down by a factor of num_samples */
1628 /* TODO: should use a smaller loop bound for non-RGBA formats */
1629 for (int j
= 0; j
< 4; ++j
) {
1630 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1631 offset(vec8(texture_data
[0]), 2*j
),
1632 brw_imm_f(1.0/num_samples
));
1636 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1641 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1643 /* We do this computation by performing the following operations:
1645 * In case of 4x, 8x MSAA:
1646 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1647 * which are later used for interpolation
1648 * - linearly interpolate samples a and b in X
1649 * - linearly interpolate samples c and d in X
1650 * - linearly interpolate the results of last two operations in Y
1652 * result = lrp(lrp(a + b) + lrp(c + d))
1654 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1655 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1656 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1657 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1659 for (unsigned i
= 0; i
< 4; ++i
) {
1660 assert(i
< ARRAY_SIZE(texture_data
));
1663 /* Compute pixel coordinates */
1664 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1665 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1666 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1667 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1668 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1669 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1671 /* The MCS value we fetch has to match up with the pixel that we're
1672 * sampling from. Since we sample from different pixels in each
1673 * iteration of this "for" loop, the call to mcs_fetch() should be
1674 * here inside the loop after computing the pixel coordinates.
1676 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1679 /* Compute sample index and map the sample index to a sample number.
1680 * Sample index layout shows the numbering of slots in a rectangular
1681 * grid of samples with in a pixel. Sample number layout shows the
1682 * rectangular grid of samples roughly corresponding to the real sample
1683 * locations with in a pixel.
1684 * In case of 4x MSAA, layout of sample indices matches the layout of
1692 * In case of 8x MSAA the two layouts don't match.
1693 * sample index layout : --------- sample number layout : ---------
1694 * | 0 | 1 | | 5 | 2 |
1695 * --------- ---------
1696 * | 2 | 3 | | 4 | 6 |
1697 * --------- ---------
1698 * | 4 | 5 | | 0 | 3 |
1699 * --------- ---------
1700 * | 6 | 7 | | 7 | 1 |
1701 * --------- ---------
1703 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1704 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1705 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1706 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1707 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1708 brw_MOV(&func
, vec16(S
), t1_f
);
1710 if (num_samples
== 8) {
1711 /* Map the sample index to a sample number */
1712 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1714 brw_IF(&func
, BRW_EXECUTE_16
);
1716 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1717 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1719 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1720 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1721 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1723 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1724 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1725 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1727 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1728 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1732 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1733 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1735 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1736 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1737 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1739 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1740 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1741 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1743 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1744 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1747 brw_MOV(&func
, vec16(S
), t2
);
1749 texel_fetch(texture_data
[i
]);
1752 #define SAMPLE(x, y) offset(texture_data[x], y)
1753 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1754 for (int index
= 3; index
> 0; ) {
1755 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1756 * Counter value of 8 in 'for' loop below is used to interpolate all
1757 * the color components.
1759 for (int k
= 0; k
< 8; ++k
)
1761 vec8(SAMPLE(index
- 1, k
)),
1762 offset(x_frac
, k
& 1),
1764 SAMPLE(index
- 1, k
));
1767 for (int k
= 0; k
< 8; ++k
)
1770 offset(y_frac
, k
& 1),
1772 vec8(SAMPLE(0, k
)));
1773 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1778 * Emit code to look up a value in the texture using the SAMPLE message (which
1779 * does blending of MSAA surfaces).
1782 brw_blorp_blit_program::sample(struct brw_reg dst
)
1784 static const sampler_message_arg args
[2] = {
1785 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1786 SAMPLER_MESSAGE_ARG_V_FLOAT
1789 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
,
1794 * Emit code to look up a value in the texture using the SAMPLE_LD message
1795 * (which does a simple texel fetch).
1798 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1800 static const sampler_message_arg gen6_args
[5] = {
1801 SAMPLER_MESSAGE_ARG_U_INT
,
1802 SAMPLER_MESSAGE_ARG_V_INT
,
1803 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1804 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1805 SAMPLER_MESSAGE_ARG_SI_INT
1807 static const sampler_message_arg gen7_ld_args
[3] = {
1808 SAMPLER_MESSAGE_ARG_U_INT
,
1809 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1810 SAMPLER_MESSAGE_ARG_V_INT
1812 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1813 SAMPLER_MESSAGE_ARG_SI_INT
,
1814 SAMPLER_MESSAGE_ARG_U_INT
,
1815 SAMPLER_MESSAGE_ARG_V_INT
1817 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1818 SAMPLER_MESSAGE_ARG_SI_INT
,
1819 SAMPLER_MESSAGE_ARG_MCS_INT
,
1820 SAMPLER_MESSAGE_ARG_U_INT
,
1821 SAMPLER_MESSAGE_ARG_V_INT
1826 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1830 switch (key
->tex_layout
) {
1831 case INTEL_MSAA_LAYOUT_IMS
:
1832 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1835 * If this field is MSFMT_DEPTH_STENCIL
1836 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1837 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1839 * So fall through to emit the same message as we use for
1840 * INTEL_MSAA_LAYOUT_CMS.
1842 case INTEL_MSAA_LAYOUT_CMS
:
1843 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1844 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1846 case INTEL_MSAA_LAYOUT_UMS
:
1847 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1848 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1850 case INTEL_MSAA_LAYOUT_NONE
:
1852 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1853 ARRAY_SIZE(gen7_ld_args
));
1858 assert(!"Should not get here.");
1864 brw_blorp_blit_program::mcs_fetch()
1866 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1867 SAMPLER_MESSAGE_ARG_U_INT
,
1868 SAMPLER_MESSAGE_ARG_V_INT
1870 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1871 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1875 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1877 const sampler_message_arg
*args
,
1880 struct brw_reg mrf
=
1881 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1882 for (int arg
= 0; arg
< num_args
; ++arg
) {
1883 switch (args
[arg
]) {
1884 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1885 if (key
->bilinear_filter
)
1886 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1887 retype(X
, BRW_REGISTER_TYPE_F
));
1889 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1891 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1892 if (key
->bilinear_filter
)
1893 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1894 retype(Y
, BRW_REGISTER_TYPE_F
));
1896 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1898 case SAMPLER_MESSAGE_ARG_U_INT
:
1899 brw_MOV(&func
, mrf
, X
);
1901 case SAMPLER_MESSAGE_ARG_V_INT
:
1902 brw_MOV(&func
, mrf
, Y
);
1904 case SAMPLER_MESSAGE_ARG_SI_INT
:
1905 /* Note: on Gen7, this code may be reached with s_is_zero==true
1906 * because in Gen7's ld2dss message, the sample index is the first
1907 * argument. When this happens, we need to move a 0 into the
1908 * appropriate message register.
1911 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1913 brw_MOV(&func
, mrf
, S
);
1915 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1916 switch (key
->tex_layout
) {
1917 case INTEL_MSAA_LAYOUT_CMS
:
1918 brw_MOV(&func
, mrf
, mcs_data
);
1920 case INTEL_MSAA_LAYOUT_IMS
:
1921 /* When sampling from an IMS surface, MCS data is not relevant,
1922 * and the hardware ignores it. So don't bother populating it.
1926 /* We shouldn't be trying to send MCS data with any other
1929 assert (!"Unsupported layout for MCS data");
1933 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1934 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1941 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1942 base_mrf
/* msg_reg_nr */,
1943 brw_message_reg(base_mrf
) /* src0 */,
1944 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1947 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1948 mrf
.nr
- base_mrf
/* msg_length */,
1949 0 /* header_present */,
1950 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1951 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1959 #undef SWAP_XY_AND_XPYP
1962 brw_blorp_blit_program::render_target_write()
1964 struct brw_reg mrf_rt_write
=
1965 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1968 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1969 * so that the render target knows which pixels we killed.
1971 bool use_header
= key
->use_kill
;
1973 /* Copy R0/1 to MRF */
1974 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1975 retype(R0
, BRW_REGISTER_TYPE_UD
));
1979 /* Copy texture data to MRFs */
1980 for (int i
= 0; i
< 4; ++i
) {
1981 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1982 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1983 offset(vec8(texture_data
[0]), 2*i
));
1987 /* Now write to the render target and terminate the thread */
1989 16 /* dispatch_width */,
1990 base_mrf
/* msg_reg_nr */,
1991 mrf_rt_write
/* src0 */,
1992 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1993 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1994 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1995 0 /* response_length */,
2002 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
2003 GLfloat dst0
, GLfloat dst1
,
2006 float scale
= (src1
- src0
) / (dst1
- dst0
);
2008 /* When not mirroring a coordinate (say, X), we need:
2009 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
2011 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
2013 * blorp program uses "round toward zero" to convert the
2014 * transformed floating point coordinates to integer coordinates,
2015 * whereas the behaviour we actually want is "round to nearest",
2016 * so 0.5 provides the necessary correction.
2019 offset
= src0
+ (-dst0
+ 0.5) * scale
;
2021 /* When mirroring X we need:
2022 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2024 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2026 multiplier
= -scale
;
2027 offset
= src0
+ (dst1
- 0.5) * scale
;
2033 * Determine which MSAA layout the GPU pipeline should be configured for,
2034 * based on the chip generation, the number of samples, and the true layout of
2035 * the image in memory.
2037 inline intel_msaa_layout
2038 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2039 intel_msaa_layout true_layout
)
2041 if (num_samples
<= 1) {
2042 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2043 * format buffers, by transforming coordinates appropriately.
2045 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2046 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2047 return INTEL_MSAA_LAYOUT_NONE
;
2049 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2052 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2053 if (brw
->gen
== 6) {
2054 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2061 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2062 struct intel_mipmap_tree
*src_mt
,
2063 unsigned src_level
, unsigned src_layer
,
2064 struct intel_mipmap_tree
*dst_mt
,
2065 unsigned dst_level
, unsigned dst_layer
,
2066 GLfloat src_x0
, GLfloat src_y0
,
2067 GLfloat src_x1
, GLfloat src_y1
,
2068 GLfloat dst_x0
, GLfloat dst_y0
,
2069 GLfloat dst_x1
, GLfloat dst_y1
,
2071 bool mirror_x
, bool mirror_y
)
2073 struct gl_context
*ctx
= &brw
->ctx
;
2074 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2076 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
2077 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
2079 /* Even though we do multisample resolves at the time of the blit, OpenGL
2080 * specification defines them as if they happen at the time of rendering,
2081 * which means that the type of averaging we do during the resolve should
2082 * only depend on the source format; the destination format should be
2083 * ignored. But, specification doesn't seem to be strict about it.
2085 * It has been observed that mulitisample resolves produce slightly better
2086 * looking images when averaging is done using destination format. NVIDIA's
2087 * proprietary OpenGL driver also follow this approach. So, we choose to
2088 * follow it in our driver.
2090 * When multisampling, if the source and destination formats are equal
2091 * (aside from the color space), we choose to blit in sRGB space to get
2092 * this higher quality image.
2094 if (src
.num_samples
> 1 &&
2095 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
2096 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2097 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2098 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2099 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2103 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2105 /* texture_data_type indicates the register type that should be used to
2106 * manipulate texture data.
2108 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2109 case GL_UNSIGNED_NORMALIZED
:
2110 case GL_SIGNED_NORMALIZED
:
2112 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2114 case GL_UNSIGNED_INT
:
2115 if (src_mt
->format
== MESA_FORMAT_S8
) {
2116 /* We process stencil as though it's an unsigned normalized color */
2117 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2119 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2123 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2126 assert(!"Unrecognized blorp format");
2131 /* Gen7's rendering hardware only supports the IMS layout for depth and
2132 * stencil render targets. Blorp always maps its destination surface as
2133 * a color render target (even if it's actually a depth or stencil
2134 * buffer). So if the destination is IMS, we'll have to map it as a
2135 * single-sampled texture and interleave the samples ourselves.
2137 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2138 dst
.num_samples
= 0;
2141 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2142 /* If the destination surface is a W-tiled multisampled stencil buffer
2143 * that we're mapping as Y tiled, then we need to arrange for the WM
2144 * program to run once per sample rather than once per pixel, because
2145 * the memory layout of related samples doesn't match between W and Y
2148 wm_prog_key
.persample_msaa_dispatch
= true;
2151 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2152 /* We are blitting from a multisample buffer to a multisample buffer, so
2153 * we must preserve samples within a pixel. This means we have to
2154 * arrange for the WM program to run once per sample rather than once
2157 wm_prog_key
.persample_msaa_dispatch
= true;
2160 /* Scaled blitting or not. */
2161 wm_prog_key
.blit_scaled
=
2162 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2163 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2165 /* Scaling factors used for bilinear filtering in multisample scaled
2168 wm_prog_key
.x_scale
= 2.0;
2169 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2171 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2172 wm_prog_key
.bilinear_filter
= true;
2174 /* The render path must be configured to use the same number of samples as
2175 * the destination buffer.
2177 num_samples
= dst
.num_samples
;
2179 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2180 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2181 base_format
!= GL_STENCIL_INDEX
&&
2182 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2183 /* We are downsampling a color buffer, so blend. */
2184 wm_prog_key
.blend
= true;
2187 /* src_samples and dst_samples are the true sample counts */
2188 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2189 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2191 /* tex_samples and rt_samples are the sample counts that are set up in
2194 wm_prog_key
.tex_samples
= src
.num_samples
;
2195 wm_prog_key
.rt_samples
= dst
.num_samples
;
2197 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2198 * use to access the source and destination surfaces.
2200 wm_prog_key
.tex_layout
=
2201 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2202 wm_prog_key
.rt_layout
=
2203 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2205 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2208 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2209 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2211 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2212 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2213 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2214 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2215 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2216 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2217 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2218 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2220 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2221 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2223 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2224 /* We must expand the rectangle we send through the rendering pipeline,
2225 * to account for the fact that we are mapping the destination region as
2226 * single-sampled when it is in fact multisampled. We must also align
2227 * it to a multiple of the multisampling pattern, because the
2228 * differences between multisampled and single-sampled surface formats
2229 * will mean that pixels are scrambled within the multisampling pattern.
2230 * TODO: what if this makes the coordinates too large?
2232 * Note: this only works if the destination surface uses the IMS layout.
2233 * If it's UMS, then we have no choice but to set up the rendering
2234 * pipeline as multisampled.
2236 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2237 switch (dst_mt
->num_samples
) {
2239 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2240 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2241 x1
= ALIGN(x1
* 2, 4);
2242 y1
= ALIGN(y1
* 2, 4);
2245 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2246 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2247 x1
= ALIGN(x1
* 4, 8);
2248 y1
= ALIGN(y1
* 2, 4);
2251 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2254 wm_prog_key
.use_kill
= true;
2257 if (dst
.map_stencil_as_y_tiled
) {
2258 /* We must modify the rectangle we send through the rendering pipeline
2259 * (and the size and x/y offset of the destination surface), to account
2260 * for the fact that we are mapping it as Y-tiled when it is in fact
2263 * Both Y tiling and W tiling can be understood as organizations of
2264 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2265 * is different, but the layout of the 32-byte sub-tiles within the 4k
2266 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2267 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2268 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2270 * Therefore, to account for the layout differences within the 32-byte
2271 * sub-tiles, we must expand the rectangle so the X coordinates of its
2272 * edges are multiples of 8 (the W sub-tile width), and its Y
2273 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2274 * Then we need to scale the X and Y coordinates of the rectangle to
2275 * account for the differences in aspect ratio between the Y and W
2276 * sub-tiles. We need to modify the layer width and height similarly.
2278 * A correction needs to be applied when MSAA is in use: since
2279 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2280 * we need to align the Y coordinates to multiples of 8, so that when
2281 * they are divided by two they are still multiples of 4.
2283 * Note: Since the x/y offset of the surface will be applied using the
2284 * SURFACE_STATE command packet, it will be invisible to the swizzling
2285 * code in the shader; therefore it needs to be in a multiple of the
2286 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2287 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2288 * buffer), and the miplevel alignment used for stencil buffers is 8
2289 * pixels horizontally and either 4 or 8 pixels vertically (see
2290 * intel_horizontal_texture_alignment_unit() and
2291 * intel_vertical_texture_alignment_unit()).
2293 * Note: Also, since the SURFACE_STATE command packet can only apply
2294 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2295 * vertically, it is important that the offsets will be multiples of
2296 * these sizes after they are converted into Y-tiled coordinates.
2297 * Fortunately they will be, since we know from above that the offsets
2298 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2299 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2301 * TODO: what if this makes the coordinates (or the texture size) too
2304 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2305 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2306 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2307 x1
= ALIGN(x1
, x_align
) * 2;
2308 y1
= ALIGN(y1
, y_align
) / 2;
2309 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2310 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2313 wm_prog_key
.use_kill
= true;
2316 if (src
.map_stencil_as_y_tiled
) {
2317 /* We must modify the size and x/y offset of the source surface to
2318 * account for the fact that we are mapping it as Y-tiled when it is in
2321 * See the comments above concerning x/y offset alignment for the
2322 * destination surface.
2324 * TODO: what if this makes the texture size too large?
2326 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2327 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2328 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2335 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2336 brw_blorp_prog_data
**prog_data
) const
2338 uint32_t prog_offset
= 0;
2339 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2340 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2341 &prog_offset
, prog_data
)) {
2342 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2343 GLuint program_size
;
2344 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2345 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2346 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2347 program
, program_size
,
2348 &prog
.prog_data
, sizeof(prog
.prog_data
),
2349 &prog_offset
, prog_data
);