2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
39 * Helper function for handling mirror image blits.
41 * If coord0 > coord1, swap them and invert the "mirror" boolean.
44 fixup_mirroring(bool &mirror
, GLint
&coord0
, GLint
&coord1
)
46 if (coord0
> coord1
) {
56 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
57 * destination coordinates.
59 * Return true if there is still blitting to do, false if all pixels got
60 * rejected by the clip and/or scissor.
62 * For clarity, the nomenclature of this function assumes we are clipping and
63 * scissoring the X coordinate; the exact same logic applies for Y
66 * Note: this function may also be used to account for clipping of source
67 * coordinates, by swapping the roles of src and dst.
70 clip_or_scissor(bool mirror
, GLint
&src_x0
, GLint
&src_x1
, GLint
&dst_x0
,
71 GLint
&dst_x1
, GLint fb_xmin
, GLint fb_xmax
)
73 /* If we are going to scissor everything away, stop. */
74 if (!(fb_xmin
< fb_xmax
&&
81 /* Clip the destination rectangle, and keep track of how many pixels we
82 * clipped off of the left and right sides of it.
84 GLint pixels_clipped_left
= 0;
85 GLint pixels_clipped_right
= 0;
86 if (dst_x0
< fb_xmin
) {
87 pixels_clipped_left
= fb_xmin
- dst_x0
;
90 if (fb_xmax
< dst_x1
) {
91 pixels_clipped_right
= dst_x1
- fb_xmax
;
95 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
96 * the source coordinates, we need to flip them to account for the
100 GLint tmp
= pixels_clipped_left
;
101 pixels_clipped_left
= pixels_clipped_right
;
102 pixels_clipped_right
= tmp
;
105 /* Adjust the source rectangle to remove the pixels corresponding to those
106 * that were clipped/scissored out of the destination rectangle.
108 src_x0
+= pixels_clipped_left
;
109 src_x1
-= pixels_clipped_right
;
115 static struct intel_mipmap_tree
*
116 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
118 struct intel_mipmap_tree
*mt
= irb
->mt
;
119 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
125 brw_blorp_blit_miptrees(struct intel_context
*intel
,
126 struct intel_mipmap_tree
*src_mt
,
127 unsigned src_level
, unsigned src_layer
,
128 struct intel_mipmap_tree
*dst_mt
,
129 unsigned dst_level
, unsigned dst_layer
,
130 int src_x0
, int src_y0
,
131 int dst_x0
, int dst_y0
,
132 int dst_x1
, int dst_y1
,
133 bool mirror_x
, bool mirror_y
)
135 brw_blorp_blit_params
params(brw_context(&intel
->ctx
),
136 src_mt
, src_level
, src_layer
,
137 dst_mt
, dst_level
, dst_layer
,
142 brw_blorp_exec(intel
, ¶ms
);
146 do_blorp_blit(struct intel_context
*intel
, GLbitfield buffer_bit
,
147 struct intel_renderbuffer
*src_irb
,
148 struct intel_renderbuffer
*dst_irb
,
149 GLint srcX0
, GLint srcY0
,
150 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
151 bool mirror_x
, bool mirror_y
)
153 /* Find source/dst miptrees */
154 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
155 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
157 /* Get ready to blit. This includes depth resolving the src and dst
158 * buffers if necessary.
160 intel_renderbuffer_resolve_depth(intel
, src_irb
);
161 intel_renderbuffer_resolve_depth(intel
, dst_irb
);
164 brw_blorp_blit_miptrees(intel
,
165 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
166 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
167 srcX0
, srcY0
, dstX0
, dstY0
, dstX1
, dstY1
,
170 intel_renderbuffer_set_needs_hiz_resolve(dst_irb
);
171 intel_renderbuffer_set_needs_downsample(dst_irb
);
176 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
177 struct intel_renderbuffer
*dst_irb
)
179 /* Note: don't just check gl_renderbuffer::Format, because in some cases
180 * multiple gl_formats resolve to the same native type in the miptree (for
181 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
182 * between those formats.
184 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
185 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
187 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
188 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
190 /* Normally, we require the formats to be equal. However, we also support
191 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
192 * (overriding alpha to 1.0 via blending).
194 return linear_src_format
== linear_dst_format
||
195 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
196 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
197 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
198 linear_dst_format
== MESA_FORMAT_XRGB8888
);
202 try_blorp_blit(struct intel_context
*intel
,
203 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
204 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
205 GLenum filter
, GLbitfield buffer_bit
)
207 struct gl_context
*ctx
= &intel
->ctx
;
209 /* Sync up the state of window system buffers. We need to do this before
210 * we go looking for the buffers.
212 intel_prepare_render(intel
);
214 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
215 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
217 /* Detect if the blit needs to be mirrored */
218 bool mirror_x
= false, mirror_y
= false;
219 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
220 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
221 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
222 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
224 /* Make sure width and height match */
225 if (srcX1
- srcX0
!= dstX1
- dstX0
) return false;
226 if (srcY1
- srcY0
!= dstY1
- dstY0
) return false;
228 /* If the destination rectangle needs to be clipped or scissored, do so.
230 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
231 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
232 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
233 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
234 /* Everything got clipped/scissored away, so the blit was successful. */
238 /* If the source rectangle needs to be clipped or scissored, do so. */
239 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
240 0, read_fb
->Width
) &&
241 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
242 0, read_fb
->Height
))) {
243 /* Everything got clipped/scissored away, so the blit was successful. */
247 /* Account for the fact that in the system framebuffer, the origin is at
250 if (_mesa_is_winsys_fbo(read_fb
)) {
251 GLint tmp
= read_fb
->Height
- srcY0
;
252 srcY0
= read_fb
->Height
- srcY1
;
254 mirror_y
= !mirror_y
;
256 if (_mesa_is_winsys_fbo(draw_fb
)) {
257 GLint tmp
= draw_fb
->Height
- dstY0
;
258 dstY0
= draw_fb
->Height
- dstY1
;
260 mirror_y
= !mirror_y
;
264 struct intel_renderbuffer
*src_irb
;
265 struct intel_renderbuffer
*dst_irb
;
266 switch (buffer_bit
) {
267 case GL_COLOR_BUFFER_BIT
:
268 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
269 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
270 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
271 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
274 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
275 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
277 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
278 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
281 case GL_DEPTH_BUFFER_BIT
:
283 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
285 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
286 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
288 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
289 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
291 case GL_STENCIL_BUFFER_BIT
:
293 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
295 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
296 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
298 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
299 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
309 brw_blorp_copytexsubimage(struct intel_context
*intel
,
310 struct gl_renderbuffer
*src_rb
,
311 struct gl_texture_image
*dst_image
,
312 int srcX0
, int srcY0
,
313 int dstX0
, int dstY0
,
314 int width
, int height
)
316 struct gl_context
*ctx
= &intel
->ctx
;
317 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
318 struct intel_renderbuffer
*dst_irb
;
320 /* BLORP is not supported before Gen6. */
324 /* Create a fake/wrapper renderbuffer to allow us to use do_blorp_blit(). */
325 dst_irb
= intel_create_fake_renderbuffer_wrapper(intel
, dst_image
);
329 struct gl_renderbuffer
*dst_rb
= &dst_irb
->Base
.Base
;
331 /* Unlike BlitFramebuffer, CopyTexSubImage doesn't have a buffer bit.
332 * It's only used by find_miptee() to decide whether to dereference the
333 * separate stencil miptree. In the case of packed depth/stencil, core
334 * Mesa hands us the depth attachment as src_rb (not stencil), so assume
335 * non-stencil for now. A buffer bit of 0 works for both color and depth.
337 GLbitfield buffer_bit
= 0;
339 if (!formats_match(buffer_bit
, src_irb
, dst_irb
)) {
340 dst_rb
->Delete(ctx
, dst_rb
);
344 /* Source clipping shouldn't be necessary, since copytexsubimage (in
345 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
348 * Destination clipping shouldn't be necessary since the restrictions on
349 * glCopyTexSubImage prevent the user from specifying a destination rectangle
350 * that falls outside the bounds of the destination texture.
351 * See error_check_subtexture_dimensions().
354 int srcY1
= srcY0
+ height
;
355 int dstX1
= dstX0
+ width
;
356 int dstY1
= dstY0
+ height
;
358 /* Sync up the state of window system buffers. We need to do this before
359 * we go looking for the buffers.
361 intel_prepare_render(intel
);
363 /* Account for the fact that in the system framebuffer, the origin is at
366 bool mirror_y
= false;
367 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
368 GLint tmp
= src_rb
->Height
- srcY0
;
369 srcY0
= src_rb
->Height
- srcY1
;
374 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
,
375 srcX0
, srcY0
, dstX0
, dstY0
, dstX1
, dstY1
, false, mirror_y
);
377 /* If we're copying a packed depth stencil texture, the above do_blorp_blit
378 * copied depth (since buffer_bit != GL_STENCIL_BIT). Now copy stencil as
379 * well. There's no need to do a formats_match() check because the separate
380 * stencil buffer is always S8.
382 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
383 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
385 src_irb
= intel_renderbuffer(src_rb
);
386 do_blorp_blit(intel
, GL_STENCIL_BUFFER_BIT
, src_irb
, dst_irb
,
387 srcX0
, srcY0
, dstX0
, dstY0
, dstX1
, dstY1
, false, mirror_y
);
390 dst_rb
->Delete(ctx
, dst_rb
);
396 brw_blorp_framebuffer(struct intel_context
*intel
,
397 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
398 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
399 GLbitfield mask
, GLenum filter
)
401 /* BLORP is not supported before Gen6. */
405 static GLbitfield buffer_bits
[] = {
408 GL_STENCIL_BUFFER_BIT
,
411 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
412 if ((mask
& buffer_bits
[i
]) &&
413 try_blorp_blit(intel
,
414 srcX0
, srcY0
, srcX1
, srcY1
,
415 dstX0
, dstY0
, dstX1
, dstY1
,
416 filter
, buffer_bits
[i
])) {
417 mask
&= ~buffer_bits
[i
];
426 * Enum to specify the order of arguments in a sampler message
428 enum sampler_message_arg
430 SAMPLER_MESSAGE_ARG_U_FLOAT
,
431 SAMPLER_MESSAGE_ARG_V_FLOAT
,
432 SAMPLER_MESSAGE_ARG_U_INT
,
433 SAMPLER_MESSAGE_ARG_V_INT
,
434 SAMPLER_MESSAGE_ARG_SI_INT
,
435 SAMPLER_MESSAGE_ARG_MCS_INT
,
436 SAMPLER_MESSAGE_ARG_ZERO_INT
,
440 * Generator for WM programs used in BLORP blits.
442 * The bulk of the work done by the WM program is to wrap and unwrap the
443 * coordinate transformations used by the hardware to store surfaces in
444 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
445 * sample index for a multisampled surface) to a memory offset by the
446 * following formulas:
448 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
449 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
451 * For a single-sampled surface, or for a multisampled surface using
452 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
455 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
456 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
457 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
458 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
460 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
461 * embeds the sample number into bit 1 of the X and Y coordinates:
463 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
464 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
465 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
466 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
467 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
468 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
469 * S = (Y & 0b10) | (X & 0b10) >> 1
471 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
472 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
475 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
476 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
477 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
478 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
479 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
480 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
481 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
483 * For X tiling, tile() combines together the low-order bits of the X and Y
484 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
485 * bytes wide and 8 rows high:
487 * tile(x_tiled, X, Y, S) = A
488 * where A = tile_num << 12 | offset
489 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
490 * offset = (Y' & 0b111) << 9
491 * | (X & 0b111111111)
493 * Y' = Y + S * qpitch
494 * detile(x_tiled, A) = (X, Y, S)
498 * Y' = (tile_num / tile_pitch) << 3
499 * | (A & 0b111000000000) >> 9
500 * X' = (tile_num % tile_pitch) << 9
501 * | (A & 0b111111111)
503 * (In all tiling formulas, cpp is the number of bytes occupied by a single
504 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
505 * to fill the width of the surface, and qpitch is the spacing (in rows)
506 * between array slices).
508 * For Y tiling, tile() combines together the low-order bits of the X and Y
509 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
510 * bytes wide and 32 rows high:
512 * tile(y_tiled, X, Y, S) = A
513 * where A = tile_num << 12 | offset
514 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
515 * offset = (X' & 0b1110000) << 5
516 * | (Y' & 0b11111) << 4
519 * Y' = Y + S * qpitch
520 * detile(y_tiled, A) = (X, Y, S)
524 * Y' = (tile_num / tile_pitch) << 5
525 * | (A & 0b111110000) >> 4
526 * X' = (tile_num % tile_pitch) << 7
527 * | (A & 0b111000000000) >> 5
530 * For W tiling, tile() combines together the low-order bits of the X and Y
531 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
532 * bytes wide and 64 rows high (note that W tiling is only used for stencil
533 * buffers, which always have cpp = 1 and S=0):
535 * tile(w_tiled, X, Y, S) = A
536 * where A = tile_num << 12 | offset
537 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
538 * offset = (X' & 0b111000) << 6
539 * | (Y' & 0b111100) << 3
540 * | (X' & 0b100) << 2
546 * Y' = Y + S * qpitch
547 * detile(w_tiled, A) = (X, Y, S)
548 * where X = X' / cpp = X'
549 * Y = Y' % qpitch = Y'
551 * Y' = (tile_num / tile_pitch) << 6
552 * | (A & 0b111100000) >> 3
553 * | (A & 0b1000) >> 2
555 * X' = (tile_num % tile_pitch) << 6
556 * | (A & 0b111000000000) >> 6
557 * | (A & 0b10000) >> 2
561 * Finally, for a non-tiled surface, tile() simply combines together the X and
562 * Y coordinates in the natural way:
564 * tile(untiled, X, Y, S) = A
565 * where A = Y * pitch + X'
567 * Y' = Y + S * qpitch
568 * detile(untiled, A) = (X, Y, S)
575 * (In these formulas, pitch is the number of bytes occupied by a single row
578 class brw_blorp_blit_program
581 brw_blorp_blit_program(struct brw_context
*brw
,
582 const brw_blorp_blit_prog_key
*key
);
583 ~brw_blorp_blit_program();
585 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
587 brw_blorp_prog_data prog_data
;
591 void alloc_push_const_regs(int base_reg
);
592 void compute_frag_coords();
593 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
594 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
595 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
596 void kill_if_outside_dst_rect();
597 void translate_dst_to_src();
598 void single_to_blend();
599 void manual_blend(unsigned num_samples
);
600 void sample(struct brw_reg dst
);
601 void texel_fetch(struct brw_reg dst
);
603 void expand_to_32_bits(struct brw_reg src
, struct brw_reg dst
);
604 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
605 const sampler_message_arg
*args
, int num_args
);
606 void render_target_write();
609 * Base-2 logarithm of the maximum number of samples that can be blended.
611 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
614 struct brw_context
*brw
;
615 const brw_blorp_blit_prog_key
*key
;
616 struct brw_compile func
;
618 /* Thread dispatch header */
621 /* Pixel X/Y coordinates (always in R1). */
625 struct brw_reg dst_x0
;
626 struct brw_reg dst_x1
;
627 struct brw_reg dst_y0
;
628 struct brw_reg dst_y1
;
630 struct brw_reg multiplier
;
631 struct brw_reg offset
;
632 } x_transform
, y_transform
;
634 /* Data read from texture (4 vec16's per array element) */
635 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
637 /* Auxiliary storage for the contents of the MCS surface.
639 * Since the sampler always returns 8 registers worth of data, this is 8
640 * registers wide, even though we only use the first 2 registers of it.
642 struct brw_reg mcs_data
;
644 /* X coordinates. We have two of them so that we can perform coordinate
645 * transformations easily.
647 struct brw_reg x_coords
[2];
649 /* Y coordinates. We have two of them so that we can perform coordinate
650 * transformations easily.
652 struct brw_reg y_coords
[2];
654 /* Which element of x_coords and y_coords is currently in use.
658 /* True if, at the point in the program currently being compiled, the
659 * sample index is known to be zero.
663 /* Register storing the sample index when s_is_zero is false. */
664 struct brw_reg sample_index
;
670 /* MRF used for sampling and render target writes */
674 brw_blorp_blit_program::brw_blorp_blit_program(
675 struct brw_context
*brw
,
676 const brw_blorp_blit_prog_key
*key
)
677 : mem_ctx(ralloc_context(NULL
)),
681 brw_init_compile(brw
, &func
, mem_ctx
);
684 brw_blorp_blit_program::~brw_blorp_blit_program()
686 ralloc_free(mem_ctx
);
690 brw_blorp_blit_program::compile(struct brw_context
*brw
,
691 GLuint
*program_size
)
694 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
695 /* If the destination image is W tiled and multisampled, then the thread
696 * must be dispatched once per sample, not once per pixel. This is
697 * necessary because after conversion between W and Y tiling, there's no
698 * guarantee that all samples corresponding to a single pixel will still
701 assert(key
->persample_msaa_dispatch
);
705 /* We are blending, which means we won't have an opportunity to
706 * translate the tiling and sample count for the texture surface. So
707 * the surface state for the texture must be configured with the correct
708 * tiling and sample count.
710 assert(!key
->src_tiled_w
);
711 assert(key
->tex_samples
== key
->src_samples
);
712 assert(key
->tex_layout
== key
->src_layout
);
713 assert(key
->tex_samples
> 0);
716 if (key
->persample_msaa_dispatch
) {
717 /* It only makes sense to do persample dispatch if the render target is
718 * configured as multisampled.
720 assert(key
->rt_samples
> 0);
723 /* Make sure layout is consistent with sample count */
724 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
725 (key
->tex_samples
== 0));
726 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
727 (key
->rt_samples
== 0));
728 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
729 (key
->src_samples
== 0));
730 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
731 (key
->dst_samples
== 0));
733 /* Set up prog_data */
734 memset(&prog_data
, 0, sizeof(prog_data
));
735 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
737 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
740 compute_frag_coords();
742 /* Render target and texture hardware don't support W tiling. */
743 const bool rt_tiled_w
= false;
744 const bool tex_tiled_w
= false;
746 /* The address that data will be written to is determined by the
747 * coordinates supplied to the WM thread and the tiling and sample count of
748 * the render target, according to the formula:
750 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
752 * If the actual tiling and sample count of the destination surface are not
753 * the same as the configuration of the render target, then these
754 * coordinates are wrong and we have to adjust them to compensate for the
757 if (rt_tiled_w
!= key
->dst_tiled_w
||
758 key
->rt_samples
!= key
->dst_samples
||
759 key
->rt_layout
!= key
->dst_layout
) {
760 encode_msaa(key
->rt_samples
, key
->rt_layout
);
761 /* Now (X, Y, S) = detile(rt_tiling, offset) */
762 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
763 /* Now (X, Y, S) = detile(dst_tiling, offset) */
764 decode_msaa(key
->dst_samples
, key
->dst_layout
);
767 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
769 * That is: X, Y and S now contain the true coordinates and sample index of
770 * the data that the WM thread should output.
772 * If we need to kill pixels that are outside the destination rectangle,
773 * now is the time to do it.
777 kill_if_outside_dst_rect();
779 /* Next, apply a translation to obtain coordinates in the source image. */
780 translate_dst_to_src();
782 /* If the source image is not multisampled, then we want to fetch sample
783 * number 0, because that's the only sample there is.
785 if (key
->src_samples
== 0)
788 /* X, Y, and S are now the coordinates of the pixel in the source image
789 * that we want to texture from. Exception: if we are blending, then S is
790 * irrelevant, because we are going to fetch all samples.
793 if (brw
->intel
.gen
== 6) {
794 /* Gen6 hardware an automatically blend using the SAMPLE message */
796 sample(texture_data
[0]);
798 /* Gen7+ hardware doesn't automaticaly blend. */
799 manual_blend(key
->src_samples
);
802 /* We aren't blending, which means we just want to fetch a single sample
803 * from the source surface. The address that we want to fetch from is
804 * related to the X, Y and S values according to the formula:
806 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
808 * If the actual tiling and sample count of the source surface are not
809 * the same as the configuration of the texture, then we need to adjust
810 * the coordinates to compensate for the difference.
812 if (tex_tiled_w
!= key
->src_tiled_w
||
813 key
->tex_samples
!= key
->src_samples
||
814 key
->tex_layout
!= key
->src_layout
) {
815 encode_msaa(key
->src_samples
, key
->src_layout
);
816 /* Now (X, Y, S) = detile(src_tiling, offset) */
817 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
818 /* Now (X, Y, S) = detile(tex_tiling, offset) */
819 decode_msaa(key
->tex_samples
, key
->tex_layout
);
822 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
824 * In other words: X, Y, and S now contain values which, when passed to
825 * the texturing unit, will cause data to be read from the correct
826 * memory location. So we can fetch the texel now.
828 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
830 texel_fetch(texture_data
[0]);
833 /* Finally, write the fetched (or blended) value to the render target and
834 * terminate the thread.
836 render_target_write();
837 return brw_get_program(&func
, program_size
);
841 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
843 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
844 #define ALLOC_REG(name) \
846 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
852 ALLOC_REG(x_transform
.multiplier
);
853 ALLOC_REG(x_transform
.offset
);
854 ALLOC_REG(y_transform
.multiplier
);
855 ALLOC_REG(y_transform
.offset
);
861 brw_blorp_blit_program::alloc_regs()
864 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
865 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
866 prog_data
.first_curbe_grf
= reg
;
867 alloc_push_const_regs(reg
);
868 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
869 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
870 this->texture_data
[i
] =
871 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
875 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
876 for (int i
= 0; i
< 2; ++i
) {
878 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
880 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
882 this->xy_coord_index
= 0;
884 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
885 this->t1
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
886 this->t2
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
888 /* Make sure we didn't run out of registers */
889 assert(reg
<= GEN7_MRF_HACK_START
);
892 this->base_mrf
= mrf
;
895 /* In the code that follows, X and Y can be used to quickly refer to the
896 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
897 * prime") to the inactive elements.
899 * S can be used to quickly refer to sample_index.
901 #define X x_coords[xy_coord_index]
902 #define Y y_coords[xy_coord_index]
903 #define Xp x_coords[!xy_coord_index]
904 #define Yp y_coords[!xy_coord_index]
905 #define S sample_index
907 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
908 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
910 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
913 * Emit code to compute the X and Y coordinates of the pixels being rendered
914 * by this WM invocation.
916 * Assuming the render target is set up for Y tiling, these (X, Y) values are
917 * related to the address offset where outputs will be written by the formula:
919 * (X, Y, S) = decode_msaa(detile(offset)).
921 * (See brw_blorp_blit_program).
924 brw_blorp_blit_program::compute_frag_coords()
926 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
927 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
928 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
929 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
931 * Pixels within a subspan are laid out in this arrangement:
935 * So, to compute the coordinates of each pixel, we need to read every 2nd
936 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
937 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
938 * In other words, the data we want to access is R1.4<2;4,0>UW.
940 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
941 * result, since pixels n+1 and n+3 are in the right half of the subspan.
943 brw_ADD(&func
, X
, stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
945 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
946 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
947 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
950 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
951 * pixels n+2 and n+3 are in the bottom half of the subspan.
953 brw_ADD(&func
, Y
, stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
955 if (key
->persample_msaa_dispatch
) {
956 switch (key
->rt_samples
) {
958 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
959 * Therefore, subspan 0 will represent sample 0, subspan 1 will
960 * represent sample 1, and so on.
962 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
963 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
964 * populate a temporary variable with the sequence (0, 1, 2, 3), and
965 * then copy from it using vstride=1, width=4, hstride=0.
967 brw_MOV(&func
, t1
, brw_imm_v(0x3210));
968 brw_MOV(&func
, S
, stride(t1
, 1, 4, 0));
971 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
972 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
973 * subspan 1 will represent sample 1, and so on. We can find the
974 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
975 * Index") and multiplying by two (since samples are always delivered
976 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
979 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
980 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
981 * variable with the sequence (0, 1, 2, 3), and then reading from it
982 * using vstride=1, width=4, hstride=0.
984 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
985 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
986 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
987 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
988 brw_MOV(&func
, t2
, brw_imm_v(0x3210));
989 brw_ADD(&func
, S
, retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
990 stride(t2
, 1, 4, 0));
994 assert(!"Unrecognized sample count in "
995 "brw_blorp_blit_program::compute_frag_coords()");
1000 /* Either the destination surface is single-sampled, or the WM will be
1001 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1002 * per pixel). In either case, it's not meaningful to compute a sample
1003 * value. Just set it to 0.
1010 * Emit code to compensate for the difference between Y and W tiling.
1012 * This code modifies the X and Y coordinates according to the formula:
1014 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1016 * (See brw_blorp_blit_program).
1018 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1019 * are booleans where true represents W tiling and false represents Y tiling.
1022 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1024 if (old_tiled_w
== new_tiled_w
)
1027 /* In the code that follows, we can safely assume that S = 0, because W
1028 * tiling formats always use IMS layout.
1033 /* Given X and Y coordinates that describe an address using Y tiling,
1034 * translate to the X and Y coordinates that describe the same address
1037 * If we break down the low order bits of X and Y, using a
1038 * single letter to represent each low-order bit:
1040 * X = A << 7 | 0bBCDEFGH
1041 * Y = J << 5 | 0bKLMNP (1)
1043 * Then we can apply the Y tiling formula to see the memory offset being
1046 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1048 * If we apply the W detiling formula to this memory location, that the
1049 * corresponding X' and Y' coordinates are:
1051 * X' = A << 6 | 0bBCDPFH (3)
1052 * Y' = J << 6 | 0bKLMNEG
1054 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1055 * we need to make the following computation:
1057 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1058 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1060 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1061 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1062 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1063 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1064 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1065 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1066 brw_OR(&func
, Xp
, t1
, t2
);
1067 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1068 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1069 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1070 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1071 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1072 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1073 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1074 brw_OR(&func
, Yp
, t1
, t2
);
1077 /* Applying the same logic as above, but in reverse, we obtain the
1080 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1081 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1083 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1084 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1085 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1086 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1087 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1088 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1089 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1090 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1092 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1093 brw_OR(&func
, Xp
, t1
, t2
);
1094 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1095 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1096 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1097 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1098 brw_OR(&func
, Yp
, t1
, t2
);
1104 * Emit code to compensate for the difference between MSAA and non-MSAA
1107 * This code modifies the X and Y coordinates according to the formula:
1109 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1111 * (See brw_blorp_blit_program).
1114 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1115 intel_msaa_layout layout
)
1118 case INTEL_MSAA_LAYOUT_NONE
:
1119 /* No translation necessary, and S should already be zero. */
1122 case INTEL_MSAA_LAYOUT_CMS
:
1123 /* We can't compensate for compressed layout since at this point in the
1124 * program we haven't read from the MCS buffer.
1126 assert(!"Bad layout in encode_msaa");
1128 case INTEL_MSAA_LAYOUT_UMS
:
1129 /* No translation necessary. */
1131 case INTEL_MSAA_LAYOUT_IMS
:
1132 switch (num_samples
) {
1134 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1135 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1136 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1138 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1140 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1141 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1143 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1145 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1146 brw_OR(&func
, Xp
, t1
, t2
);
1147 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1148 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1150 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1151 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1153 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1154 brw_OR(&func
, Yp
, t1
, t2
);
1157 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1158 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1160 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1162 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1163 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1165 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1166 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1167 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1168 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1169 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1172 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1173 brw_OR(&func
, Xp
, t1
, t2
);
1174 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1175 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1177 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1178 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1180 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1181 brw_OR(&func
, Yp
, t1
, t2
);
1191 * Emit code to compensate for the difference between MSAA and non-MSAA
1194 * This code modifies the X and Y coordinates according to the formula:
1196 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1198 * (See brw_blorp_blit_program).
1201 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1202 intel_msaa_layout layout
)
1205 case INTEL_MSAA_LAYOUT_NONE
:
1206 /* No translation necessary, and S should already be zero. */
1209 case INTEL_MSAA_LAYOUT_CMS
:
1210 /* We can't compensate for compressed layout since at this point in the
1211 * program we don't have access to the MCS buffer.
1213 assert(!"Bad layout in encode_msaa");
1215 case INTEL_MSAA_LAYOUT_UMS
:
1216 /* No translation necessary. */
1218 case INTEL_MSAA_LAYOUT_IMS
:
1220 switch (num_samples
) {
1222 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1223 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1224 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1225 * S = (Y & 0b10) | (X & 0b10) >> 1
1227 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1228 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1229 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1230 brw_OR(&func
, Xp
, t1
, t2
);
1231 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1232 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1233 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1234 brw_OR(&func
, Yp
, t1
, t2
);
1235 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1236 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1237 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1238 brw_OR(&func
, S
, t1
, t2
);
1241 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1242 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1243 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1244 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1246 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1247 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1248 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1249 brw_OR(&func
, Xp
, t1
, t2
);
1250 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1251 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1252 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1253 brw_OR(&func
, Yp
, t1
, t2
);
1254 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1255 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1256 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1257 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1258 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1259 brw_OR(&func
, S
, t1
, t2
);
1269 * Emit code that kills pixels whose X and Y coordinates are outside the
1270 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1274 brw_blorp_blit_program::kill_if_outside_dst_rect()
1276 struct brw_reg f0
= brw_flag_reg(0, 0);
1277 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1278 struct brw_reg null16
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
1280 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1281 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1282 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1283 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1285 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1286 brw_push_insn_state(&func
);
1287 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1288 brw_AND(&func
, g1
, f0
, g1
);
1289 brw_pop_insn_state(&func
);
1293 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1297 brw_blorp_blit_program::translate_dst_to_src()
1299 brw_MUL(&func
, Xp
, X
, x_transform
.multiplier
);
1300 brw_MUL(&func
, Yp
, Y
, y_transform
.multiplier
);
1301 brw_ADD(&func
, Xp
, Xp
, x_transform
.offset
);
1302 brw_ADD(&func
, Yp
, Yp
, y_transform
.offset
);
1307 * Emit code to transform the X and Y coordinates as needed for blending
1308 * together the different samples in an MSAA texture.
1311 brw_blorp_blit_program::single_to_blend()
1313 /* When looking up samples in an MSAA texture using the SAMPLE message,
1314 * Gen6 requires the texture coordinates to be odd integers (so that they
1315 * correspond to the center of a 2x2 block representing the four samples
1316 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1317 * each by 2 and then add 1.
1319 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1320 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1321 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1322 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1328 * Count the number of trailing 1 bits in the given value. For example:
1330 * count_trailing_one_bits(0) == 0
1331 * count_trailing_one_bits(7) == 3
1332 * count_trailing_one_bits(11) == 2
1334 inline int count_trailing_one_bits(unsigned value
)
1336 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1337 return __builtin_ctz(~value
);
1339 return _mesa_bitcount(value
& ~(value
+ 1));
1345 brw_blorp_blit_program::manual_blend(unsigned num_samples
)
1347 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1350 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1352 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1354 * This ensures that when all samples have the same value, no numerical
1355 * precision is lost, since each addition operation always adds two equal
1356 * values, and summing two equal floating point values does not lose
1359 * We perform this computation by treating the texture_data array as a
1360 * stack and performing the following operations:
1362 * - push sample 0 onto stack
1363 * - push sample 1 onto stack
1364 * - add top two stack entries
1365 * - push sample 2 onto stack
1366 * - push sample 3 onto stack
1367 * - add top two stack entries
1368 * - add top two stack entries
1369 * - divide top stack entry by 4
1371 * Note that after pushing sample i onto the stack, the number of add
1372 * operations we do is equal to the number of trailing 1 bits in i. This
1373 * works provided the total number of samples is a power of two, which it
1374 * always is for i965.
1376 * For integer formats, we replace the add operations with average
1377 * operations and skip the final division.
1379 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1383 brw_op2_ptr combine_op
=
1384 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1385 unsigned stack_depth
= 0;
1386 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1387 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1389 /* Push sample i onto the stack */
1390 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1395 brw_MOV(&func
, S
, brw_imm_uw(i
));
1397 texel_fetch(texture_data
[stack_depth
++]);
1399 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1400 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1401 * suggests an optimization:
1403 * "A simple optimization with probable large return in
1404 * performance is to compare the MCS value to zero (indicating
1405 * all samples are on sample slice 0), and sample only from
1406 * sample slice 0 using ld2dss if MCS is zero."
1408 * Note that in the case where the MCS value is zero, sampling from
1409 * sample slice 0 using ld2dss and sampling from sample 0 using
1410 * ld2dms are equivalent (since all samples are on sample slice 0).
1411 * Since we have already sampled from sample 0, all we need to do is
1412 * skip the remaining fetches and averaging if MCS is zero.
1414 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1415 mcs_data
, brw_imm_ud(0));
1416 brw_IF(&func
, BRW_EXECUTE_16
);
1419 /* Do count_trailing_one_bits(i) times */
1420 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1421 assert(stack_depth
>= 2);
1424 /* TODO: should use a smaller loop bound for non_RGBA formats */
1425 for (int k
= 0; k
< 4; ++k
) {
1426 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1427 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1428 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1433 /* We should have just 1 sample on the stack now. */
1434 assert(stack_depth
== 1);
1436 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1437 /* Scale the result down by a factor of num_samples */
1438 /* TODO: should use a smaller loop bound for non-RGBA formats */
1439 for (int j
= 0; j
< 4; ++j
) {
1440 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1441 offset(vec8(texture_data
[0]), 2*j
),
1442 brw_imm_f(1.0/num_samples
));
1446 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1451 * Emit code to look up a value in the texture using the SAMPLE message (which
1452 * does blending of MSAA surfaces).
1455 brw_blorp_blit_program::sample(struct brw_reg dst
)
1457 static const sampler_message_arg args
[2] = {
1458 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1459 SAMPLER_MESSAGE_ARG_V_FLOAT
1462 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
, ARRAY_SIZE(args
));
1466 * Emit code to look up a value in the texture using the SAMPLE_LD message
1467 * (which does a simple texel fetch).
1470 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1472 static const sampler_message_arg gen6_args
[5] = {
1473 SAMPLER_MESSAGE_ARG_U_INT
,
1474 SAMPLER_MESSAGE_ARG_V_INT
,
1475 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1476 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1477 SAMPLER_MESSAGE_ARG_SI_INT
1479 static const sampler_message_arg gen7_ld_args
[3] = {
1480 SAMPLER_MESSAGE_ARG_U_INT
,
1481 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1482 SAMPLER_MESSAGE_ARG_V_INT
1484 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1485 SAMPLER_MESSAGE_ARG_SI_INT
,
1486 SAMPLER_MESSAGE_ARG_U_INT
,
1487 SAMPLER_MESSAGE_ARG_V_INT
1489 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1490 SAMPLER_MESSAGE_ARG_SI_INT
,
1491 SAMPLER_MESSAGE_ARG_MCS_INT
,
1492 SAMPLER_MESSAGE_ARG_U_INT
,
1493 SAMPLER_MESSAGE_ARG_V_INT
1496 switch (brw
->intel
.gen
) {
1498 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1502 switch (key
->tex_layout
) {
1503 case INTEL_MSAA_LAYOUT_IMS
:
1504 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1507 * If this field is MSFMT_DEPTH_STENCIL
1508 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1509 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1511 * So fall through to emit the same message as we use for
1512 * INTEL_MSAA_LAYOUT_CMS.
1514 case INTEL_MSAA_LAYOUT_CMS
:
1515 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1516 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1518 case INTEL_MSAA_LAYOUT_UMS
:
1519 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1520 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1522 case INTEL_MSAA_LAYOUT_NONE
:
1524 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1525 ARRAY_SIZE(gen7_ld_args
));
1530 assert(!"Should not get here.");
1536 brw_blorp_blit_program::mcs_fetch()
1538 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1539 SAMPLER_MESSAGE_ARG_U_INT
,
1540 SAMPLER_MESSAGE_ARG_V_INT
1542 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1543 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1547 brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src
,
1550 brw_MOV(&func
, vec8(dst
), vec8(src
));
1551 brw_set_compression_control(&func
, BRW_COMPRESSION_2NDHALF
);
1552 brw_MOV(&func
, offset(vec8(dst
), 1), suboffset(vec8(src
), 8));
1553 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1557 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1559 const sampler_message_arg
*args
,
1562 struct brw_reg mrf
=
1563 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1564 for (int arg
= 0; arg
< num_args
; ++arg
) {
1565 switch (args
[arg
]) {
1566 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1567 expand_to_32_bits(X
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1569 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1570 expand_to_32_bits(Y
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1572 case SAMPLER_MESSAGE_ARG_U_INT
:
1573 expand_to_32_bits(X
, mrf
);
1575 case SAMPLER_MESSAGE_ARG_V_INT
:
1576 expand_to_32_bits(Y
, mrf
);
1578 case SAMPLER_MESSAGE_ARG_SI_INT
:
1579 /* Note: on Gen7, this code may be reached with s_is_zero==true
1580 * because in Gen7's ld2dss message, the sample index is the first
1581 * argument. When this happens, we need to move a 0 into the
1582 * appropriate message register.
1585 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1587 expand_to_32_bits(S
, mrf
);
1589 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1590 switch (key
->tex_layout
) {
1591 case INTEL_MSAA_LAYOUT_CMS
:
1592 brw_MOV(&func
, mrf
, mcs_data
);
1594 case INTEL_MSAA_LAYOUT_IMS
:
1595 /* When sampling from an IMS surface, MCS data is not relevant,
1596 * and the hardware ignores it. So don't bother populating it.
1600 /* We shouldn't be trying to send MCS data with any other
1603 assert (!"Unsupported layout for MCS data");
1607 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1608 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1615 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1616 base_mrf
/* msg_reg_nr */,
1617 brw_message_reg(base_mrf
) /* src0 */,
1618 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1621 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1622 mrf
.nr
- base_mrf
/* msg_length */,
1623 0 /* header_present */,
1624 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1625 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1633 #undef SWAP_XY_AND_XPYP
1636 brw_blorp_blit_program::render_target_write()
1638 struct brw_reg mrf_rt_write
=
1639 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1642 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1643 * so that the render target knows which pixels we killed.
1645 bool use_header
= key
->use_kill
;
1647 /* Copy R0/1 to MRF */
1648 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1649 retype(R0
, BRW_REGISTER_TYPE_UD
));
1653 /* Copy texture data to MRFs */
1654 for (int i
= 0; i
< 4; ++i
) {
1655 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1656 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1657 offset(vec8(texture_data
[0]), 2*i
));
1661 /* Now write to the render target and terminate the thread */
1663 16 /* dispatch_width */,
1664 base_mrf
/* msg_reg_nr */,
1665 mrf_rt_write
/* src0 */,
1666 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1667 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1668 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1669 0 /* response_length */,
1676 brw_blorp_coord_transform_params::setup(GLuint src0
, GLuint dst0
, GLuint dst1
,
1680 /* When not mirroring a coordinate (say, X), we need:
1681 * x' - src_x0 = x - dst_x0
1683 * x' = 1*x + (src_x0 - dst_x0)
1686 offset
= src0
- dst0
;
1688 /* When mirroring X we need:
1689 * x' - src_x0 = dst_x1 - x - 1
1691 * x' = -1*x + (src_x0 + dst_x1 - 1)
1694 offset
= src0
+ dst1
- 1;
1700 * Determine which MSAA layout the GPU pipeline should be configured for,
1701 * based on the chip generation, the number of samples, and the true layout of
1702 * the image in memory.
1704 inline intel_msaa_layout
1705 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1706 intel_msaa_layout true_layout
)
1708 if (num_samples
<= 1) {
1709 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1710 * format buffers, by transforming coordinates appropriately.
1712 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1713 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1714 return INTEL_MSAA_LAYOUT_NONE
;
1716 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1719 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1720 if (brw
->intel
.gen
== 6) {
1721 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1728 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1729 struct intel_mipmap_tree
*src_mt
,
1730 unsigned src_level
, unsigned src_layer
,
1731 struct intel_mipmap_tree
*dst_mt
,
1732 unsigned dst_level
, unsigned dst_layer
,
1733 GLuint src_x0
, GLuint src_y0
,
1734 GLuint dst_x0
, GLuint dst_y0
,
1735 GLuint dst_x1
, GLuint dst_y1
,
1736 bool mirror_x
, bool mirror_y
)
1738 src
.set(brw
, src_mt
, src_level
, src_layer
);
1739 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
);
1741 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1744 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1746 /* texture_data_type indicates the register type that should be used to
1747 * manipulate texture data.
1749 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1750 case GL_UNSIGNED_NORMALIZED
:
1751 case GL_SIGNED_NORMALIZED
:
1753 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1755 case GL_UNSIGNED_INT
:
1756 if (src_mt
->format
== MESA_FORMAT_S8
) {
1757 /* We process stencil as though it's an unsigned normalized color */
1758 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1760 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1764 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1767 assert(!"Unrecognized blorp format");
1771 if (brw
->intel
.gen
> 6) {
1772 /* Gen7's rendering hardware only supports the IMS layout for depth and
1773 * stencil render targets. Blorp always maps its destination surface as
1774 * a color render target (even if it's actually a depth or stencil
1775 * buffer). So if the destination is IMS, we'll have to map it as a
1776 * single-sampled texture and interleave the samples ourselves.
1778 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1779 dst
.num_samples
= 0;
1782 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1783 /* If the destination surface is a W-tiled multisampled stencil buffer
1784 * that we're mapping as Y tiled, then we need to arrange for the WM
1785 * program to run once per sample rather than once per pixel, because
1786 * the memory layout of related samples doesn't match between W and Y
1789 wm_prog_key
.persample_msaa_dispatch
= true;
1792 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1793 /* We are blitting from a multisample buffer to a multisample buffer, so
1794 * we must preserve samples within a pixel. This means we have to
1795 * arrange for the WM program to run once per sample rather than once
1798 wm_prog_key
.persample_msaa_dispatch
= true;
1801 /* The render path must be configured to use the same number of samples as
1802 * the destination buffer.
1804 num_samples
= dst
.num_samples
;
1806 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1807 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1808 base_format
!= GL_STENCIL_INDEX
&&
1809 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1810 /* We are downsampling a color buffer, so blend. */
1811 wm_prog_key
.blend
= true;
1814 /* src_samples and dst_samples are the true sample counts */
1815 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1816 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1818 /* tex_samples and rt_samples are the sample counts that are set up in
1821 wm_prog_key
.tex_samples
= src
.num_samples
;
1822 wm_prog_key
.rt_samples
= dst
.num_samples
;
1824 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1825 * use to access the source and destination surfaces.
1827 wm_prog_key
.tex_layout
=
1828 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1829 wm_prog_key
.rt_layout
=
1830 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1832 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1835 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1836 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1838 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1839 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1840 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1841 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1842 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1843 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1844 wm_push_consts
.x_transform
.setup(src_x0
, dst_x0
, dst_x1
, mirror_x
);
1845 wm_push_consts
.y_transform
.setup(src_y0
, dst_y0
, dst_y1
, mirror_y
);
1847 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
1848 /* We must expand the rectangle we send through the rendering pipeline,
1849 * to account for the fact that we are mapping the destination region as
1850 * single-sampled when it is in fact multisampled. We must also align
1851 * it to a multiple of the multisampling pattern, because the
1852 * differences between multisampled and single-sampled surface formats
1853 * will mean that pixels are scrambled within the multisampling pattern.
1854 * TODO: what if this makes the coordinates too large?
1856 * Note: this only works if the destination surface uses the IMS layout.
1857 * If it's UMS, then we have no choice but to set up the rendering
1858 * pipeline as multisampled.
1860 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
1861 switch (dst_mt
->num_samples
) {
1863 x0
= ROUND_DOWN_TO(x0
* 2, 4);
1864 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1865 x1
= ALIGN(x1
* 2, 4);
1866 y1
= ALIGN(y1
* 2, 4);
1869 x0
= ROUND_DOWN_TO(x0
* 4, 8);
1870 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1871 x1
= ALIGN(x1
* 4, 8);
1872 y1
= ALIGN(y1
* 2, 4);
1875 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
1878 wm_prog_key
.use_kill
= true;
1881 if (dst
.map_stencil_as_y_tiled
) {
1882 /* We must modify the rectangle we send through the rendering pipeline
1883 * (and the size and x/y offset of the destination surface), to account
1884 * for the fact that we are mapping it as Y-tiled when it is in fact
1887 * Both Y tiling and W tiling can be understood as organizations of
1888 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1889 * is different, but the layout of the 32-byte sub-tiles within the 4k
1890 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1891 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1892 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1894 * Therefore, to account for the layout differences within the 32-byte
1895 * sub-tiles, we must expand the rectangle so the X coordinates of its
1896 * edges are multiples of 8 (the W sub-tile width), and its Y
1897 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1898 * Then we need to scale the X and Y coordinates of the rectangle to
1899 * account for the differences in aspect ratio between the Y and W
1900 * sub-tiles. We need to modify the layer width and height similarly.
1902 * A correction needs to be applied when MSAA is in use: since
1903 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1904 * we need to align the Y coordinates to multiples of 8, so that when
1905 * they are divided by two they are still multiples of 4.
1907 * Note: Since the x/y offset of the surface will be applied using the
1908 * SURFACE_STATE command packet, it will be invisible to the swizzling
1909 * code in the shader; therefore it needs to be in a multiple of the
1910 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1911 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1912 * buffer), and the miplevel alignment used for stencil buffers is 8
1913 * pixels horizontally and either 4 or 8 pixels vertically (see
1914 * intel_horizontal_texture_alignment_unit() and
1915 * intel_vertical_texture_alignment_unit()).
1917 * Note: Also, since the SURFACE_STATE command packet can only apply
1918 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1919 * vertically, it is important that the offsets will be multiples of
1920 * these sizes after they are converted into Y-tiled coordinates.
1921 * Fortunately they will be, since we know from above that the offsets
1922 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1923 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1925 * TODO: what if this makes the coordinates (or the texture size) too
1928 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
1929 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
1930 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
1931 x1
= ALIGN(x1
, x_align
) * 2;
1932 y1
= ALIGN(y1
, y_align
) / 2;
1933 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
1934 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
1937 wm_prog_key
.use_kill
= true;
1940 if (src
.map_stencil_as_y_tiled
) {
1941 /* We must modify the size and x/y offset of the source surface to
1942 * account for the fact that we are mapping it as Y-tiled when it is in
1945 * See the comments above concerning x/y offset alignment for the
1946 * destination surface.
1948 * TODO: what if this makes the texture size too large?
1950 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
1951 src
.width
= ALIGN(src
.width
, x_align
) * 2;
1952 src
.height
= ALIGN(src
.height
, y_align
) / 2;
1959 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
1960 brw_blorp_prog_data
**prog_data
) const
1962 uint32_t prog_offset
;
1963 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1964 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1965 &prog_offset
, prog_data
)) {
1966 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
1967 GLuint program_size
;
1968 const GLuint
*program
= prog
.compile(brw
, &program_size
);
1969 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1970 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1971 program
, program_size
,
1972 &prog
.prog_data
, sizeof(prog
.prog_data
),
1973 &prog_offset
, prog_data
);