2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
37 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 * Helper function for handling mirror image blits.
42 * If coord0 > coord1, swap them and invert the "mirror" boolean.
45 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
47 if (coord0
> coord1
) {
57 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
58 * destination coordinates.
60 * Return true if there is still blitting to do, false if all pixels got
61 * rejected by the clip and/or scissor.
63 * For clarity, the nomenclature of this function assumes we are clipping and
64 * scissoring the X coordinate; the exact same logic applies for Y
67 * Note: this function may also be used to account for clipping of source
68 * coordinates, by swapping the roles of src and dst.
71 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
72 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
74 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
75 /* If we are going to scissor everything away, stop. */
76 if (!(fb_xmin
< fb_xmax
&&
83 /* Clip the destination rectangle, and keep track of how many pixels we
84 * clipped off of the left and right sides of it.
86 GLint pixels_clipped_left
= 0;
87 GLint pixels_clipped_right
= 0;
88 if (dst_x0
< fb_xmin
) {
89 pixels_clipped_left
= fb_xmin
- dst_x0
;
92 if (fb_xmax
< dst_x1
) {
93 pixels_clipped_right
= dst_x1
- fb_xmax
;
97 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
98 * the source coordinates, we need to flip them to account for the
102 GLint tmp
= pixels_clipped_left
;
103 pixels_clipped_left
= pixels_clipped_right
;
104 pixels_clipped_right
= tmp
;
107 /* Adjust the source rectangle to remove the pixels corresponding to those
108 * that were clipped/scissored out of the destination rectangle.
110 src_x0
+= pixels_clipped_left
* scale
;
111 src_x1
-= pixels_clipped_right
* scale
;
117 static struct intel_mipmap_tree
*
118 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
120 struct intel_mipmap_tree
*mt
= irb
->mt
;
121 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
128 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
129 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
130 * the physical layer holding sample 0. So, for example, if
131 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
135 brw_blorp_blit_miptrees(struct brw_context
*brw
,
136 struct intel_mipmap_tree
*src_mt
,
137 unsigned src_level
, unsigned src_layer
,
138 struct intel_mipmap_tree
*dst_mt
,
139 unsigned dst_level
, unsigned dst_layer
,
140 float src_x0
, float src_y0
,
141 float src_x1
, float src_y1
,
142 float dst_x0
, float dst_y0
,
143 float dst_x1
, float dst_y1
,
144 GLenum filter
, bool mirror_x
, bool mirror_y
)
146 /* Get ready to blit. This includes depth resolving the src and dst
147 * buffers if necessary. Note: it's not necessary to do a color resolve on
148 * the destination buffer because we use the standard render path to render
149 * to destination color buffers, and the standard render path is
152 intel_miptree_resolve_color(brw
, src_mt
);
153 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
154 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
156 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
157 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
159 _mesa_get_format_name(src_mt
->format
), src_mt
,
160 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
161 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
162 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
165 brw_blorp_blit_params
params(brw
,
166 src_mt
, src_level
, src_layer
,
167 dst_mt
, dst_level
, dst_layer
,
172 filter
, mirror_x
, mirror_y
);
173 brw_blorp_exec(brw
, ¶ms
);
175 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
179 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
180 struct intel_renderbuffer
*src_irb
,
181 struct intel_renderbuffer
*dst_irb
,
182 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
183 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
184 GLenum filter
, bool mirror_x
, bool mirror_y
)
186 /* Find source/dst miptrees */
187 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
188 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
191 brw_blorp_blit_miptrees(brw
,
192 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
193 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
194 srcX0
, srcY0
, srcX1
, srcY1
,
195 dstX0
, dstY0
, dstX1
, dstY1
,
196 filter
, mirror_x
, mirror_y
);
198 intel_renderbuffer_set_needs_downsample(dst_irb
);
202 color_formats_match(gl_format src_format
, gl_format dst_format
)
204 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
205 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
207 /* Normally, we require the formats to be equal. However, we also support
208 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
209 * (overriding alpha to 1.0 via blending).
211 return linear_src_format
== linear_dst_format
||
212 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
213 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
214 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
215 linear_dst_format
== MESA_FORMAT_XRGB8888
);
219 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
220 struct intel_renderbuffer
*dst_irb
)
222 /* Note: don't just check gl_renderbuffer::Format, because in some cases
223 * multiple gl_formats resolve to the same native type in the miptree (for
224 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
225 * between those formats.
227 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
228 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
230 return color_formats_match(src_format
, dst_format
);
234 try_blorp_blit(struct brw_context
*brw
,
235 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
236 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
237 GLenum filter
, GLbitfield buffer_bit
)
239 struct gl_context
*ctx
= &brw
->ctx
;
241 /* Sync up the state of window system buffers. We need to do this before
242 * we go looking for the buffers.
244 intel_prepare_render(brw
);
246 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
247 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
249 /* Detect if the blit needs to be mirrored */
250 bool mirror_x
= false, mirror_y
= false;
251 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
252 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
253 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
254 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
256 /* If the destination rectangle needs to be clipped or scissored, do so.
258 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
259 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
260 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
261 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
262 /* Everything got clipped/scissored away, so the blit was successful. */
266 /* If the source rectangle needs to be clipped or scissored, do so. */
267 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
268 0, read_fb
->Width
) &&
269 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
270 0, read_fb
->Height
))) {
271 /* Everything got clipped/scissored away, so the blit was successful. */
275 /* Account for the fact that in the system framebuffer, the origin is at
278 if (_mesa_is_winsys_fbo(read_fb
)) {
279 GLint tmp
= read_fb
->Height
- srcY0
;
280 srcY0
= read_fb
->Height
- srcY1
;
282 mirror_y
= !mirror_y
;
284 if (_mesa_is_winsys_fbo(draw_fb
)) {
285 GLint tmp
= draw_fb
->Height
- dstY0
;
286 dstY0
= draw_fb
->Height
- dstY1
;
288 mirror_y
= !mirror_y
;
292 struct intel_renderbuffer
*src_irb
;
293 struct intel_renderbuffer
*dst_irb
;
294 switch (buffer_bit
) {
295 case GL_COLOR_BUFFER_BIT
:
296 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
297 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
298 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
299 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
302 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
303 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
305 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
306 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
307 filter
, mirror_x
, mirror_y
);
310 case GL_DEPTH_BUFFER_BIT
:
312 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
314 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
315 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
317 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
318 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
319 filter
, mirror_x
, mirror_y
);
321 case GL_STENCIL_BUFFER_BIT
:
323 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
325 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
326 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
328 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
329 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
330 filter
, mirror_x
, mirror_y
);
340 brw_blorp_copytexsubimage(struct brw_context
*brw
,
341 struct gl_renderbuffer
*src_rb
,
342 struct gl_texture_image
*dst_image
,
344 int srcX0
, int srcY0
,
345 int dstX0
, int dstY0
,
346 int width
, int height
)
348 struct gl_context
*ctx
= &brw
->ctx
;
349 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
350 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
352 /* Sync up the state of window system buffers. We need to do this before
353 * we go looking at the src renderbuffer's miptree.
355 intel_prepare_render(brw
);
357 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
358 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
360 /* BLORP is not supported before Gen6. */
361 if (brw
->gen
< 6 || brw
->gen
>= 8)
364 if (_mesa_get_format_base_format(src_mt
->format
) !=
365 _mesa_get_format_base_format(dst_mt
->format
)) {
369 /* We can't handle format conversions between Z24 and other formats since
370 * we have to lie about the surface format. See the comments in
371 * brw_blorp_surface_info::set().
373 if ((src_mt
->format
== MESA_FORMAT_X8_Z24
) !=
374 (dst_mt
->format
== MESA_FORMAT_X8_Z24
)) {
378 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
381 /* Source clipping shouldn't be necessary, since copytexsubimage (in
382 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
385 * Destination clipping shouldn't be necessary since the restrictions on
386 * glCopyTexSubImage prevent the user from specifying a destination rectangle
387 * that falls outside the bounds of the destination texture.
388 * See error_check_subtexture_dimensions().
391 int srcY1
= srcY0
+ height
;
392 int srcX1
= srcX0
+ width
;
393 int dstX1
= dstX0
+ width
;
394 int dstY1
= dstY0
+ height
;
396 /* Account for the fact that in the system framebuffer, the origin is at
399 bool mirror_y
= false;
400 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
401 GLint tmp
= src_rb
->Height
- srcY0
;
402 srcY0
= src_rb
->Height
- srcY1
;
407 brw_blorp_blit_miptrees(brw
,
408 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
409 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
410 srcX0
, srcY0
, srcX1
, srcY1
,
411 dstX0
, dstY0
, dstX1
, dstY1
,
412 GL_NEAREST
, false, mirror_y
);
414 /* If we're copying to a packed depth stencil texture and the source
415 * framebuffer has separate stencil, we need to also copy the stencil data
418 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
419 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
421 src_irb
= intel_renderbuffer(src_rb
);
422 src_mt
= src_irb
->mt
;
424 if (src_mt
->stencil_mt
)
425 src_mt
= src_mt
->stencil_mt
;
426 if (dst_mt
->stencil_mt
)
427 dst_mt
= dst_mt
->stencil_mt
;
429 if (src_mt
!= dst_mt
) {
430 brw_blorp_blit_miptrees(brw
,
431 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
432 dst_mt
, dst_image
->Level
,
433 dst_image
->Face
+ slice
,
434 srcX0
, srcY0
, srcX1
, srcY1
,
435 dstX0
, dstY0
, dstX1
, dstY1
,
436 GL_NEAREST
, false, mirror_y
);
445 brw_blorp_framebuffer(struct brw_context
*brw
,
446 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
447 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
448 GLbitfield mask
, GLenum filter
)
450 /* BLORP is not supported before Gen6. */
451 if (brw
->gen
< 6 || brw
->gen
>= 8)
454 static GLbitfield buffer_bits
[] = {
457 GL_STENCIL_BUFFER_BIT
,
460 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
461 if ((mask
& buffer_bits
[i
]) &&
463 srcX0
, srcY0
, srcX1
, srcY1
,
464 dstX0
, dstY0
, dstX1
, dstY1
,
465 filter
, buffer_bits
[i
])) {
466 mask
&= ~buffer_bits
[i
];
475 * Enum to specify the order of arguments in a sampler message
477 enum sampler_message_arg
479 SAMPLER_MESSAGE_ARG_U_FLOAT
,
480 SAMPLER_MESSAGE_ARG_V_FLOAT
,
481 SAMPLER_MESSAGE_ARG_U_INT
,
482 SAMPLER_MESSAGE_ARG_V_INT
,
483 SAMPLER_MESSAGE_ARG_SI_INT
,
484 SAMPLER_MESSAGE_ARG_MCS_INT
,
485 SAMPLER_MESSAGE_ARG_ZERO_INT
,
489 * Generator for WM programs used in BLORP blits.
491 * The bulk of the work done by the WM program is to wrap and unwrap the
492 * coordinate transformations used by the hardware to store surfaces in
493 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
494 * sample index for a multisampled surface) to a memory offset by the
495 * following formulas:
497 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
498 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
500 * For a single-sampled surface, or for a multisampled surface using
501 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
504 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
505 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
506 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
507 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
509 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
510 * embeds the sample number into bit 1 of the X and Y coordinates:
512 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
513 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
514 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
515 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
516 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
517 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
518 * S = (Y & 0b10) | (X & 0b10) >> 1
520 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
521 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
524 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
525 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
526 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
527 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
528 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
529 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
530 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
532 * For X tiling, tile() combines together the low-order bits of the X and Y
533 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
534 * bytes wide and 8 rows high:
536 * tile(x_tiled, X, Y, S) = A
537 * where A = tile_num << 12 | offset
538 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
539 * offset = (Y' & 0b111) << 9
540 * | (X & 0b111111111)
542 * Y' = Y + S * qpitch
543 * detile(x_tiled, A) = (X, Y, S)
547 * Y' = (tile_num / tile_pitch) << 3
548 * | (A & 0b111000000000) >> 9
549 * X' = (tile_num % tile_pitch) << 9
550 * | (A & 0b111111111)
552 * (In all tiling formulas, cpp is the number of bytes occupied by a single
553 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
554 * to fill the width of the surface, and qpitch is the spacing (in rows)
555 * between array slices).
557 * For Y tiling, tile() combines together the low-order bits of the X and Y
558 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
559 * bytes wide and 32 rows high:
561 * tile(y_tiled, X, Y, S) = A
562 * where A = tile_num << 12 | offset
563 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
564 * offset = (X' & 0b1110000) << 5
565 * | (Y' & 0b11111) << 4
568 * Y' = Y + S * qpitch
569 * detile(y_tiled, A) = (X, Y, S)
573 * Y' = (tile_num / tile_pitch) << 5
574 * | (A & 0b111110000) >> 4
575 * X' = (tile_num % tile_pitch) << 7
576 * | (A & 0b111000000000) >> 5
579 * For W tiling, tile() combines together the low-order bits of the X and Y
580 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
581 * bytes wide and 64 rows high (note that W tiling is only used for stencil
582 * buffers, which always have cpp = 1 and S=0):
584 * tile(w_tiled, X, Y, S) = A
585 * where A = tile_num << 12 | offset
586 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
587 * offset = (X' & 0b111000) << 6
588 * | (Y' & 0b111100) << 3
589 * | (X' & 0b100) << 2
595 * Y' = Y + S * qpitch
596 * detile(w_tiled, A) = (X, Y, S)
597 * where X = X' / cpp = X'
598 * Y = Y' % qpitch = Y'
600 * Y' = (tile_num / tile_pitch) << 6
601 * | (A & 0b111100000) >> 3
602 * | (A & 0b1000) >> 2
604 * X' = (tile_num % tile_pitch) << 6
605 * | (A & 0b111000000000) >> 6
606 * | (A & 0b10000) >> 2
610 * Finally, for a non-tiled surface, tile() simply combines together the X and
611 * Y coordinates in the natural way:
613 * tile(untiled, X, Y, S) = A
614 * where A = Y * pitch + X'
616 * Y' = Y + S * qpitch
617 * detile(untiled, A) = (X, Y, S)
624 * (In these formulas, pitch is the number of bytes occupied by a single row
627 class brw_blorp_blit_program
630 brw_blorp_blit_program(struct brw_context
*brw
,
631 const brw_blorp_blit_prog_key
*key
);
632 ~brw_blorp_blit_program();
634 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
,
635 FILE *dump_file
= stdout
);
637 brw_blorp_prog_data prog_data
;
641 void alloc_push_const_regs(int base_reg
);
642 void compute_frag_coords();
643 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
644 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
645 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
646 void kill_if_outside_dst_rect();
647 void translate_dst_to_src();
648 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
649 struct brw_reg clampX0
, struct brw_reg clampY0
,
650 struct brw_reg clampX1
, struct brw_reg clampY1
);
651 void single_to_blend();
652 void manual_blend_average(unsigned num_samples
);
653 void manual_blend_bilinear(unsigned num_samples
);
654 void sample(struct brw_reg dst
);
655 void texel_fetch(struct brw_reg dst
);
657 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
658 const sampler_message_arg
*args
, int num_args
);
659 void render_target_write();
661 void emit_lrp(const struct brw_reg
&dst
,
662 const struct brw_reg
&src1
,
663 const struct brw_reg
&src2
,
664 const struct brw_reg
&src3
);
667 * Base-2 logarithm of the maximum number of samples that can be blended.
669 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
672 struct brw_context
*brw
;
673 const brw_blorp_blit_prog_key
*key
;
674 struct brw_compile func
;
676 /* Thread dispatch header */
679 /* Pixel X/Y coordinates (always in R1). */
683 struct brw_reg dst_x0
;
684 struct brw_reg dst_x1
;
685 struct brw_reg dst_y0
;
686 struct brw_reg dst_y1
;
687 /* Top right coordinates of the rectangular grid used for scaled blitting */
688 struct brw_reg rect_grid_x1
;
689 struct brw_reg rect_grid_y1
;
691 struct brw_reg multiplier
;
692 struct brw_reg offset
;
693 } x_transform
, y_transform
;
695 /* Data read from texture (4 vec16's per array element) */
696 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
698 /* Auxiliary storage for the contents of the MCS surface.
700 * Since the sampler always returns 8 registers worth of data, this is 8
701 * registers wide, even though we only use the first 2 registers of it.
703 struct brw_reg mcs_data
;
705 /* X coordinates. We have two of them so that we can perform coordinate
706 * transformations easily.
708 struct brw_reg x_coords
[2];
710 /* Y coordinates. We have two of them so that we can perform coordinate
711 * transformations easily.
713 struct brw_reg y_coords
[2];
715 /* X, Y coordinates of the pixel from which we need to fetch the specific
716 * sample. These are used for multisample scaled blitting.
718 struct brw_reg x_sample_coords
;
719 struct brw_reg y_sample_coords
;
721 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
722 struct brw_reg x_frac
;
723 struct brw_reg y_frac
;
725 /* Which element of x_coords and y_coords is currently in use.
729 /* True if, at the point in the program currently being compiled, the
730 * sample index is known to be zero.
734 /* Register storing the sample index when s_is_zero is false. */
735 struct brw_reg sample_index
;
741 /* MRF used for sampling and render target writes */
745 brw_blorp_blit_program::brw_blorp_blit_program(
746 struct brw_context
*brw
,
747 const brw_blorp_blit_prog_key
*key
)
748 : mem_ctx(ralloc_context(NULL
)),
752 brw_init_compile(brw
, &func
, mem_ctx
);
755 brw_blorp_blit_program::~brw_blorp_blit_program()
757 ralloc_free(mem_ctx
);
761 brw_blorp_blit_program::compile(struct brw_context
*brw
,
762 GLuint
*program_size
,
766 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
767 /* If the destination image is W tiled and multisampled, then the thread
768 * must be dispatched once per sample, not once per pixel. This is
769 * necessary because after conversion between W and Y tiling, there's no
770 * guarantee that all samples corresponding to a single pixel will still
773 assert(key
->persample_msaa_dispatch
);
777 /* We are blending, which means we won't have an opportunity to
778 * translate the tiling and sample count for the texture surface. So
779 * the surface state for the texture must be configured with the correct
780 * tiling and sample count.
782 assert(!key
->src_tiled_w
);
783 assert(key
->tex_samples
== key
->src_samples
);
784 assert(key
->tex_layout
== key
->src_layout
);
785 assert(key
->tex_samples
> 0);
788 if (key
->persample_msaa_dispatch
) {
789 /* It only makes sense to do persample dispatch if the render target is
790 * configured as multisampled.
792 assert(key
->rt_samples
> 0);
795 /* Make sure layout is consistent with sample count */
796 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
797 (key
->tex_samples
== 0));
798 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
799 (key
->rt_samples
== 0));
800 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
801 (key
->src_samples
== 0));
802 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
803 (key
->dst_samples
== 0));
805 /* Set up prog_data */
806 memset(&prog_data
, 0, sizeof(prog_data
));
807 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
810 * By default everything is emitted as 16-wide with only a few exceptions
811 * handled explicitly either here in the compiler or by one of the specific
812 * code emission calls.
813 * It should be also noted that here in this file any alterations of the
814 * compression control settings are only used to affect the execution size
815 * of the instructions. The instruction template used to initialise all the
816 * instructions is effectively not altered -- the value stays at zero
817 * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
819 * If any other settings are used in the instruction headers, they are set
820 * elsewhere by the individual code emission calls.
822 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
825 compute_frag_coords();
827 /* Render target and texture hardware don't support W tiling. */
828 const bool rt_tiled_w
= false;
829 const bool tex_tiled_w
= false;
831 /* The address that data will be written to is determined by the
832 * coordinates supplied to the WM thread and the tiling and sample count of
833 * the render target, according to the formula:
835 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
837 * If the actual tiling and sample count of the destination surface are not
838 * the same as the configuration of the render target, then these
839 * coordinates are wrong and we have to adjust them to compensate for the
842 if (rt_tiled_w
!= key
->dst_tiled_w
||
843 key
->rt_samples
!= key
->dst_samples
||
844 key
->rt_layout
!= key
->dst_layout
) {
845 encode_msaa(key
->rt_samples
, key
->rt_layout
);
846 /* Now (X, Y, S) = detile(rt_tiling, offset) */
847 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
848 /* Now (X, Y, S) = detile(dst_tiling, offset) */
849 decode_msaa(key
->dst_samples
, key
->dst_layout
);
852 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
854 * That is: X, Y and S now contain the true coordinates and sample index of
855 * the data that the WM thread should output.
857 * If we need to kill pixels that are outside the destination rectangle,
858 * now is the time to do it.
862 kill_if_outside_dst_rect();
864 /* Next, apply a translation to obtain coordinates in the source image. */
865 translate_dst_to_src();
867 /* If the source image is not multisampled, then we want to fetch sample
868 * number 0, because that's the only sample there is.
870 if (key
->src_samples
== 0)
873 /* X, Y, and S are now the coordinates of the pixel in the source image
874 * that we want to texture from. Exception: if we are blending, then S is
875 * irrelevant, because we are going to fetch all samples.
877 if (key
->blend
&& !key
->blit_scaled
) {
879 /* Gen6 hardware an automatically blend using the SAMPLE message */
881 sample(texture_data
[0]);
883 /* Gen7+ hardware doesn't automaticaly blend. */
884 manual_blend_average(key
->src_samples
);
886 } else if(key
->blend
&& key
->blit_scaled
) {
887 manual_blend_bilinear(key
->src_samples
);
889 /* We aren't blending, which means we just want to fetch a single sample
890 * from the source surface. The address that we want to fetch from is
891 * related to the X, Y and S values according to the formula:
893 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
895 * If the actual tiling and sample count of the source surface are not
896 * the same as the configuration of the texture, then we need to adjust
897 * the coordinates to compensate for the difference.
899 if ((tex_tiled_w
!= key
->src_tiled_w
||
900 key
->tex_samples
!= key
->src_samples
||
901 key
->tex_layout
!= key
->src_layout
) &&
902 !key
->bilinear_filter
) {
903 encode_msaa(key
->src_samples
, key
->src_layout
);
904 /* Now (X, Y, S) = detile(src_tiling, offset) */
905 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
906 /* Now (X, Y, S) = detile(tex_tiling, offset) */
907 decode_msaa(key
->tex_samples
, key
->tex_layout
);
910 if (key
->bilinear_filter
) {
911 sample(texture_data
[0]);
914 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
916 * In other words: X, Y, and S now contain values which, when passed to
917 * the texturing unit, will cause data to be read from the correct
918 * memory location. So we can fetch the texel now.
920 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
922 texel_fetch(texture_data
[0]);
926 /* Finally, write the fetched (or blended) value to the render target and
927 * terminate the thread.
929 render_target_write();
931 brw_set_uip_jip(&func
);
933 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
934 printf("Native code for BLORP blit:\n");
935 brw_dump_compile(&func
, dump_file
, 0, func
.next_insn_offset
);
938 return brw_get_program(&func
, program_size
);
942 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
944 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
945 #define ALLOC_REG(name, type) \
947 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
948 base_reg + CONST_LOC(name) / 32, \
949 (CONST_LOC(name) % 32) / 4), type)
951 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
952 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
953 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
954 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
955 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
956 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
957 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
958 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
959 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
960 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
966 brw_blorp_blit_program::alloc_regs()
969 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
970 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
971 prog_data
.first_curbe_grf
= reg
;
972 alloc_push_const_regs(reg
);
973 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
974 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
975 this->texture_data
[i
] =
976 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
980 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
982 for (int i
= 0; i
< 2; ++i
) {
984 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
987 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
991 if (key
->blit_scaled
&& key
->blend
) {
992 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
994 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
996 this->x_frac
= brw_vec8_grf(reg
, 0);
998 this->y_frac
= brw_vec8_grf(reg
, 0);
1002 this->xy_coord_index
= 0;
1004 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1006 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1008 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1011 /* Make sure we didn't run out of registers */
1012 assert(reg
<= GEN7_MRF_HACK_START
);
1015 this->base_mrf
= mrf
;
1018 /* In the code that follows, X and Y can be used to quickly refer to the
1019 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
1020 * prime") to the inactive elements.
1022 * S can be used to quickly refer to sample_index.
1024 #define X x_coords[xy_coord_index]
1025 #define Y y_coords[xy_coord_index]
1026 #define Xp x_coords[!xy_coord_index]
1027 #define Yp y_coords[!xy_coord_index]
1028 #define S sample_index
1030 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
1031 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
1033 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
1036 * Emit code to compute the X and Y coordinates of the pixels being rendered
1037 * by this WM invocation.
1039 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1040 * related to the address offset where outputs will be written by the formula:
1042 * (X, Y, S) = decode_msaa(detile(offset)).
1044 * (See brw_blorp_blit_program).
1047 brw_blorp_blit_program::compute_frag_coords()
1049 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1050 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1051 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1052 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1054 * Pixels within a subspan are laid out in this arrangement:
1058 * So, to compute the coordinates of each pixel, we need to read every 2nd
1059 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1060 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1061 * In other words, the data we want to access is R1.4<2;4,0>UW.
1063 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1064 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1066 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1067 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1069 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1070 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1071 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1074 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1075 * pixels n+2 and n+3 are in the bottom half of the subspan.
1077 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1078 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1080 /* Move the coordinates to UD registers. */
1081 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1082 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1085 if (key
->persample_msaa_dispatch
) {
1086 switch (key
->rt_samples
) {
1088 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1089 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1090 * represent sample 1, and so on.
1092 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1093 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1094 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1095 * then copy from it using vstride=1, width=4, hstride=0.
1097 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1098 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1099 /* Move to UD sample_index register. */
1100 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1101 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1102 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1103 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1107 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1108 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1109 * subspan 1 will represent sample 1, and so on. We can find the
1110 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1111 * Index") and multiplying by two (since samples are always delivered
1112 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1115 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1116 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1117 * variable with the sequence (0, 1, 2, 3), and then reading from it
1118 * using vstride=1, width=4, hstride=0.
1120 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1121 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1122 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1123 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1124 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1125 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1126 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1127 stride(t2_uw1
, 1, 4, 0));
1128 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1129 brw_ADD(&func
, offset(S
, 1),
1130 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1131 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1132 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1136 assert(!"Unrecognized sample count in "
1137 "brw_blorp_blit_program::compute_frag_coords()");
1142 /* Either the destination surface is single-sampled, or the WM will be
1143 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1144 * per pixel). In either case, it's not meaningful to compute a sample
1145 * value. Just set it to 0.
1152 * Emit code to compensate for the difference between Y and W tiling.
1154 * This code modifies the X and Y coordinates according to the formula:
1156 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1158 * (See brw_blorp_blit_program).
1160 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1161 * are booleans where true represents W tiling and false represents Y tiling.
1164 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1166 if (old_tiled_w
== new_tiled_w
)
1169 /* In the code that follows, we can safely assume that S = 0, because W
1170 * tiling formats always use IMS layout.
1175 /* Given X and Y coordinates that describe an address using Y tiling,
1176 * translate to the X and Y coordinates that describe the same address
1179 * If we break down the low order bits of X and Y, using a
1180 * single letter to represent each low-order bit:
1182 * X = A << 7 | 0bBCDEFGH
1183 * Y = J << 5 | 0bKLMNP (1)
1185 * Then we can apply the Y tiling formula to see the memory offset being
1188 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1190 * If we apply the W detiling formula to this memory location, that the
1191 * corresponding X' and Y' coordinates are:
1193 * X' = A << 6 | 0bBCDPFH (3)
1194 * Y' = J << 6 | 0bKLMNEG
1196 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1197 * we need to make the following computation:
1199 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1200 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1202 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1203 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1204 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1205 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1206 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1207 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1208 brw_OR(&func
, Xp
, t1
, t2
);
1209 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1210 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1211 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1212 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1213 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1214 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1215 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1216 brw_OR(&func
, Yp
, t1
, t2
);
1219 /* Applying the same logic as above, but in reverse, we obtain the
1222 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1223 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1225 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1226 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1227 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1228 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1229 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1230 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1231 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1232 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1234 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1235 brw_OR(&func
, Xp
, t1
, t2
);
1236 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1237 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1238 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1239 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1240 brw_OR(&func
, Yp
, t1
, t2
);
1246 * Emit code to compensate for the difference between MSAA and non-MSAA
1249 * This code modifies the X and Y coordinates according to the formula:
1251 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1253 * (See brw_blorp_blit_program).
1256 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1257 intel_msaa_layout layout
)
1260 case INTEL_MSAA_LAYOUT_NONE
:
1261 /* No translation necessary, and S should already be zero. */
1264 case INTEL_MSAA_LAYOUT_CMS
:
1265 /* We can't compensate for compressed layout since at this point in the
1266 * program we haven't read from the MCS buffer.
1268 assert(!"Bad layout in encode_msaa");
1270 case INTEL_MSAA_LAYOUT_UMS
:
1271 /* No translation necessary. */
1273 case INTEL_MSAA_LAYOUT_IMS
:
1274 switch (num_samples
) {
1276 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1277 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1278 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1280 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1282 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1283 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1285 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1287 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1288 brw_OR(&func
, Xp
, t1
, t2
);
1289 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1290 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1292 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1293 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1295 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1296 brw_OR(&func
, Yp
, t1
, t2
);
1299 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1300 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1302 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1304 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1305 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1307 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1308 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1309 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1310 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1311 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1314 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1315 brw_OR(&func
, Xp
, t1
, t2
);
1316 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1317 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1319 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1320 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1322 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1323 brw_OR(&func
, Yp
, t1
, t2
);
1333 * Emit code to compensate for the difference between MSAA and non-MSAA
1336 * This code modifies the X and Y coordinates according to the formula:
1338 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1340 * (See brw_blorp_blit_program).
1343 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1344 intel_msaa_layout layout
)
1347 case INTEL_MSAA_LAYOUT_NONE
:
1348 /* No translation necessary, and S should already be zero. */
1351 case INTEL_MSAA_LAYOUT_CMS
:
1352 /* We can't compensate for compressed layout since at this point in the
1353 * program we don't have access to the MCS buffer.
1355 assert(!"Bad layout in encode_msaa");
1357 case INTEL_MSAA_LAYOUT_UMS
:
1358 /* No translation necessary. */
1360 case INTEL_MSAA_LAYOUT_IMS
:
1362 switch (num_samples
) {
1364 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1365 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1366 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1367 * S = (Y & 0b10) | (X & 0b10) >> 1
1369 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1370 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1371 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1372 brw_OR(&func
, Xp
, t1
, t2
);
1373 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1374 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1375 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1376 brw_OR(&func
, Yp
, t1
, t2
);
1377 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1378 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1379 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1380 brw_OR(&func
, S
, t1
, t2
);
1383 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1384 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1385 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1386 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1388 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1389 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1390 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1391 brw_OR(&func
, Xp
, t1
, t2
);
1392 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1393 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1394 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1395 brw_OR(&func
, Yp
, t1
, t2
);
1396 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1397 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1398 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1399 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1400 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1401 brw_OR(&func
, S
, t1
, t2
);
1411 * Emit code that kills pixels whose X and Y coordinates are outside the
1412 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1416 brw_blorp_blit_program::kill_if_outside_dst_rect()
1418 struct brw_reg f0
= brw_flag_reg(0, 0);
1419 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1420 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1422 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1423 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1424 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1425 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1427 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1429 struct brw_instruction
*inst
= brw_AND(&func
, g1
, f0
, g1
);
1430 inst
->header
.mask_control
= BRW_MASK_DISABLE
;
1434 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1438 brw_blorp_blit_program::translate_dst_to_src()
1440 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1441 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1442 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1443 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1445 /* Move the UD coordinates to float registers. */
1446 brw_MOV(&func
, Xp_f
, X
);
1447 brw_MOV(&func
, Yp_f
, Y
);
1448 /* Scale and offset */
1449 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1450 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1451 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1452 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1453 if (key
->blit_scaled
&& key
->blend
) {
1454 /* Translate coordinates to lay out the samples in a rectangular grid
1455 * roughly corresponding to sample locations.
1457 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1458 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1459 /* Adjust coordinates so that integers represent pixel centers rather
1462 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1463 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1465 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1466 * texels on texture edges.
1468 clamp_tex_coords(X_f
, Y_f
,
1469 brw_imm_f(0.0), brw_imm_f(0.0),
1470 rect_grid_x1
, rect_grid_y1
);
1472 /* Store the fractional parts to be used as bilinear interpolation
1475 brw_FRC(&func
, x_frac
, X_f
);
1476 brw_FRC(&func
, y_frac
, Y_f
);
1478 /* Round the float coordinates down to nearest integer */
1479 brw_RNDD(&func
, Xp_f
, X_f
);
1480 brw_RNDD(&func
, Yp_f
, Y_f
);
1481 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1482 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1484 } else if (!key
->bilinear_filter
) {
1485 /* Round the float coordinates down to nearest integer by moving to
1488 brw_MOV(&func
, Xp
, X_f
);
1489 brw_MOV(&func
, Yp
, Y_f
);
1495 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1496 struct brw_reg regY
,
1497 struct brw_reg clampX0
,
1498 struct brw_reg clampY0
,
1499 struct brw_reg clampX1
,
1500 struct brw_reg clampY1
)
1502 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regX
, clampX0
);
1503 brw_MOV(&func
, regX
, clampX0
);
1504 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1506 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regX
, clampX1
);
1507 brw_MOV(&func
, regX
, clampX1
);
1508 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1510 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regY
, clampY0
);
1511 brw_MOV(&func
, regY
, clampY0
);
1512 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1514 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regY
, clampY1
);
1515 brw_MOV(&func
, regY
, clampY1
);
1516 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1520 * Emit code to transform the X and Y coordinates as needed for blending
1521 * together the different samples in an MSAA texture.
1524 brw_blorp_blit_program::single_to_blend()
1526 /* When looking up samples in an MSAA texture using the SAMPLE message,
1527 * Gen6 requires the texture coordinates to be odd integers (so that they
1528 * correspond to the center of a 2x2 block representing the four samples
1529 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1530 * each by 2 and then add 1.
1532 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1533 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1534 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1535 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1541 * Count the number of trailing 1 bits in the given value. For example:
1543 * count_trailing_one_bits(0) == 0
1544 * count_trailing_one_bits(7) == 3
1545 * count_trailing_one_bits(11) == 2
1547 inline int count_trailing_one_bits(unsigned value
)
1549 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1550 return __builtin_ctz(~value
);
1552 return _mesa_bitcount(value
& ~(value
+ 1));
1558 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1560 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1563 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1565 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1567 * This ensures that when all samples have the same value, no numerical
1568 * precision is lost, since each addition operation always adds two equal
1569 * values, and summing two equal floating point values does not lose
1572 * We perform this computation by treating the texture_data array as a
1573 * stack and performing the following operations:
1575 * - push sample 0 onto stack
1576 * - push sample 1 onto stack
1577 * - add top two stack entries
1578 * - push sample 2 onto stack
1579 * - push sample 3 onto stack
1580 * - add top two stack entries
1581 * - add top two stack entries
1582 * - divide top stack entry by 4
1584 * Note that after pushing sample i onto the stack, the number of add
1585 * operations we do is equal to the number of trailing 1 bits in i. This
1586 * works provided the total number of samples is a power of two, which it
1587 * always is for i965.
1589 * For integer formats, we replace the add operations with average
1590 * operations and skip the final division.
1592 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1596 brw_op2_ptr combine_op
=
1597 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1598 unsigned stack_depth
= 0;
1599 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1600 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1602 /* Push sample i onto the stack */
1603 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1608 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1610 texel_fetch(texture_data
[stack_depth
++]);
1612 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1613 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1614 * suggests an optimization:
1616 * "A simple optimization with probable large return in
1617 * performance is to compare the MCS value to zero (indicating
1618 * all samples are on sample slice 0), and sample only from
1619 * sample slice 0 using ld2dss if MCS is zero."
1621 * Note that in the case where the MCS value is zero, sampling from
1622 * sample slice 0 using ld2dss and sampling from sample 0 using
1623 * ld2dms are equivalent (since all samples are on sample slice 0).
1624 * Since we have already sampled from sample 0, all we need to do is
1625 * skip the remaining fetches and averaging if MCS is zero.
1627 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1628 mcs_data
, brw_imm_ud(0));
1629 brw_IF(&func
, BRW_EXECUTE_16
);
1632 /* Do count_trailing_one_bits(i) times */
1633 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1634 assert(stack_depth
>= 2);
1637 /* TODO: should use a smaller loop bound for non_RGBA formats */
1638 for (int k
= 0; k
< 4; ++k
) {
1639 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1640 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1641 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1646 /* We should have just 1 sample on the stack now. */
1647 assert(stack_depth
== 1);
1649 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1650 /* Scale the result down by a factor of num_samples */
1651 /* TODO: should use a smaller loop bound for non-RGBA formats */
1652 for (int j
= 0; j
< 4; ++j
) {
1653 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1654 offset(vec8(texture_data
[0]), 2*j
),
1655 brw_imm_f(1.0/num_samples
));
1659 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1664 brw_blorp_blit_program::emit_lrp(const struct brw_reg
&dst
,
1665 const struct brw_reg
&src1
,
1666 const struct brw_reg
&src2
,
1667 const struct brw_reg
&src3
)
1669 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1670 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1671 brw_LRP(&func
, dst
, src1
, src2
, src3
);
1672 brw_set_compression_control(&func
, BRW_COMPRESSION_2NDHALF
);
1673 brw_LRP(&func
, sechalf(dst
), sechalf(src1
), sechalf(src2
), sechalf(src3
));
1674 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1675 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1679 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1681 /* We do this computation by performing the following operations:
1683 * In case of 4x, 8x MSAA:
1684 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1685 * which are later used for interpolation
1686 * - linearly interpolate samples a and b in X
1687 * - linearly interpolate samples c and d in X
1688 * - linearly interpolate the results of last two operations in Y
1690 * result = lrp(lrp(a + b) + lrp(c + d))
1692 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1693 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1694 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1695 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1697 for (unsigned i
= 0; i
< 4; ++i
) {
1698 assert(i
< ARRAY_SIZE(texture_data
));
1701 /* Compute pixel coordinates */
1702 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1703 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1704 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1705 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1706 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1707 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1709 /* The MCS value we fetch has to match up with the pixel that we're
1710 * sampling from. Since we sample from different pixels in each
1711 * iteration of this "for" loop, the call to mcs_fetch() should be
1712 * here inside the loop after computing the pixel coordinates.
1714 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1717 /* Compute sample index and map the sample index to a sample number.
1718 * Sample index layout shows the numbering of slots in a rectangular
1719 * grid of samples with in a pixel. Sample number layout shows the
1720 * rectangular grid of samples roughly corresponding to the real sample
1721 * locations with in a pixel.
1722 * In case of 4x MSAA, layout of sample indices matches the layout of
1730 * In case of 8x MSAA the two layouts don't match.
1731 * sample index layout : --------- sample number layout : ---------
1732 * | 0 | 1 | | 5 | 2 |
1733 * --------- ---------
1734 * | 2 | 3 | | 4 | 6 |
1735 * --------- ---------
1736 * | 4 | 5 | | 0 | 3 |
1737 * --------- ---------
1738 * | 6 | 7 | | 7 | 1 |
1739 * --------- ---------
1741 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1742 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1743 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1744 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1745 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1746 brw_MOV(&func
, vec16(S
), t1_f
);
1748 if (num_samples
== 8) {
1749 /* Map the sample index to a sample number */
1750 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1752 brw_IF(&func
, BRW_EXECUTE_16
);
1754 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1755 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1757 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1758 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1759 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1761 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1762 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1763 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1765 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1766 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1770 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1771 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1773 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1774 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1775 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1777 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1778 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1779 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1781 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1782 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1785 brw_MOV(&func
, vec16(S
), t2
);
1787 texel_fetch(texture_data
[i
]);
1790 #define SAMPLE(x, y) offset(texture_data[x], y)
1791 for (int index
= 3; index
> 0; ) {
1792 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1793 * Counter value of 8 in 'for' loop below is used to interpolate all
1794 * the color components.
1796 for (int k
= 0; k
< 8; k
+= 2)
1797 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1799 vec8(SAMPLE(index
, k
)),
1800 vec8(SAMPLE(index
- 1, k
)));
1803 for (int k
= 0; k
< 8; k
+= 2)
1804 emit_lrp(vec8(SAMPLE(0, k
)),
1807 vec8(SAMPLE(0, k
)));
1812 * Emit code to look up a value in the texture using the SAMPLE message (which
1813 * does blending of MSAA surfaces).
1816 brw_blorp_blit_program::sample(struct brw_reg dst
)
1818 static const sampler_message_arg args
[2] = {
1819 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1820 SAMPLER_MESSAGE_ARG_V_FLOAT
1823 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
,
1828 * Emit code to look up a value in the texture using the SAMPLE_LD message
1829 * (which does a simple texel fetch).
1832 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1834 static const sampler_message_arg gen6_args
[5] = {
1835 SAMPLER_MESSAGE_ARG_U_INT
,
1836 SAMPLER_MESSAGE_ARG_V_INT
,
1837 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1838 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1839 SAMPLER_MESSAGE_ARG_SI_INT
1841 static const sampler_message_arg gen7_ld_args
[3] = {
1842 SAMPLER_MESSAGE_ARG_U_INT
,
1843 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1844 SAMPLER_MESSAGE_ARG_V_INT
1846 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1847 SAMPLER_MESSAGE_ARG_SI_INT
,
1848 SAMPLER_MESSAGE_ARG_U_INT
,
1849 SAMPLER_MESSAGE_ARG_V_INT
1851 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1852 SAMPLER_MESSAGE_ARG_SI_INT
,
1853 SAMPLER_MESSAGE_ARG_MCS_INT
,
1854 SAMPLER_MESSAGE_ARG_U_INT
,
1855 SAMPLER_MESSAGE_ARG_V_INT
1860 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1864 switch (key
->tex_layout
) {
1865 case INTEL_MSAA_LAYOUT_IMS
:
1866 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1869 * If this field is MSFMT_DEPTH_STENCIL
1870 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1871 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1873 * So fall through to emit the same message as we use for
1874 * INTEL_MSAA_LAYOUT_CMS.
1876 case INTEL_MSAA_LAYOUT_CMS
:
1877 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1878 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1880 case INTEL_MSAA_LAYOUT_UMS
:
1881 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1882 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1884 case INTEL_MSAA_LAYOUT_NONE
:
1886 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1887 ARRAY_SIZE(gen7_ld_args
));
1892 assert(!"Should not get here.");
1898 brw_blorp_blit_program::mcs_fetch()
1900 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1901 SAMPLER_MESSAGE_ARG_U_INT
,
1902 SAMPLER_MESSAGE_ARG_V_INT
1904 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1905 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1909 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1911 const sampler_message_arg
*args
,
1914 struct brw_reg mrf
=
1915 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1916 for (int arg
= 0; arg
< num_args
; ++arg
) {
1917 switch (args
[arg
]) {
1918 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1919 if (key
->bilinear_filter
)
1920 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1921 retype(X
, BRW_REGISTER_TYPE_F
));
1923 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1925 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1926 if (key
->bilinear_filter
)
1927 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1928 retype(Y
, BRW_REGISTER_TYPE_F
));
1930 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1932 case SAMPLER_MESSAGE_ARG_U_INT
:
1933 brw_MOV(&func
, mrf
, X
);
1935 case SAMPLER_MESSAGE_ARG_V_INT
:
1936 brw_MOV(&func
, mrf
, Y
);
1938 case SAMPLER_MESSAGE_ARG_SI_INT
:
1939 /* Note: on Gen7, this code may be reached with s_is_zero==true
1940 * because in Gen7's ld2dss message, the sample index is the first
1941 * argument. When this happens, we need to move a 0 into the
1942 * appropriate message register.
1945 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1947 brw_MOV(&func
, mrf
, S
);
1949 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1950 switch (key
->tex_layout
) {
1951 case INTEL_MSAA_LAYOUT_CMS
:
1952 brw_MOV(&func
, mrf
, mcs_data
);
1954 case INTEL_MSAA_LAYOUT_IMS
:
1955 /* When sampling from an IMS surface, MCS data is not relevant,
1956 * and the hardware ignores it. So don't bother populating it.
1960 /* We shouldn't be trying to send MCS data with any other
1963 assert (!"Unsupported layout for MCS data");
1967 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1968 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1975 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1976 base_mrf
/* msg_reg_nr */,
1977 brw_message_reg(base_mrf
) /* src0 */,
1978 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1981 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1982 mrf
.nr
- base_mrf
/* msg_length */,
1983 0 /* header_present */,
1984 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1985 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1993 #undef SWAP_XY_AND_XPYP
1996 brw_blorp_blit_program::render_target_write()
1998 struct brw_reg mrf_rt_write
=
1999 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
2002 /* If we may have killed pixels, then we need to send R0 and R1 in a header
2003 * so that the render target knows which pixels we killed.
2005 bool use_header
= key
->use_kill
;
2007 /* Copy R0/1 to MRF */
2008 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
2009 retype(R0
, BRW_REGISTER_TYPE_UD
));
2013 /* Copy texture data to MRFs */
2014 for (int i
= 0; i
< 4; ++i
) {
2015 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
2016 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
2017 offset(vec8(texture_data
[0]), 2*i
));
2021 /* Now write to the render target and terminate the thread */
2023 16 /* dispatch_width */,
2024 base_mrf
/* msg_reg_nr */,
2025 mrf_rt_write
/* src0 */,
2026 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
2027 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
2028 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
2029 0 /* response_length */,
2036 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
2037 GLfloat dst0
, GLfloat dst1
,
2040 float scale
= (src1
- src0
) / (dst1
- dst0
);
2042 /* When not mirroring a coordinate (say, X), we need:
2043 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
2045 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
2047 * blorp program uses "round toward zero" to convert the
2048 * transformed floating point coordinates to integer coordinates,
2049 * whereas the behaviour we actually want is "round to nearest",
2050 * so 0.5 provides the necessary correction.
2053 offset
= src0
+ (-dst0
+ 0.5) * scale
;
2055 /* When mirroring X we need:
2056 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2058 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2060 multiplier
= -scale
;
2061 offset
= src0
+ (dst1
- 0.5) * scale
;
2067 * Determine which MSAA layout the GPU pipeline should be configured for,
2068 * based on the chip generation, the number of samples, and the true layout of
2069 * the image in memory.
2071 inline intel_msaa_layout
2072 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2073 intel_msaa_layout true_layout
)
2075 if (num_samples
<= 1) {
2076 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2077 * format buffers, by transforming coordinates appropriately.
2079 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2080 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2081 return INTEL_MSAA_LAYOUT_NONE
;
2083 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2086 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2087 if (brw
->gen
== 6) {
2088 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2095 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2096 struct intel_mipmap_tree
*src_mt
,
2097 unsigned src_level
, unsigned src_layer
,
2098 struct intel_mipmap_tree
*dst_mt
,
2099 unsigned dst_level
, unsigned dst_layer
,
2100 GLfloat src_x0
, GLfloat src_y0
,
2101 GLfloat src_x1
, GLfloat src_y1
,
2102 GLfloat dst_x0
, GLfloat dst_y0
,
2103 GLfloat dst_x1
, GLfloat dst_y1
,
2105 bool mirror_x
, bool mirror_y
)
2107 struct gl_context
*ctx
= &brw
->ctx
;
2108 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2110 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
2111 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
2113 /* Even though we do multisample resolves at the time of the blit, OpenGL
2114 * specification defines them as if they happen at the time of rendering,
2115 * which means that the type of averaging we do during the resolve should
2116 * only depend on the source format; the destination format should be
2117 * ignored. But, specification doesn't seem to be strict about it.
2119 * It has been observed that mulitisample resolves produce slightly better
2120 * looking images when averaging is done using destination format. NVIDIA's
2121 * proprietary OpenGL driver also follow this approach. So, we choose to
2122 * follow it in our driver.
2124 * When multisampling, if the source and destination formats are equal
2125 * (aside from the color space), we choose to blit in sRGB space to get
2126 * this higher quality image.
2128 if (src
.num_samples
> 1 &&
2129 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
2130 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2131 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2132 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2133 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2136 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
2137 * texture, the above code configures the source format for L32_FLOAT or
2138 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
2139 * the SAMPLE message appears to handle multisampled L32_FLOAT and
2140 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
2141 * around the problem by using a source format of R32_FLOAT. This
2142 * shouldn't affect rendering correctness, since the destination format is
2143 * R32_FLOAT, so only the contents of the red channel matters.
2145 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
2146 src_mt
->format
== dst_mt
->format
&&
2147 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
2148 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2152 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2154 /* texture_data_type indicates the register type that should be used to
2155 * manipulate texture data.
2157 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2158 case GL_UNSIGNED_NORMALIZED
:
2159 case GL_SIGNED_NORMALIZED
:
2161 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2163 case GL_UNSIGNED_INT
:
2164 if (src_mt
->format
== MESA_FORMAT_S8
) {
2165 /* We process stencil as though it's an unsigned normalized color */
2166 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2168 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2172 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2175 assert(!"Unrecognized blorp format");
2180 /* Gen7's rendering hardware only supports the IMS layout for depth and
2181 * stencil render targets. Blorp always maps its destination surface as
2182 * a color render target (even if it's actually a depth or stencil
2183 * buffer). So if the destination is IMS, we'll have to map it as a
2184 * single-sampled texture and interleave the samples ourselves.
2186 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2187 dst
.num_samples
= 0;
2190 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2191 /* If the destination surface is a W-tiled multisampled stencil buffer
2192 * that we're mapping as Y tiled, then we need to arrange for the WM
2193 * program to run once per sample rather than once per pixel, because
2194 * the memory layout of related samples doesn't match between W and Y
2197 wm_prog_key
.persample_msaa_dispatch
= true;
2200 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2201 /* We are blitting from a multisample buffer to a multisample buffer, so
2202 * we must preserve samples within a pixel. This means we have to
2203 * arrange for the WM program to run once per sample rather than once
2206 wm_prog_key
.persample_msaa_dispatch
= true;
2209 /* Scaled blitting or not. */
2210 wm_prog_key
.blit_scaled
=
2211 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2212 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2214 /* Scaling factors used for bilinear filtering in multisample scaled
2217 wm_prog_key
.x_scale
= 2.0;
2218 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2220 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2221 wm_prog_key
.bilinear_filter
= true;
2223 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2224 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2225 base_format
!= GL_STENCIL_INDEX
&&
2226 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2227 /* We are downsampling a color buffer, so blend. */
2228 wm_prog_key
.blend
= true;
2231 /* src_samples and dst_samples are the true sample counts */
2232 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2233 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2235 /* tex_samples and rt_samples are the sample counts that are set up in
2238 wm_prog_key
.tex_samples
= src
.num_samples
;
2239 wm_prog_key
.rt_samples
= dst
.num_samples
;
2241 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2242 * use to access the source and destination surfaces.
2244 wm_prog_key
.tex_layout
=
2245 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2246 wm_prog_key
.rt_layout
=
2247 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2249 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2252 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2253 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2255 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2256 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2257 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2258 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2259 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2260 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2261 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2262 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2264 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2265 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2267 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2268 /* We must expand the rectangle we send through the rendering pipeline,
2269 * to account for the fact that we are mapping the destination region as
2270 * single-sampled when it is in fact multisampled. We must also align
2271 * it to a multiple of the multisampling pattern, because the
2272 * differences between multisampled and single-sampled surface formats
2273 * will mean that pixels are scrambled within the multisampling pattern.
2274 * TODO: what if this makes the coordinates too large?
2276 * Note: this only works if the destination surface uses the IMS layout.
2277 * If it's UMS, then we have no choice but to set up the rendering
2278 * pipeline as multisampled.
2280 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2281 switch (dst_mt
->num_samples
) {
2283 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2284 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2285 x1
= ALIGN(x1
* 2, 4);
2286 y1
= ALIGN(y1
* 2, 4);
2289 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2290 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2291 x1
= ALIGN(x1
* 4, 8);
2292 y1
= ALIGN(y1
* 2, 4);
2295 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2298 wm_prog_key
.use_kill
= true;
2301 if (dst
.map_stencil_as_y_tiled
) {
2302 /* We must modify the rectangle we send through the rendering pipeline
2303 * (and the size and x/y offset of the destination surface), to account
2304 * for the fact that we are mapping it as Y-tiled when it is in fact
2307 * Both Y tiling and W tiling can be understood as organizations of
2308 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2309 * is different, but the layout of the 32-byte sub-tiles within the 4k
2310 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2311 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2312 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2314 * Therefore, to account for the layout differences within the 32-byte
2315 * sub-tiles, we must expand the rectangle so the X coordinates of its
2316 * edges are multiples of 8 (the W sub-tile width), and its Y
2317 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2318 * Then we need to scale the X and Y coordinates of the rectangle to
2319 * account for the differences in aspect ratio between the Y and W
2320 * sub-tiles. We need to modify the layer width and height similarly.
2322 * A correction needs to be applied when MSAA is in use: since
2323 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2324 * we need to align the Y coordinates to multiples of 8, so that when
2325 * they are divided by two they are still multiples of 4.
2327 * Note: Since the x/y offset of the surface will be applied using the
2328 * SURFACE_STATE command packet, it will be invisible to the swizzling
2329 * code in the shader; therefore it needs to be in a multiple of the
2330 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2331 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2332 * buffer), and the miplevel alignment used for stencil buffers is 8
2333 * pixels horizontally and either 4 or 8 pixels vertically (see
2334 * intel_horizontal_texture_alignment_unit() and
2335 * intel_vertical_texture_alignment_unit()).
2337 * Note: Also, since the SURFACE_STATE command packet can only apply
2338 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2339 * vertically, it is important that the offsets will be multiples of
2340 * these sizes after they are converted into Y-tiled coordinates.
2341 * Fortunately they will be, since we know from above that the offsets
2342 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2343 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2345 * TODO: what if this makes the coordinates (or the texture size) too
2348 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2349 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2350 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2351 x1
= ALIGN(x1
, x_align
) * 2;
2352 y1
= ALIGN(y1
, y_align
) / 2;
2353 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2354 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2357 wm_prog_key
.use_kill
= true;
2360 if (src
.map_stencil_as_y_tiled
) {
2361 /* We must modify the size and x/y offset of the source surface to
2362 * account for the fact that we are mapping it as Y-tiled when it is in
2365 * See the comments above concerning x/y offset alignment for the
2366 * destination surface.
2368 * TODO: what if this makes the texture size too large?
2370 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2371 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2372 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2379 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2380 brw_blorp_prog_data
**prog_data
) const
2382 uint32_t prog_offset
= 0;
2383 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2384 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2385 &prog_offset
, prog_data
)) {
2386 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2387 GLuint program_size
;
2388 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2389 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2390 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2391 program
, program_size
,
2392 &prog
.prog_data
, sizeof(prog
.prog_data
),
2393 &prog_offset
, prog_data
);
2399 brw_blorp_blit_test_compile(struct brw_context
*brw
,
2400 const brw_blorp_blit_prog_key
*key
,
2403 GLuint program_size
;
2404 brw_blorp_blit_program
prog(brw
, key
);
2405 INTEL_DEBUG
|= DEBUG_BLORP
;
2406 prog
.compile(brw
, &program_size
, out
);