2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
37 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 * Helper function for handling mirror image blits.
42 * If coord0 > coord1, swap them and invert the "mirror" boolean.
45 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
47 if (coord0
> coord1
) {
57 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
58 * destination coordinates.
60 * Return true if there is still blitting to do, false if all pixels got
61 * rejected by the clip and/or scissor.
63 * For clarity, the nomenclature of this function assumes we are clipping and
64 * scissoring the X coordinate; the exact same logic applies for Y
67 * Note: this function may also be used to account for clipping of source
68 * coordinates, by swapping the roles of src and dst.
71 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
72 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
74 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
75 /* If we are going to scissor everything away, stop. */
76 if (!(fb_xmin
< fb_xmax
&&
83 /* Clip the destination rectangle, and keep track of how many pixels we
84 * clipped off of the left and right sides of it.
86 GLint pixels_clipped_left
= 0;
87 GLint pixels_clipped_right
= 0;
88 if (dst_x0
< fb_xmin
) {
89 pixels_clipped_left
= fb_xmin
- dst_x0
;
92 if (fb_xmax
< dst_x1
) {
93 pixels_clipped_right
= dst_x1
- fb_xmax
;
97 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
98 * the source coordinates, we need to flip them to account for the
102 GLint tmp
= pixels_clipped_left
;
103 pixels_clipped_left
= pixels_clipped_right
;
104 pixels_clipped_right
= tmp
;
107 /* Adjust the source rectangle to remove the pixels corresponding to those
108 * that were clipped/scissored out of the destination rectangle.
110 src_x0
+= pixels_clipped_left
* scale
;
111 src_x1
-= pixels_clipped_right
* scale
;
117 static struct intel_mipmap_tree
*
118 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
120 struct intel_mipmap_tree
*mt
= irb
->mt
;
121 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
127 brw_blorp_blit_miptrees(struct brw_context
*brw
,
128 struct intel_mipmap_tree
*src_mt
,
129 unsigned src_level
, unsigned src_layer
,
130 struct intel_mipmap_tree
*dst_mt
,
131 unsigned dst_level
, unsigned dst_layer
,
132 float src_x0
, float src_y0
,
133 float src_x1
, float src_y1
,
134 float dst_x0
, float dst_y0
,
135 float dst_x1
, float dst_y1
,
136 bool mirror_x
, bool mirror_y
)
138 /* Get ready to blit. This includes depth resolving the src and dst
139 * buffers if necessary. Note: it's not necessary to do a color resolve on
140 * the destination buffer because we use the standard render path to render
141 * to destination color buffers, and the standard render path is
144 intel_miptree_resolve_color(brw
, src_mt
);
145 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
146 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
148 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
149 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
151 _mesa_get_format_name(src_mt
->format
), src_mt
,
152 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
153 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
154 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
157 brw_blorp_blit_params
params(brw
,
158 src_mt
, src_level
, src_layer
,
159 dst_mt
, dst_level
, dst_layer
,
165 brw_blorp_exec(brw
, ¶ms
);
167 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
171 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
172 struct intel_renderbuffer
*src_irb
,
173 struct intel_renderbuffer
*dst_irb
,
174 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
175 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
176 bool mirror_x
, bool mirror_y
)
178 /* Find source/dst miptrees */
179 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
180 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
183 brw_blorp_blit_miptrees(brw
,
184 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
185 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
186 srcX0
, srcY0
, srcX1
, srcY1
,
187 dstX0
, dstY0
, dstX1
, dstY1
,
190 intel_renderbuffer_set_needs_downsample(dst_irb
);
194 color_formats_match(gl_format src_format
, gl_format dst_format
)
196 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
197 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
199 /* Normally, we require the formats to be equal. However, we also support
200 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
201 * (overriding alpha to 1.0 via blending).
203 return linear_src_format
== linear_dst_format
||
204 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
205 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
206 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
207 linear_dst_format
== MESA_FORMAT_XRGB8888
);
211 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
212 struct intel_renderbuffer
*dst_irb
)
214 /* Note: don't just check gl_renderbuffer::Format, because in some cases
215 * multiple gl_formats resolve to the same native type in the miptree (for
216 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
217 * between those formats.
219 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
220 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
222 return color_formats_match(src_format
, dst_format
);
226 try_blorp_blit(struct brw_context
*brw
,
227 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
228 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
229 GLenum filter
, GLbitfield buffer_bit
)
231 struct gl_context
*ctx
= &brw
->ctx
;
233 /* Sync up the state of window system buffers. We need to do this before
234 * we go looking for the buffers.
236 intel_prepare_render(brw
);
238 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
239 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
241 /* Detect if the blit needs to be mirrored */
242 bool mirror_x
= false, mirror_y
= false;
243 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
244 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
245 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
246 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
248 /* Linear filtering is not yet implemented in blorp engine. So, fallback
249 * to other blit paths.
251 if ((srcX1
- srcX0
!= dstX1
- dstX0
||
252 srcY1
- srcY0
!= dstY1
- dstY0
) &&
256 /* If the destination rectangle needs to be clipped or scissored, do so.
258 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
259 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
260 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
261 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
262 /* Everything got clipped/scissored away, so the blit was successful. */
266 /* If the source rectangle needs to be clipped or scissored, do so. */
267 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
268 0, read_fb
->Width
) &&
269 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
270 0, read_fb
->Height
))) {
271 /* Everything got clipped/scissored away, so the blit was successful. */
275 /* Account for the fact that in the system framebuffer, the origin is at
278 if (_mesa_is_winsys_fbo(read_fb
)) {
279 GLint tmp
= read_fb
->Height
- srcY0
;
280 srcY0
= read_fb
->Height
- srcY1
;
282 mirror_y
= !mirror_y
;
284 if (_mesa_is_winsys_fbo(draw_fb
)) {
285 GLint tmp
= draw_fb
->Height
- dstY0
;
286 dstY0
= draw_fb
->Height
- dstY1
;
288 mirror_y
= !mirror_y
;
292 struct intel_renderbuffer
*src_irb
;
293 struct intel_renderbuffer
*dst_irb
;
294 switch (buffer_bit
) {
295 case GL_COLOR_BUFFER_BIT
:
296 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
297 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
298 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
299 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
302 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
303 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
305 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
306 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
310 case GL_DEPTH_BUFFER_BIT
:
312 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
314 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
315 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
317 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
318 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
321 case GL_STENCIL_BUFFER_BIT
:
323 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
325 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
326 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
328 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
329 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
340 brw_blorp_copytexsubimage(struct brw_context
*brw
,
341 struct gl_renderbuffer
*src_rb
,
342 struct gl_texture_image
*dst_image
,
344 int srcX0
, int srcY0
,
345 int dstX0
, int dstY0
,
346 int width
, int height
)
348 struct gl_context
*ctx
= &brw
->ctx
;
349 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
350 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
352 /* Sync up the state of window system buffers. We need to do this before
353 * we go looking at the src renderbuffer's miptree.
355 intel_prepare_render(brw
);
357 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
358 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
360 /* BLORP is not supported before Gen6. */
364 if (!color_formats_match(src_mt
->format
, dst_mt
->format
)) {
368 /* Source clipping shouldn't be necessary, since copytexsubimage (in
369 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
372 * Destination clipping shouldn't be necessary since the restrictions on
373 * glCopyTexSubImage prevent the user from specifying a destination rectangle
374 * that falls outside the bounds of the destination texture.
375 * See error_check_subtexture_dimensions().
378 int srcY1
= srcY0
+ height
;
379 int srcX1
= srcX0
+ width
;
380 int dstX1
= dstX0
+ width
;
381 int dstY1
= dstY0
+ height
;
383 /* Account for the fact that in the system framebuffer, the origin is at
386 bool mirror_y
= false;
387 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
388 GLint tmp
= src_rb
->Height
- srcY0
;
389 srcY0
= src_rb
->Height
- srcY1
;
394 brw_blorp_blit_miptrees(brw
,
395 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
396 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
397 srcX0
, srcY0
, srcX1
, srcY1
,
398 dstX0
, dstY0
, dstX1
, dstY1
,
401 /* If we're copying to a packed depth stencil texture and the source
402 * framebuffer has separate stencil, we need to also copy the stencil data
405 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
406 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
408 src_irb
= intel_renderbuffer(src_rb
);
409 src_mt
= src_irb
->mt
;
411 if (src_mt
->stencil_mt
)
412 src_mt
= src_mt
->stencil_mt
;
413 if (dst_mt
->stencil_mt
)
414 dst_mt
= dst_mt
->stencil_mt
;
416 if (src_mt
!= dst_mt
) {
417 brw_blorp_blit_miptrees(brw
,
418 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
419 dst_mt
, dst_image
->Level
,
420 dst_image
->Face
+ slice
,
421 srcX0
, srcY0
, srcX1
, srcY1
,
422 dstX0
, dstY0
, dstX1
, dstY1
,
432 brw_blorp_framebuffer(struct brw_context
*brw
,
433 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
434 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
435 GLbitfield mask
, GLenum filter
)
437 /* BLORP is not supported before Gen6. */
441 static GLbitfield buffer_bits
[] = {
444 GL_STENCIL_BUFFER_BIT
,
447 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
448 if ((mask
& buffer_bits
[i
]) &&
450 srcX0
, srcY0
, srcX1
, srcY1
,
451 dstX0
, dstY0
, dstX1
, dstY1
,
452 filter
, buffer_bits
[i
])) {
453 mask
&= ~buffer_bits
[i
];
462 * Enum to specify the order of arguments in a sampler message
464 enum sampler_message_arg
466 SAMPLER_MESSAGE_ARG_U_FLOAT
,
467 SAMPLER_MESSAGE_ARG_V_FLOAT
,
468 SAMPLER_MESSAGE_ARG_U_INT
,
469 SAMPLER_MESSAGE_ARG_V_INT
,
470 SAMPLER_MESSAGE_ARG_SI_INT
,
471 SAMPLER_MESSAGE_ARG_MCS_INT
,
472 SAMPLER_MESSAGE_ARG_ZERO_INT
,
476 * Generator for WM programs used in BLORP blits.
478 * The bulk of the work done by the WM program is to wrap and unwrap the
479 * coordinate transformations used by the hardware to store surfaces in
480 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
481 * sample index for a multisampled surface) to a memory offset by the
482 * following formulas:
484 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
485 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
487 * For a single-sampled surface, or for a multisampled surface using
488 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
491 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
492 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
493 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
494 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
496 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
497 * embeds the sample number into bit 1 of the X and Y coordinates:
499 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
500 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
501 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
502 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
503 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
504 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
505 * S = (Y & 0b10) | (X & 0b10) >> 1
507 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
508 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
511 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
512 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
513 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
514 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
515 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
516 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
517 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
519 * For X tiling, tile() combines together the low-order bits of the X and Y
520 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
521 * bytes wide and 8 rows high:
523 * tile(x_tiled, X, Y, S) = A
524 * where A = tile_num << 12 | offset
525 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
526 * offset = (Y' & 0b111) << 9
527 * | (X & 0b111111111)
529 * Y' = Y + S * qpitch
530 * detile(x_tiled, A) = (X, Y, S)
534 * Y' = (tile_num / tile_pitch) << 3
535 * | (A & 0b111000000000) >> 9
536 * X' = (tile_num % tile_pitch) << 9
537 * | (A & 0b111111111)
539 * (In all tiling formulas, cpp is the number of bytes occupied by a single
540 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
541 * to fill the width of the surface, and qpitch is the spacing (in rows)
542 * between array slices).
544 * For Y tiling, tile() combines together the low-order bits of the X and Y
545 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
546 * bytes wide and 32 rows high:
548 * tile(y_tiled, X, Y, S) = A
549 * where A = tile_num << 12 | offset
550 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
551 * offset = (X' & 0b1110000) << 5
552 * | (Y' & 0b11111) << 4
555 * Y' = Y + S * qpitch
556 * detile(y_tiled, A) = (X, Y, S)
560 * Y' = (tile_num / tile_pitch) << 5
561 * | (A & 0b111110000) >> 4
562 * X' = (tile_num % tile_pitch) << 7
563 * | (A & 0b111000000000) >> 5
566 * For W tiling, tile() combines together the low-order bits of the X and Y
567 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
568 * bytes wide and 64 rows high (note that W tiling is only used for stencil
569 * buffers, which always have cpp = 1 and S=0):
571 * tile(w_tiled, X, Y, S) = A
572 * where A = tile_num << 12 | offset
573 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
574 * offset = (X' & 0b111000) << 6
575 * | (Y' & 0b111100) << 3
576 * | (X' & 0b100) << 2
582 * Y' = Y + S * qpitch
583 * detile(w_tiled, A) = (X, Y, S)
584 * where X = X' / cpp = X'
585 * Y = Y' % qpitch = Y'
587 * Y' = (tile_num / tile_pitch) << 6
588 * | (A & 0b111100000) >> 3
589 * | (A & 0b1000) >> 2
591 * X' = (tile_num % tile_pitch) << 6
592 * | (A & 0b111000000000) >> 6
593 * | (A & 0b10000) >> 2
597 * Finally, for a non-tiled surface, tile() simply combines together the X and
598 * Y coordinates in the natural way:
600 * tile(untiled, X, Y, S) = A
601 * where A = Y * pitch + X'
603 * Y' = Y + S * qpitch
604 * detile(untiled, A) = (X, Y, S)
611 * (In these formulas, pitch is the number of bytes occupied by a single row
614 class brw_blorp_blit_program
617 brw_blorp_blit_program(struct brw_context
*brw
,
618 const brw_blorp_blit_prog_key
*key
);
619 ~brw_blorp_blit_program();
621 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
623 brw_blorp_prog_data prog_data
;
627 void alloc_push_const_regs(int base_reg
);
628 void compute_frag_coords();
629 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
630 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
631 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
632 void kill_if_outside_dst_rect();
633 void translate_dst_to_src();
634 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
635 struct brw_reg clampX0
, struct brw_reg clampY0
,
636 struct brw_reg clampX1
, struct brw_reg clampY1
);
637 void single_to_blend();
638 void manual_blend_average(unsigned num_samples
);
639 void manual_blend_bilinear(unsigned num_samples
);
640 void sample(struct brw_reg dst
);
641 void texel_fetch(struct brw_reg dst
);
643 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
644 const sampler_message_arg
*args
, int num_args
);
645 void render_target_write();
648 * Base-2 logarithm of the maximum number of samples that can be blended.
650 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
653 struct brw_context
*brw
;
654 const brw_blorp_blit_prog_key
*key
;
655 struct brw_compile func
;
657 /* Thread dispatch header */
660 /* Pixel X/Y coordinates (always in R1). */
664 struct brw_reg dst_x0
;
665 struct brw_reg dst_x1
;
666 struct brw_reg dst_y0
;
667 struct brw_reg dst_y1
;
668 /* Top right coordinates of the rectangular grid used for scaled blitting */
669 struct brw_reg rect_grid_x1
;
670 struct brw_reg rect_grid_y1
;
672 struct brw_reg multiplier
;
673 struct brw_reg offset
;
674 } x_transform
, y_transform
;
676 /* Data read from texture (4 vec16's per array element) */
677 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
679 /* Auxiliary storage for the contents of the MCS surface.
681 * Since the sampler always returns 8 registers worth of data, this is 8
682 * registers wide, even though we only use the first 2 registers of it.
684 struct brw_reg mcs_data
;
686 /* X coordinates. We have two of them so that we can perform coordinate
687 * transformations easily.
689 struct brw_reg x_coords
[2];
691 /* Y coordinates. We have two of them so that we can perform coordinate
692 * transformations easily.
694 struct brw_reg y_coords
[2];
696 /* X, Y coordinates of the pixel from which we need to fetch the specific
697 * sample. These are used for multisample scaled blitting.
699 struct brw_reg x_sample_coords
;
700 struct brw_reg y_sample_coords
;
702 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
703 struct brw_reg x_frac
;
704 struct brw_reg y_frac
;
706 /* Which element of x_coords and y_coords is currently in use.
710 /* True if, at the point in the program currently being compiled, the
711 * sample index is known to be zero.
715 /* Register storing the sample index when s_is_zero is false. */
716 struct brw_reg sample_index
;
722 /* MRF used for sampling and render target writes */
726 brw_blorp_blit_program::brw_blorp_blit_program(
727 struct brw_context
*brw
,
728 const brw_blorp_blit_prog_key
*key
)
729 : mem_ctx(ralloc_context(NULL
)),
733 brw_init_compile(brw
, &func
, mem_ctx
);
736 brw_blorp_blit_program::~brw_blorp_blit_program()
738 ralloc_free(mem_ctx
);
742 brw_blorp_blit_program::compile(struct brw_context
*brw
,
743 GLuint
*program_size
)
746 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
747 /* If the destination image is W tiled and multisampled, then the thread
748 * must be dispatched once per sample, not once per pixel. This is
749 * necessary because after conversion between W and Y tiling, there's no
750 * guarantee that all samples corresponding to a single pixel will still
753 assert(key
->persample_msaa_dispatch
);
757 /* We are blending, which means we won't have an opportunity to
758 * translate the tiling and sample count for the texture surface. So
759 * the surface state for the texture must be configured with the correct
760 * tiling and sample count.
762 assert(!key
->src_tiled_w
);
763 assert(key
->tex_samples
== key
->src_samples
);
764 assert(key
->tex_layout
== key
->src_layout
);
765 assert(key
->tex_samples
> 0);
768 if (key
->persample_msaa_dispatch
) {
769 /* It only makes sense to do persample dispatch if the render target is
770 * configured as multisampled.
772 assert(key
->rt_samples
> 0);
775 /* Make sure layout is consistent with sample count */
776 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
777 (key
->tex_samples
== 0));
778 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
779 (key
->rt_samples
== 0));
780 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
781 (key
->src_samples
== 0));
782 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
783 (key
->dst_samples
== 0));
785 /* Set up prog_data */
786 memset(&prog_data
, 0, sizeof(prog_data
));
787 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
789 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
792 compute_frag_coords();
794 /* Render target and texture hardware don't support W tiling. */
795 const bool rt_tiled_w
= false;
796 const bool tex_tiled_w
= false;
798 /* The address that data will be written to is determined by the
799 * coordinates supplied to the WM thread and the tiling and sample count of
800 * the render target, according to the formula:
802 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
804 * If the actual tiling and sample count of the destination surface are not
805 * the same as the configuration of the render target, then these
806 * coordinates are wrong and we have to adjust them to compensate for the
809 if (rt_tiled_w
!= key
->dst_tiled_w
||
810 key
->rt_samples
!= key
->dst_samples
||
811 key
->rt_layout
!= key
->dst_layout
) {
812 encode_msaa(key
->rt_samples
, key
->rt_layout
);
813 /* Now (X, Y, S) = detile(rt_tiling, offset) */
814 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
815 /* Now (X, Y, S) = detile(dst_tiling, offset) */
816 decode_msaa(key
->dst_samples
, key
->dst_layout
);
819 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
821 * That is: X, Y and S now contain the true coordinates and sample index of
822 * the data that the WM thread should output.
824 * If we need to kill pixels that are outside the destination rectangle,
825 * now is the time to do it.
829 kill_if_outside_dst_rect();
831 /* Next, apply a translation to obtain coordinates in the source image. */
832 translate_dst_to_src();
834 /* If the source image is not multisampled, then we want to fetch sample
835 * number 0, because that's the only sample there is.
837 if (key
->src_samples
== 0)
840 /* X, Y, and S are now the coordinates of the pixel in the source image
841 * that we want to texture from. Exception: if we are blending, then S is
842 * irrelevant, because we are going to fetch all samples.
844 if (key
->blend
&& !key
->blit_scaled
) {
846 /* Gen6 hardware an automatically blend using the SAMPLE message */
848 sample(texture_data
[0]);
850 /* Gen7+ hardware doesn't automaticaly blend. */
851 manual_blend_average(key
->src_samples
);
853 } else if(key
->blend
&& key
->blit_scaled
) {
854 manual_blend_bilinear(key
->src_samples
);
856 /* We aren't blending, which means we just want to fetch a single sample
857 * from the source surface. The address that we want to fetch from is
858 * related to the X, Y and S values according to the formula:
860 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
862 * If the actual tiling and sample count of the source surface are not
863 * the same as the configuration of the texture, then we need to adjust
864 * the coordinates to compensate for the difference.
866 if (tex_tiled_w
!= key
->src_tiled_w
||
867 key
->tex_samples
!= key
->src_samples
||
868 key
->tex_layout
!= key
->src_layout
) {
869 encode_msaa(key
->src_samples
, key
->src_layout
);
870 /* Now (X, Y, S) = detile(src_tiling, offset) */
871 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
872 /* Now (X, Y, S) = detile(tex_tiling, offset) */
873 decode_msaa(key
->tex_samples
, key
->tex_layout
);
876 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
878 * In other words: X, Y, and S now contain values which, when passed to
879 * the texturing unit, will cause data to be read from the correct
880 * memory location. So we can fetch the texel now.
882 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
884 texel_fetch(texture_data
[0]);
887 /* Finally, write the fetched (or blended) value to the render target and
888 * terminate the thread.
890 render_target_write();
892 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
893 printf("Native code for BLORP blit:\n");
894 brw_dump_compile(&func
, stdout
, 0, func
.next_insn_offset
);
897 return brw_get_program(&func
, program_size
);
901 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
903 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
904 #define ALLOC_REG(name) \
906 brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
907 base_reg + CONST_LOC(name) / 32, \
908 (CONST_LOC(name) % 32) / 4)
914 ALLOC_REG(rect_grid_x1
);
915 ALLOC_REG(rect_grid_y1
);
916 ALLOC_REG(x_transform
.multiplier
);
917 ALLOC_REG(x_transform
.offset
);
918 ALLOC_REG(y_transform
.multiplier
);
919 ALLOC_REG(y_transform
.offset
);
925 brw_blorp_blit_program::alloc_regs()
928 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
929 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
930 prog_data
.first_curbe_grf
= reg
;
931 alloc_push_const_regs(reg
);
932 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
933 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
934 this->texture_data
[i
] =
935 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
939 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
941 for (int i
= 0; i
< 2; ++i
) {
943 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
946 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
950 if (key
->blit_scaled
&& key
->blend
) {
951 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
953 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
955 this->x_frac
= brw_vec8_grf(reg
, 0);
957 this->y_frac
= brw_vec8_grf(reg
, 0);
961 this->xy_coord_index
= 0;
963 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
965 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
967 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
970 /* Make sure we didn't run out of registers */
971 assert(reg
<= GEN7_MRF_HACK_START
);
974 this->base_mrf
= mrf
;
977 /* In the code that follows, X and Y can be used to quickly refer to the
978 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
979 * prime") to the inactive elements.
981 * S can be used to quickly refer to sample_index.
983 #define X x_coords[xy_coord_index]
984 #define Y y_coords[xy_coord_index]
985 #define Xp x_coords[!xy_coord_index]
986 #define Yp y_coords[!xy_coord_index]
987 #define S sample_index
989 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
990 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
992 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
995 * Emit code to compute the X and Y coordinates of the pixels being rendered
996 * by this WM invocation.
998 * Assuming the render target is set up for Y tiling, these (X, Y) values are
999 * related to the address offset where outputs will be written by the formula:
1001 * (X, Y, S) = decode_msaa(detile(offset)).
1003 * (See brw_blorp_blit_program).
1006 brw_blorp_blit_program::compute_frag_coords()
1008 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1009 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1010 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1011 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1013 * Pixels within a subspan are laid out in this arrangement:
1017 * So, to compute the coordinates of each pixel, we need to read every 2nd
1018 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1019 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1020 * In other words, the data we want to access is R1.4<2;4,0>UW.
1022 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1023 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1025 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1026 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1028 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1029 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1030 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1033 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1034 * pixels n+2 and n+3 are in the bottom half of the subspan.
1036 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1037 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1039 /* Move the coordinates to UD registers. */
1040 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1041 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1044 if (key
->persample_msaa_dispatch
) {
1045 switch (key
->rt_samples
) {
1047 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1048 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1049 * represent sample 1, and so on.
1051 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1052 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1053 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1054 * then copy from it using vstride=1, width=4, hstride=0.
1056 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1057 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1058 /* Move to UD sample_index register. */
1059 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1060 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1064 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1065 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1066 * subspan 1 will represent sample 1, and so on. We can find the
1067 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1068 * Index") and multiplying by two (since samples are always delivered
1069 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1072 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1073 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1074 * variable with the sequence (0, 1, 2, 3), and then reading from it
1075 * using vstride=1, width=4, hstride=0.
1077 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1078 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1079 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1080 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1081 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1082 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1083 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1084 stride(t2_uw1
, 1, 4, 0));
1085 brw_ADD(&func
, offset(S
, 1),
1086 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1087 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1091 assert(!"Unrecognized sample count in "
1092 "brw_blorp_blit_program::compute_frag_coords()");
1097 /* Either the destination surface is single-sampled, or the WM will be
1098 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1099 * per pixel). In either case, it's not meaningful to compute a sample
1100 * value. Just set it to 0.
1107 * Emit code to compensate for the difference between Y and W tiling.
1109 * This code modifies the X and Y coordinates according to the formula:
1111 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1113 * (See brw_blorp_blit_program).
1115 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1116 * are booleans where true represents W tiling and false represents Y tiling.
1119 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1121 if (old_tiled_w
== new_tiled_w
)
1124 /* In the code that follows, we can safely assume that S = 0, because W
1125 * tiling formats always use IMS layout.
1129 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1131 /* Given X and Y coordinates that describe an address using Y tiling,
1132 * translate to the X and Y coordinates that describe the same address
1135 * If we break down the low order bits of X and Y, using a
1136 * single letter to represent each low-order bit:
1138 * X = A << 7 | 0bBCDEFGH
1139 * Y = J << 5 | 0bKLMNP (1)
1141 * Then we can apply the Y tiling formula to see the memory offset being
1144 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1146 * If we apply the W detiling formula to this memory location, that the
1147 * corresponding X' and Y' coordinates are:
1149 * X' = A << 6 | 0bBCDPFH (3)
1150 * Y' = J << 6 | 0bKLMNEG
1152 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1153 * we need to make the following computation:
1155 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1156 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1158 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1159 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1160 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1161 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1162 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1163 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1164 brw_OR(&func
, Xp
, t1
, t2
);
1165 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1166 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1167 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1168 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1169 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1170 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1171 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1172 brw_OR(&func
, Yp
, t1
, t2
);
1175 /* Applying the same logic as above, but in reverse, we obtain the
1178 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1179 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1181 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1182 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1183 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1184 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1185 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1186 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1187 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1188 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1190 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1191 brw_OR(&func
, Xp
, t1
, t2
);
1192 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1193 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1194 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1195 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1196 brw_OR(&func
, Yp
, t1
, t2
);
1199 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1203 * Emit code to compensate for the difference between MSAA and non-MSAA
1206 * This code modifies the X and Y coordinates according to the formula:
1208 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1210 * (See brw_blorp_blit_program).
1213 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1214 intel_msaa_layout layout
)
1216 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1218 case INTEL_MSAA_LAYOUT_NONE
:
1219 /* No translation necessary, and S should already be zero. */
1222 case INTEL_MSAA_LAYOUT_CMS
:
1223 /* We can't compensate for compressed layout since at this point in the
1224 * program we haven't read from the MCS buffer.
1226 assert(!"Bad layout in encode_msaa");
1228 case INTEL_MSAA_LAYOUT_UMS
:
1229 /* No translation necessary. */
1231 case INTEL_MSAA_LAYOUT_IMS
:
1232 switch (num_samples
) {
1234 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1235 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1236 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1238 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1240 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1241 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1243 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1245 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1246 brw_OR(&func
, Xp
, t1
, t2
);
1247 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1248 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1250 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1251 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1253 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1254 brw_OR(&func
, Yp
, t1
, t2
);
1257 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1258 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1260 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1262 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1263 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1265 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1266 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1267 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1268 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1269 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1272 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1273 brw_OR(&func
, Xp
, t1
, t2
);
1274 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1275 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1277 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1278 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1280 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1281 brw_OR(&func
, Yp
, t1
, t2
);
1288 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1292 * Emit code to compensate for the difference between MSAA and non-MSAA
1295 * This code modifies the X and Y coordinates according to the formula:
1297 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1299 * (See brw_blorp_blit_program).
1302 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1303 intel_msaa_layout layout
)
1305 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1307 case INTEL_MSAA_LAYOUT_NONE
:
1308 /* No translation necessary, and S should already be zero. */
1311 case INTEL_MSAA_LAYOUT_CMS
:
1312 /* We can't compensate for compressed layout since at this point in the
1313 * program we don't have access to the MCS buffer.
1315 assert(!"Bad layout in encode_msaa");
1317 case INTEL_MSAA_LAYOUT_UMS
:
1318 /* No translation necessary. */
1320 case INTEL_MSAA_LAYOUT_IMS
:
1322 switch (num_samples
) {
1324 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1325 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1326 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1327 * S = (Y & 0b10) | (X & 0b10) >> 1
1329 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1330 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1331 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1332 brw_OR(&func
, Xp
, t1
, t2
);
1333 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1334 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1335 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1336 brw_OR(&func
, Yp
, t1
, t2
);
1337 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1338 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1339 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1340 brw_OR(&func
, S
, t1
, t2
);
1343 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1344 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1345 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1346 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1348 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1349 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1350 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1351 brw_OR(&func
, Xp
, t1
, t2
);
1352 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1353 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1354 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1355 brw_OR(&func
, Yp
, t1
, t2
);
1356 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1357 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1358 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1359 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1360 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1361 brw_OR(&func
, S
, t1
, t2
);
1368 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1372 * Emit code that kills pixels whose X and Y coordinates are outside the
1373 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1377 brw_blorp_blit_program::kill_if_outside_dst_rect()
1379 struct brw_reg f0
= brw_flag_reg(0, 0);
1380 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1381 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1383 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1384 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1385 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1386 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1388 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1389 brw_push_insn_state(&func
);
1390 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1391 brw_AND(&func
, g1
, f0
, g1
);
1392 brw_pop_insn_state(&func
);
1395 #define X_f retype(X, BRW_REGISTER_TYPE_F)
1396 #define Y_f retype(Y, BRW_REGISTER_TYPE_F)
1397 #define Xp_f retype(Xp, BRW_REGISTER_TYPE_F)
1398 #define Yp_f retype(Yp, BRW_REGISTER_TYPE_F)
1400 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1404 brw_blorp_blit_program::translate_dst_to_src()
1406 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1407 /* Move the UD coordinates to float registers. */
1408 brw_MOV(&func
, Xp_f
, X
);
1409 brw_MOV(&func
, Yp_f
, Y
);
1410 /* Scale and offset */
1411 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1412 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1413 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1414 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1415 if (key
->blit_scaled
&& key
->blend
) {
1416 /* Translate coordinates to lay out the samples in a rectangular grid
1417 * roughly corresponding to sample locations.
1419 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1420 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1421 /* Adjust coordinates so that integers represent pixel centers rather
1424 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1425 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1427 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1428 * texels on texture edges.
1430 clamp_tex_coords(X_f
, Y_f
,
1431 brw_imm_f(0.0), brw_imm_f(0.0),
1432 rect_grid_x1
, rect_grid_y1
);
1434 /* Store the fractional parts to be used as bilinear interpolation
1437 brw_FRC(&func
, x_frac
, X_f
);
1438 brw_FRC(&func
, y_frac
, Y_f
);
1440 /* Round the float coordinates down to nearest integer */
1441 brw_RNDD(&func
, Xp_f
, X_f
);
1442 brw_RNDD(&func
, Yp_f
, Y_f
);
1443 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1444 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1446 /* Round the float coordinates down to nearest integer by moving to
1449 brw_MOV(&func
, Xp
, X_f
);
1450 brw_MOV(&func
, Yp
, Y_f
);
1453 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1457 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1458 struct brw_reg regY
,
1459 struct brw_reg clampX0
,
1460 struct brw_reg clampY0
,
1461 struct brw_reg clampX1
,
1462 struct brw_reg clampY1
)
1464 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regX
, clampX0
);
1465 brw_MOV(&func
, regX
, clampX0
);
1466 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1468 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regX
, clampX1
);
1469 brw_MOV(&func
, regX
, clampX1
);
1470 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1472 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regY
, clampY0
);
1473 brw_MOV(&func
, regY
, clampY0
);
1474 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1476 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regY
, clampY1
);
1477 brw_MOV(&func
, regY
, clampY1
);
1478 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1486 * Emit code to transform the X and Y coordinates as needed for blending
1487 * together the different samples in an MSAA texture.
1490 brw_blorp_blit_program::single_to_blend()
1492 /* When looking up samples in an MSAA texture using the SAMPLE message,
1493 * Gen6 requires the texture coordinates to be odd integers (so that they
1494 * correspond to the center of a 2x2 block representing the four samples
1495 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1496 * each by 2 and then add 1.
1498 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1499 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1500 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1501 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1502 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1503 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1509 * Count the number of trailing 1 bits in the given value. For example:
1511 * count_trailing_one_bits(0) == 0
1512 * count_trailing_one_bits(7) == 3
1513 * count_trailing_one_bits(11) == 2
1515 inline int count_trailing_one_bits(unsigned value
)
1517 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1518 return __builtin_ctz(~value
);
1520 return _mesa_bitcount(value
& ~(value
+ 1));
1526 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1528 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1531 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1533 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1535 * This ensures that when all samples have the same value, no numerical
1536 * precision is lost, since each addition operation always adds two equal
1537 * values, and summing two equal floating point values does not lose
1540 * We perform this computation by treating the texture_data array as a
1541 * stack and performing the following operations:
1543 * - push sample 0 onto stack
1544 * - push sample 1 onto stack
1545 * - add top two stack entries
1546 * - push sample 2 onto stack
1547 * - push sample 3 onto stack
1548 * - add top two stack entries
1549 * - add top two stack entries
1550 * - divide top stack entry by 4
1552 * Note that after pushing sample i onto the stack, the number of add
1553 * operations we do is equal to the number of trailing 1 bits in i. This
1554 * works provided the total number of samples is a power of two, which it
1555 * always is for i965.
1557 * For integer formats, we replace the add operations with average
1558 * operations and skip the final division.
1560 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1564 brw_op2_ptr combine_op
=
1565 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1566 unsigned stack_depth
= 0;
1567 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1568 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1570 /* Push sample i onto the stack */
1571 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1576 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1578 texel_fetch(texture_data
[stack_depth
++]);
1580 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1581 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1582 * suggests an optimization:
1584 * "A simple optimization with probable large return in
1585 * performance is to compare the MCS value to zero (indicating
1586 * all samples are on sample slice 0), and sample only from
1587 * sample slice 0 using ld2dss if MCS is zero."
1589 * Note that in the case where the MCS value is zero, sampling from
1590 * sample slice 0 using ld2dss and sampling from sample 0 using
1591 * ld2dms are equivalent (since all samples are on sample slice 0).
1592 * Since we have already sampled from sample 0, all we need to do is
1593 * skip the remaining fetches and averaging if MCS is zero.
1595 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1596 mcs_data
, brw_imm_ud(0));
1597 brw_IF(&func
, BRW_EXECUTE_16
);
1600 /* Do count_trailing_one_bits(i) times */
1601 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1602 assert(stack_depth
>= 2);
1605 /* TODO: should use a smaller loop bound for non_RGBA formats */
1606 for (int k
= 0; k
< 4; ++k
) {
1607 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1608 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1609 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1614 /* We should have just 1 sample on the stack now. */
1615 assert(stack_depth
== 1);
1617 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1618 /* Scale the result down by a factor of num_samples */
1619 /* TODO: should use a smaller loop bound for non-RGBA formats */
1620 for (int j
= 0; j
< 4; ++j
) {
1621 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1622 offset(vec8(texture_data
[0]), 2*j
),
1623 brw_imm_f(1.0/num_samples
));
1627 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1632 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1634 /* We do this computation by performing the following operations:
1636 * In case of 4x, 8x MSAA:
1637 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1638 * which are later used for interpolation
1639 * - linearly interpolate samples a and b in X
1640 * - linearly interpolate samples c and d in X
1641 * - linearly interpolate the results of last two operations in Y
1643 * result = lrp(lrp(a + b) + lrp(c + d))
1645 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1646 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1647 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1648 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1650 for (unsigned i
= 0; i
< 4; ++i
) {
1651 assert(i
< ARRAY_SIZE(texture_data
));
1654 /* Compute pixel coordinates */
1655 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1656 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1657 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1658 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1659 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1660 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1662 /* The MCS value we fetch has to match up with the pixel that we're
1663 * sampling from. Since we sample from different pixels in each
1664 * iteration of this "for" loop, the call to mcs_fetch() should be
1665 * here inside the loop after computing the pixel coordinates.
1667 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1670 /* Compute sample index and map the sample index to a sample number.
1671 * Sample index layout shows the numbering of slots in a rectangular
1672 * grid of samples with in a pixel. Sample number layout shows the
1673 * rectangular grid of samples roughly corresponding to the real sample
1674 * locations with in a pixel.
1675 * In case of 4x MSAA, layout of sample indices matches the layout of
1683 * In case of 8x MSAA the two layouts don't match.
1684 * sample index layout : --------- sample number layout : ---------
1685 * | 0 | 1 | | 5 | 2 |
1686 * --------- ---------
1687 * | 2 | 3 | | 4 | 6 |
1688 * --------- ---------
1689 * | 4 | 5 | | 0 | 3 |
1690 * --------- ---------
1691 * | 6 | 7 | | 7 | 1 |
1692 * --------- ---------
1694 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1695 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1696 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1697 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1698 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1699 brw_MOV(&func
, vec16(S
), t1_f
);
1701 if (num_samples
== 8) {
1702 /* Map the sample index to a sample number */
1703 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1705 brw_IF(&func
, BRW_EXECUTE_16
);
1707 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1708 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1710 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1711 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1712 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1714 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1715 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1716 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1718 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1719 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1723 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1724 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1726 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1727 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1728 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1730 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1731 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1732 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1734 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1735 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1738 brw_MOV(&func
, vec16(S
), t2
);
1740 texel_fetch(texture_data
[i
]);
1743 #define SAMPLE(x, y) offset(texture_data[x], y)
1744 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1745 for (int index
= 3; index
> 0; ) {
1746 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1747 * Counter value of 8 in 'for' loop below is used to interpolate all
1748 * the color components.
1750 for (int k
= 0; k
< 8; ++k
)
1752 vec8(SAMPLE(index
- 1, k
)),
1753 offset(x_frac
, k
& 1),
1755 SAMPLE(index
- 1, k
));
1758 for (int k
= 0; k
< 8; ++k
)
1761 offset(y_frac
, k
& 1),
1763 vec8(SAMPLE(0, k
)));
1764 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1769 * Emit code to look up a value in the texture using the SAMPLE message (which
1770 * does blending of MSAA surfaces).
1773 brw_blorp_blit_program::sample(struct brw_reg dst
)
1775 static const sampler_message_arg args
[2] = {
1776 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1777 SAMPLER_MESSAGE_ARG_V_FLOAT
1780 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
,
1785 * Emit code to look up a value in the texture using the SAMPLE_LD message
1786 * (which does a simple texel fetch).
1789 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1791 static const sampler_message_arg gen6_args
[5] = {
1792 SAMPLER_MESSAGE_ARG_U_INT
,
1793 SAMPLER_MESSAGE_ARG_V_INT
,
1794 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1795 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1796 SAMPLER_MESSAGE_ARG_SI_INT
1798 static const sampler_message_arg gen7_ld_args
[3] = {
1799 SAMPLER_MESSAGE_ARG_U_INT
,
1800 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1801 SAMPLER_MESSAGE_ARG_V_INT
1803 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1804 SAMPLER_MESSAGE_ARG_SI_INT
,
1805 SAMPLER_MESSAGE_ARG_U_INT
,
1806 SAMPLER_MESSAGE_ARG_V_INT
1808 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1809 SAMPLER_MESSAGE_ARG_SI_INT
,
1810 SAMPLER_MESSAGE_ARG_MCS_INT
,
1811 SAMPLER_MESSAGE_ARG_U_INT
,
1812 SAMPLER_MESSAGE_ARG_V_INT
1817 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1821 switch (key
->tex_layout
) {
1822 case INTEL_MSAA_LAYOUT_IMS
:
1823 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1826 * If this field is MSFMT_DEPTH_STENCIL
1827 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1828 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1830 * So fall through to emit the same message as we use for
1831 * INTEL_MSAA_LAYOUT_CMS.
1833 case INTEL_MSAA_LAYOUT_CMS
:
1834 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1835 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1837 case INTEL_MSAA_LAYOUT_UMS
:
1838 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1839 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1841 case INTEL_MSAA_LAYOUT_NONE
:
1843 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1844 ARRAY_SIZE(gen7_ld_args
));
1849 assert(!"Should not get here.");
1855 brw_blorp_blit_program::mcs_fetch()
1857 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1858 SAMPLER_MESSAGE_ARG_U_INT
,
1859 SAMPLER_MESSAGE_ARG_V_INT
1861 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1862 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1866 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1868 const sampler_message_arg
*args
,
1871 struct brw_reg mrf
=
1872 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1873 for (int arg
= 0; arg
< num_args
; ++arg
) {
1874 switch (args
[arg
]) {
1875 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1876 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1878 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1879 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1881 case SAMPLER_MESSAGE_ARG_U_INT
:
1882 brw_MOV(&func
, mrf
, X
);
1884 case SAMPLER_MESSAGE_ARG_V_INT
:
1885 brw_MOV(&func
, mrf
, Y
);
1887 case SAMPLER_MESSAGE_ARG_SI_INT
:
1888 /* Note: on Gen7, this code may be reached with s_is_zero==true
1889 * because in Gen7's ld2dss message, the sample index is the first
1890 * argument. When this happens, we need to move a 0 into the
1891 * appropriate message register.
1894 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1896 brw_MOV(&func
, mrf
, S
);
1898 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1899 switch (key
->tex_layout
) {
1900 case INTEL_MSAA_LAYOUT_CMS
:
1901 brw_MOV(&func
, mrf
, mcs_data
);
1903 case INTEL_MSAA_LAYOUT_IMS
:
1904 /* When sampling from an IMS surface, MCS data is not relevant,
1905 * and the hardware ignores it. So don't bother populating it.
1909 /* We shouldn't be trying to send MCS data with any other
1912 assert (!"Unsupported layout for MCS data");
1916 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1917 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1924 retype(dst
, BRW_REGISTER_TYPE_F
) /* dest */,
1925 base_mrf
/* msg_reg_nr */,
1926 brw_message_reg(base_mrf
) /* src0 */,
1927 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1930 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1931 mrf
.nr
- base_mrf
/* msg_length */,
1932 0 /* header_present */,
1933 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1934 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1942 #undef SWAP_XY_AND_XPYP
1945 brw_blorp_blit_program::render_target_write()
1947 struct brw_reg mrf_rt_write
=
1948 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1951 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1952 * so that the render target knows which pixels we killed.
1954 bool use_header
= key
->use_kill
;
1956 /* Copy R0/1 to MRF */
1957 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1958 retype(R0
, BRW_REGISTER_TYPE_UD
));
1962 /* Copy texture data to MRFs */
1963 for (int i
= 0; i
< 4; ++i
) {
1964 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1965 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1966 offset(vec8(texture_data
[0]), 2*i
));
1970 /* Now write to the render target and terminate the thread */
1972 16 /* dispatch_width */,
1973 base_mrf
/* msg_reg_nr */,
1974 mrf_rt_write
/* src0 */,
1975 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1976 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1977 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1978 0 /* response_length */,
1985 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1986 GLfloat dst0
, GLfloat dst1
,
1989 float scale
= (src1
- src0
) / (dst1
- dst0
);
1991 /* When not mirroring a coordinate (say, X), we need:
1992 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1994 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1996 * blorp program uses "round toward zero" to convert the
1997 * transformed floating point coordinates to integer coordinates,
1998 * whereas the behaviour we actually want is "round to nearest",
1999 * so 0.5 provides the necessary correction.
2002 offset
= src0
+ (-dst0
+ 0.5) * scale
;
2004 /* When mirroring X we need:
2005 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2007 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2009 multiplier
= -scale
;
2010 offset
= src0
+ (dst1
- 0.5) * scale
;
2016 * Determine which MSAA layout the GPU pipeline should be configured for,
2017 * based on the chip generation, the number of samples, and the true layout of
2018 * the image in memory.
2020 inline intel_msaa_layout
2021 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2022 intel_msaa_layout true_layout
)
2024 if (num_samples
<= 1) {
2025 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2026 * format buffers, by transforming coordinates appropriately.
2028 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2029 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2030 return INTEL_MSAA_LAYOUT_NONE
;
2032 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2035 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2036 if (brw
->gen
== 6) {
2037 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2044 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2045 struct intel_mipmap_tree
*src_mt
,
2046 unsigned src_level
, unsigned src_layer
,
2047 struct intel_mipmap_tree
*dst_mt
,
2048 unsigned dst_level
, unsigned dst_layer
,
2049 GLfloat src_x0
, GLfloat src_y0
,
2050 GLfloat src_x1
, GLfloat src_y1
,
2051 GLfloat dst_x0
, GLfloat dst_y0
,
2052 GLfloat dst_x1
, GLfloat dst_y1
,
2053 bool mirror_x
, bool mirror_y
)
2055 struct gl_context
*ctx
= &brw
->ctx
;
2056 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2058 src
.set(brw
, src_mt
, src_level
, src_layer
);
2059 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
);
2061 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2064 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2066 /* texture_data_type indicates the register type that should be used to
2067 * manipulate texture data.
2069 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2070 case GL_UNSIGNED_NORMALIZED
:
2071 case GL_SIGNED_NORMALIZED
:
2073 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2075 case GL_UNSIGNED_INT
:
2076 if (src_mt
->format
== MESA_FORMAT_S8
) {
2077 /* We process stencil as though it's an unsigned normalized color */
2078 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2080 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2084 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2087 assert(!"Unrecognized blorp format");
2092 /* Gen7's rendering hardware only supports the IMS layout for depth and
2093 * stencil render targets. Blorp always maps its destination surface as
2094 * a color render target (even if it's actually a depth or stencil
2095 * buffer). So if the destination is IMS, we'll have to map it as a
2096 * single-sampled texture and interleave the samples ourselves.
2098 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2099 dst
.num_samples
= 0;
2102 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2103 /* If the destination surface is a W-tiled multisampled stencil buffer
2104 * that we're mapping as Y tiled, then we need to arrange for the WM
2105 * program to run once per sample rather than once per pixel, because
2106 * the memory layout of related samples doesn't match between W and Y
2109 wm_prog_key
.persample_msaa_dispatch
= true;
2112 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2113 /* We are blitting from a multisample buffer to a multisample buffer, so
2114 * we must preserve samples within a pixel. This means we have to
2115 * arrange for the WM program to run once per sample rather than once
2118 wm_prog_key
.persample_msaa_dispatch
= true;
2121 /* Scaled blitting or not. */
2122 wm_prog_key
.blit_scaled
=
2123 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2124 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2126 /* Scaling factors used for bilinear filtering in multisample scaled
2129 wm_prog_key
.x_scale
= 2.0;
2130 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2132 /* The render path must be configured to use the same number of samples as
2133 * the destination buffer.
2135 num_samples
= dst
.num_samples
;
2137 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2138 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2139 base_format
!= GL_STENCIL_INDEX
&&
2140 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2141 /* We are downsampling a color buffer, so blend. */
2142 wm_prog_key
.blend
= true;
2145 /* src_samples and dst_samples are the true sample counts */
2146 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2147 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2149 /* tex_samples and rt_samples are the sample counts that are set up in
2152 wm_prog_key
.tex_samples
= src
.num_samples
;
2153 wm_prog_key
.rt_samples
= dst
.num_samples
;
2155 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2156 * use to access the source and destination surfaces.
2158 wm_prog_key
.tex_layout
=
2159 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2160 wm_prog_key
.rt_layout
=
2161 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2163 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2166 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2167 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2169 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2170 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2171 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2172 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2173 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2174 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2175 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2176 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2178 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2179 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2181 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2182 /* We must expand the rectangle we send through the rendering pipeline,
2183 * to account for the fact that we are mapping the destination region as
2184 * single-sampled when it is in fact multisampled. We must also align
2185 * it to a multiple of the multisampling pattern, because the
2186 * differences between multisampled and single-sampled surface formats
2187 * will mean that pixels are scrambled within the multisampling pattern.
2188 * TODO: what if this makes the coordinates too large?
2190 * Note: this only works if the destination surface uses the IMS layout.
2191 * If it's UMS, then we have no choice but to set up the rendering
2192 * pipeline as multisampled.
2194 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2195 switch (dst_mt
->num_samples
) {
2197 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2198 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2199 x1
= ALIGN(x1
* 2, 4);
2200 y1
= ALIGN(y1
* 2, 4);
2203 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2204 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2205 x1
= ALIGN(x1
* 4, 8);
2206 y1
= ALIGN(y1
* 2, 4);
2209 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2212 wm_prog_key
.use_kill
= true;
2215 if (dst
.map_stencil_as_y_tiled
) {
2216 /* We must modify the rectangle we send through the rendering pipeline
2217 * (and the size and x/y offset of the destination surface), to account
2218 * for the fact that we are mapping it as Y-tiled when it is in fact
2221 * Both Y tiling and W tiling can be understood as organizations of
2222 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2223 * is different, but the layout of the 32-byte sub-tiles within the 4k
2224 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2225 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2226 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2228 * Therefore, to account for the layout differences within the 32-byte
2229 * sub-tiles, we must expand the rectangle so the X coordinates of its
2230 * edges are multiples of 8 (the W sub-tile width), and its Y
2231 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2232 * Then we need to scale the X and Y coordinates of the rectangle to
2233 * account for the differences in aspect ratio between the Y and W
2234 * sub-tiles. We need to modify the layer width and height similarly.
2236 * A correction needs to be applied when MSAA is in use: since
2237 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2238 * we need to align the Y coordinates to multiples of 8, so that when
2239 * they are divided by two they are still multiples of 4.
2241 * Note: Since the x/y offset of the surface will be applied using the
2242 * SURFACE_STATE command packet, it will be invisible to the swizzling
2243 * code in the shader; therefore it needs to be in a multiple of the
2244 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2245 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2246 * buffer), and the miplevel alignment used for stencil buffers is 8
2247 * pixels horizontally and either 4 or 8 pixels vertically (see
2248 * intel_horizontal_texture_alignment_unit() and
2249 * intel_vertical_texture_alignment_unit()).
2251 * Note: Also, since the SURFACE_STATE command packet can only apply
2252 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2253 * vertically, it is important that the offsets will be multiples of
2254 * these sizes after they are converted into Y-tiled coordinates.
2255 * Fortunately they will be, since we know from above that the offsets
2256 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2257 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2259 * TODO: what if this makes the coordinates (or the texture size) too
2262 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2263 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2264 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2265 x1
= ALIGN(x1
, x_align
) * 2;
2266 y1
= ALIGN(y1
, y_align
) / 2;
2267 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2268 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2271 wm_prog_key
.use_kill
= true;
2274 if (src
.map_stencil_as_y_tiled
) {
2275 /* We must modify the size and x/y offset of the source surface to
2276 * account for the fact that we are mapping it as Y-tiled when it is in
2279 * See the comments above concerning x/y offset alignment for the
2280 * destination surface.
2282 * TODO: what if this makes the texture size too large?
2284 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2285 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2286 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2293 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2294 brw_blorp_prog_data
**prog_data
) const
2296 uint32_t prog_offset
= 0;
2297 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2298 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2299 &prog_offset
, prog_data
)) {
2300 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2301 GLuint program_size
;
2302 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2303 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2304 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2305 program
, program_size
,
2306 &prog
.prog_data
, sizeof(prog
.prog_data
),
2307 &prog_offset
, prog_data
);