2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
49 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
50 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
51 * the physical layer holding sample 0. So, for example, if
52 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
56 brw_blorp_blit_miptrees(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*src_mt
,
58 unsigned src_level
, unsigned src_layer
,
59 struct intel_mipmap_tree
*dst_mt
,
60 unsigned dst_level
, unsigned dst_layer
,
61 float src_x0
, float src_y0
,
62 float src_x1
, float src_y1
,
63 float dst_x0
, float dst_y0
,
64 float dst_x1
, float dst_y1
,
65 GLenum filter
, bool mirror_x
, bool mirror_y
)
67 /* Get ready to blit. This includes depth resolving the src and dst
68 * buffers if necessary. Note: it's not necessary to do a color resolve on
69 * the destination buffer because we use the standard render path to render
70 * to destination color buffers, and the standard render path is
73 intel_miptree_resolve_color(brw
, src_mt
);
74 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
75 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
77 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
78 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
80 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
81 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
82 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
83 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
86 brw_blorp_blit_params
params(brw
,
87 src_mt
, src_level
, src_layer
,
88 dst_mt
, dst_level
, dst_layer
,
93 filter
, mirror_x
, mirror_y
);
94 brw_blorp_exec(brw
, ¶ms
);
96 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
100 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
101 struct intel_renderbuffer
*src_irb
,
102 struct intel_renderbuffer
*dst_irb
,
103 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
104 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
105 GLenum filter
, bool mirror_x
, bool mirror_y
)
107 /* Find source/dst miptrees */
108 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
109 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
112 brw_blorp_blit_miptrees(brw
,
113 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
114 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
115 srcX0
, srcY0
, srcX1
, srcY1
,
116 dstX0
, dstY0
, dstX1
, dstY1
,
117 filter
, mirror_x
, mirror_y
);
119 dst_irb
->need_downsample
= true;
123 try_blorp_blit(struct brw_context
*brw
,
124 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
125 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
126 GLenum filter
, GLbitfield buffer_bit
)
128 struct gl_context
*ctx
= &brw
->ctx
;
130 /* Sync up the state of window system buffers. We need to do this before
131 * we go looking for the buffers.
133 intel_prepare_render(brw
);
135 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
136 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
138 bool mirror_x
, mirror_y
;
139 if (brw_meta_mirror_clip_and_scissor(ctx
,
140 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
141 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
142 &mirror_x
, &mirror_y
))
146 struct intel_renderbuffer
*src_irb
;
147 struct intel_renderbuffer
*dst_irb
;
148 struct intel_mipmap_tree
*src_mt
;
149 struct intel_mipmap_tree
*dst_mt
;
150 switch (buffer_bit
) {
151 case GL_COLOR_BUFFER_BIT
:
152 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
153 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
154 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
156 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
157 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
158 filter
, mirror_x
, mirror_y
);
161 case GL_DEPTH_BUFFER_BIT
:
163 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
165 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
166 src_mt
= find_miptree(buffer_bit
, src_irb
);
167 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
169 /* We can't handle format conversions between Z24 and other formats
170 * since we have to lie about the surface format. See the comments in
171 * brw_blorp_surface_info::set().
173 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
174 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
177 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
178 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
179 filter
, mirror_x
, mirror_y
);
181 case GL_STENCIL_BUFFER_BIT
:
183 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
185 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
186 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
187 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
188 filter
, mirror_x
, mirror_y
);
191 unreachable("not reached");
198 brw_blorp_copytexsubimage(struct brw_context
*brw
,
199 struct gl_renderbuffer
*src_rb
,
200 struct gl_texture_image
*dst_image
,
202 int srcX0
, int srcY0
,
203 int dstX0
, int dstY0
,
204 int width
, int height
)
206 struct gl_context
*ctx
= &brw
->ctx
;
207 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
208 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
210 /* Sync up the state of window system buffers. We need to do this before
211 * we go looking at the src renderbuffer's miptree.
213 intel_prepare_render(brw
);
215 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
216 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
218 /* BLORP is not supported before Gen6. */
219 if (brw
->gen
< 6 || brw
->gen
>= 8)
222 if (_mesa_get_format_base_format(src_mt
->format
) !=
223 _mesa_get_format_base_format(dst_mt
->format
)) {
227 /* We can't handle format conversions between Z24 and other formats since
228 * we have to lie about the surface format. See the comments in
229 * brw_blorp_surface_info::set().
231 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
232 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
236 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
239 /* Source clipping shouldn't be necessary, since copytexsubimage (in
240 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
243 * Destination clipping shouldn't be necessary since the restrictions on
244 * glCopyTexSubImage prevent the user from specifying a destination rectangle
245 * that falls outside the bounds of the destination texture.
246 * See error_check_subtexture_dimensions().
249 int srcY1
= srcY0
+ height
;
250 int srcX1
= srcX0
+ width
;
251 int dstX1
= dstX0
+ width
;
252 int dstY1
= dstY0
+ height
;
254 /* Account for the fact that in the system framebuffer, the origin is at
257 bool mirror_y
= false;
258 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
259 GLint tmp
= src_rb
->Height
- srcY0
;
260 srcY0
= src_rb
->Height
- srcY1
;
265 /* Account for face selection and texture view MinLayer */
266 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
267 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
269 brw_blorp_blit_miptrees(brw
,
270 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
271 dst_mt
, dst_level
, dst_slice
,
272 srcX0
, srcY0
, srcX1
, srcY1
,
273 dstX0
, dstY0
, dstX1
, dstY1
,
274 GL_NEAREST
, false, mirror_y
);
276 /* If we're copying to a packed depth stencil texture and the source
277 * framebuffer has separate stencil, we need to also copy the stencil data
280 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
281 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
283 src_irb
= intel_renderbuffer(src_rb
);
284 src_mt
= src_irb
->mt
;
286 if (src_mt
->stencil_mt
)
287 src_mt
= src_mt
->stencil_mt
;
288 if (dst_mt
->stencil_mt
)
289 dst_mt
= dst_mt
->stencil_mt
;
291 if (src_mt
!= dst_mt
) {
292 brw_blorp_blit_miptrees(brw
,
293 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
294 dst_mt
, dst_level
, dst_slice
,
295 srcX0
, srcY0
, srcX1
, srcY1
,
296 dstX0
, dstY0
, dstX1
, dstY1
,
297 GL_NEAREST
, false, mirror_y
);
306 brw_blorp_framebuffer(struct brw_context
*brw
,
307 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
308 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
309 GLbitfield mask
, GLenum filter
)
311 /* BLORP is not supported before Gen6. */
312 if (brw
->gen
< 6 || brw
->gen
>= 8)
315 static GLbitfield buffer_bits
[] = {
318 GL_STENCIL_BUFFER_BIT
,
321 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
322 if ((mask
& buffer_bits
[i
]) &&
324 srcX0
, srcY0
, srcX1
, srcY1
,
325 dstX0
, dstY0
, dstX1
, dstY1
,
326 filter
, buffer_bits
[i
])) {
327 mask
&= ~buffer_bits
[i
];
336 * Enum to specify the order of arguments in a sampler message
338 enum sampler_message_arg
340 SAMPLER_MESSAGE_ARG_U_FLOAT
,
341 SAMPLER_MESSAGE_ARG_V_FLOAT
,
342 SAMPLER_MESSAGE_ARG_U_INT
,
343 SAMPLER_MESSAGE_ARG_V_INT
,
344 SAMPLER_MESSAGE_ARG_SI_INT
,
345 SAMPLER_MESSAGE_ARG_MCS_INT
,
346 SAMPLER_MESSAGE_ARG_ZERO_INT
,
350 * Generator for WM programs used in BLORP blits.
352 * The bulk of the work done by the WM program is to wrap and unwrap the
353 * coordinate transformations used by the hardware to store surfaces in
354 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
355 * sample index for a multisampled surface) to a memory offset by the
356 * following formulas:
358 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
359 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
361 * For a single-sampled surface, or for a multisampled surface using
362 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
365 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
366 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
367 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
368 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
370 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
371 * embeds the sample number into bit 1 of the X and Y coordinates:
373 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
374 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
375 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
376 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
377 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
378 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
379 * S = (Y & 0b10) | (X & 0b10) >> 1
381 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
382 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
385 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
386 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
387 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
388 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
389 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
390 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
391 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
393 * For X tiling, tile() combines together the low-order bits of the X and Y
394 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
395 * bytes wide and 8 rows high:
397 * tile(x_tiled, X, Y, S) = A
398 * where A = tile_num << 12 | offset
399 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
400 * offset = (Y' & 0b111) << 9
401 * | (X & 0b111111111)
403 * Y' = Y + S * qpitch
404 * detile(x_tiled, A) = (X, Y, S)
408 * Y' = (tile_num / tile_pitch) << 3
409 * | (A & 0b111000000000) >> 9
410 * X' = (tile_num % tile_pitch) << 9
411 * | (A & 0b111111111)
413 * (In all tiling formulas, cpp is the number of bytes occupied by a single
414 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
415 * to fill the width of the surface, and qpitch is the spacing (in rows)
416 * between array slices).
418 * For Y tiling, tile() combines together the low-order bits of the X and Y
419 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
420 * bytes wide and 32 rows high:
422 * tile(y_tiled, X, Y, S) = A
423 * where A = tile_num << 12 | offset
424 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
425 * offset = (X' & 0b1110000) << 5
426 * | (Y' & 0b11111) << 4
429 * Y' = Y + S * qpitch
430 * detile(y_tiled, A) = (X, Y, S)
434 * Y' = (tile_num / tile_pitch) << 5
435 * | (A & 0b111110000) >> 4
436 * X' = (tile_num % tile_pitch) << 7
437 * | (A & 0b111000000000) >> 5
440 * For W tiling, tile() combines together the low-order bits of the X and Y
441 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
442 * bytes wide and 64 rows high (note that W tiling is only used for stencil
443 * buffers, which always have cpp = 1 and S=0):
445 * tile(w_tiled, X, Y, S) = A
446 * where A = tile_num << 12 | offset
447 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
448 * offset = (X' & 0b111000) << 6
449 * | (Y' & 0b111100) << 3
450 * | (X' & 0b100) << 2
456 * Y' = Y + S * qpitch
457 * detile(w_tiled, A) = (X, Y, S)
458 * where X = X' / cpp = X'
459 * Y = Y' % qpitch = Y'
461 * Y' = (tile_num / tile_pitch) << 6
462 * | (A & 0b111100000) >> 3
463 * | (A & 0b1000) >> 2
465 * X' = (tile_num % tile_pitch) << 6
466 * | (A & 0b111000000000) >> 6
467 * | (A & 0b10000) >> 2
471 * Finally, for a non-tiled surface, tile() simply combines together the X and
472 * Y coordinates in the natural way:
474 * tile(untiled, X, Y, S) = A
475 * where A = Y * pitch + X'
477 * Y' = Y + S * qpitch
478 * detile(untiled, A) = (X, Y, S)
485 * (In these formulas, pitch is the number of bytes occupied by a single row
488 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
491 brw_blorp_blit_program(struct brw_context
*brw
,
492 const brw_blorp_blit_prog_key
*key
, bool debug_flag
);
494 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
496 brw_blorp_prog_data prog_data
;
500 void alloc_push_const_regs(int base_reg
);
501 void compute_frag_coords();
502 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
503 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
504 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
505 void translate_dst_to_src();
506 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
507 struct brw_reg clampX0
, struct brw_reg clampY0
,
508 struct brw_reg clampX1
, struct brw_reg clampY1
);
509 void single_to_blend();
510 void manual_blend_average(unsigned num_samples
);
511 void manual_blend_bilinear(unsigned num_samples
);
512 void sample(struct brw_reg dst
);
513 void texel_fetch(struct brw_reg dst
);
515 void texture_lookup(struct brw_reg dst
, enum opcode op
,
516 const sampler_message_arg
*args
, int num_args
);
517 void render_target_write();
520 * Base-2 logarithm of the maximum number of samples that can be blended.
522 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
524 struct brw_context
*brw
;
525 const brw_blorp_blit_prog_key
*key
;
527 /* Thread dispatch header */
530 /* Pixel X/Y coordinates (always in R1). */
534 struct brw_reg dst_x0
;
535 struct brw_reg dst_x1
;
536 struct brw_reg dst_y0
;
537 struct brw_reg dst_y1
;
538 /* Top right coordinates of the rectangular grid used for scaled blitting */
539 struct brw_reg rect_grid_x1
;
540 struct brw_reg rect_grid_y1
;
542 struct brw_reg multiplier
;
543 struct brw_reg offset
;
544 } x_transform
, y_transform
;
546 /* Data read from texture (4 vec16's per array element) */
547 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
549 /* Auxiliary storage for the contents of the MCS surface.
551 * Since the sampler always returns 8 registers worth of data, this is 8
552 * registers wide, even though we only use the first 2 registers of it.
554 struct brw_reg mcs_data
;
556 /* X coordinates. We have two of them so that we can perform coordinate
557 * transformations easily.
559 struct brw_reg x_coords
[2];
561 /* Y coordinates. We have two of them so that we can perform coordinate
562 * transformations easily.
564 struct brw_reg y_coords
[2];
566 /* X, Y coordinates of the pixel from which we need to fetch the specific
567 * sample. These are used for multisample scaled blitting.
569 struct brw_reg x_sample_coords
;
570 struct brw_reg y_sample_coords
;
572 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
573 struct brw_reg x_frac
;
574 struct brw_reg y_frac
;
576 /* Which element of x_coords and y_coords is currently in use.
580 /* True if, at the point in the program currently being compiled, the
581 * sample index is known to be zero.
585 /* Register storing the sample index when s_is_zero is false. */
586 struct brw_reg sample_index
;
592 /* MRF used for sampling and render target writes */
596 brw_blorp_blit_program::brw_blorp_blit_program(
597 struct brw_context
*brw
,
598 const brw_blorp_blit_prog_key
*key
,
600 : brw_blorp_eu_emitter(brw
, debug_flag
),
607 brw_blorp_blit_program::compile(struct brw_context
*brw
,
608 GLuint
*program_size
)
611 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
612 /* If the destination image is W tiled and multisampled, then the thread
613 * must be dispatched once per sample, not once per pixel. This is
614 * necessary because after conversion between W and Y tiling, there's no
615 * guarantee that all samples corresponding to a single pixel will still
618 assert(key
->persample_msaa_dispatch
);
622 /* We are blending, which means we won't have an opportunity to
623 * translate the tiling and sample count for the texture surface. So
624 * the surface state for the texture must be configured with the correct
625 * tiling and sample count.
627 assert(!key
->src_tiled_w
);
628 assert(key
->tex_samples
== key
->src_samples
);
629 assert(key
->tex_layout
== key
->src_layout
);
630 assert(key
->tex_samples
> 0);
633 if (key
->persample_msaa_dispatch
) {
634 /* It only makes sense to do persample dispatch if the render target is
635 * configured as multisampled.
637 assert(key
->rt_samples
> 0);
640 /* Make sure layout is consistent with sample count */
641 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
642 (key
->tex_samples
== 0));
643 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
644 (key
->rt_samples
== 0));
645 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
646 (key
->src_samples
== 0));
647 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
648 (key
->dst_samples
== 0));
650 /* Set up prog_data */
651 memset(&prog_data
, 0, sizeof(prog_data
));
652 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
655 compute_frag_coords();
657 /* Render target and texture hardware don't support W tiling. */
658 const bool rt_tiled_w
= false;
659 const bool tex_tiled_w
= false;
661 /* The address that data will be written to is determined by the
662 * coordinates supplied to the WM thread and the tiling and sample count of
663 * the render target, according to the formula:
665 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
667 * If the actual tiling and sample count of the destination surface are not
668 * the same as the configuration of the render target, then these
669 * coordinates are wrong and we have to adjust them to compensate for the
672 if (rt_tiled_w
!= key
->dst_tiled_w
||
673 key
->rt_samples
!= key
->dst_samples
||
674 key
->rt_layout
!= key
->dst_layout
) {
675 encode_msaa(key
->rt_samples
, key
->rt_layout
);
676 /* Now (X, Y, S) = detile(rt_tiling, offset) */
677 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
678 /* Now (X, Y, S) = detile(dst_tiling, offset) */
679 decode_msaa(key
->dst_samples
, key
->dst_layout
);
682 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
684 * That is: X, Y and S now contain the true coordinates and sample index of
685 * the data that the WM thread should output.
687 * If we need to kill pixels that are outside the destination rectangle,
688 * now is the time to do it.
692 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
693 y_coords
[xy_coord_index
],
694 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
696 /* Next, apply a translation to obtain coordinates in the source image. */
697 translate_dst_to_src();
699 /* If the source image is not multisampled, then we want to fetch sample
700 * number 0, because that's the only sample there is.
702 if (key
->src_samples
== 0)
705 /* X, Y, and S are now the coordinates of the pixel in the source image
706 * that we want to texture from. Exception: if we are blending, then S is
707 * irrelevant, because we are going to fetch all samples.
709 if (key
->blend
&& !key
->blit_scaled
) {
711 /* Gen6 hardware an automatically blend using the SAMPLE message */
713 sample(texture_data
[0]);
715 /* Gen7+ hardware doesn't automaticaly blend. */
716 manual_blend_average(key
->src_samples
);
718 } else if(key
->blend
&& key
->blit_scaled
) {
719 manual_blend_bilinear(key
->src_samples
);
721 /* We aren't blending, which means we just want to fetch a single sample
722 * from the source surface. The address that we want to fetch from is
723 * related to the X, Y and S values according to the formula:
725 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
727 * If the actual tiling and sample count of the source surface are not
728 * the same as the configuration of the texture, then we need to adjust
729 * the coordinates to compensate for the difference.
731 if ((tex_tiled_w
!= key
->src_tiled_w
||
732 key
->tex_samples
!= key
->src_samples
||
733 key
->tex_layout
!= key
->src_layout
) &&
734 !key
->bilinear_filter
) {
735 encode_msaa(key
->src_samples
, key
->src_layout
);
736 /* Now (X, Y, S) = detile(src_tiling, offset) */
737 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
738 /* Now (X, Y, S) = detile(tex_tiling, offset) */
739 decode_msaa(key
->tex_samples
, key
->tex_layout
);
742 if (key
->bilinear_filter
) {
743 sample(texture_data
[0]);
746 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
748 * In other words: X, Y, and S now contain values which, when passed to
749 * the texturing unit, will cause data to be read from the correct
750 * memory location. So we can fetch the texel now.
752 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
754 texel_fetch(texture_data
[0]);
758 /* Finally, write the fetched (or blended) value to the render target and
759 * terminate the thread.
761 render_target_write();
763 return get_program(program_size
);
767 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
769 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
770 #define ALLOC_REG(name, type) \
772 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
773 base_reg + CONST_LOC(name) / 32, \
774 (CONST_LOC(name) % 32) / 4), type)
776 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
777 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
778 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
779 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
780 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
781 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
782 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
783 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
784 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
785 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
791 brw_blorp_blit_program::alloc_regs()
794 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
795 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
796 prog_data
.first_curbe_grf
= reg
;
797 alloc_push_const_regs(reg
);
798 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
799 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
800 this->texture_data
[i
] =
801 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
805 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
807 for (int i
= 0; i
< 2; ++i
) {
809 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
812 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
816 if (key
->blit_scaled
&& key
->blend
) {
817 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
819 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
821 this->x_frac
= brw_vec8_grf(reg
, 0);
823 this->y_frac
= brw_vec8_grf(reg
, 0);
827 this->xy_coord_index
= 0;
829 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
831 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
833 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
836 /* Make sure we didn't run out of registers */
837 assert(reg
<= GEN7_MRF_HACK_START
);
840 this->base_mrf
= mrf
;
843 /* In the code that follows, X and Y can be used to quickly refer to the
844 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
845 * prime") to the inactive elements.
847 * S can be used to quickly refer to sample_index.
849 #define X x_coords[xy_coord_index]
850 #define Y y_coords[xy_coord_index]
851 #define Xp x_coords[!xy_coord_index]
852 #define Yp y_coords[!xy_coord_index]
853 #define S sample_index
855 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
856 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
858 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
861 * Emit code to compute the X and Y coordinates of the pixels being rendered
862 * by this WM invocation.
864 * Assuming the render target is set up for Y tiling, these (X, Y) values are
865 * related to the address offset where outputs will be written by the formula:
867 * (X, Y, S) = decode_msaa(detile(offset)).
869 * (See brw_blorp_blit_program).
872 brw_blorp_blit_program::compute_frag_coords()
874 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
875 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
876 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
877 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
879 * Pixels within a subspan are laid out in this arrangement:
883 * So, to compute the coordinates of each pixel, we need to read every 2nd
884 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
885 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
886 * In other words, the data we want to access is R1.4<2;4,0>UW.
888 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
889 * result, since pixels n+1 and n+3 are in the right half of the subspan.
891 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
892 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
894 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
895 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
896 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
899 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
900 * pixels n+2 and n+3 are in the bottom half of the subspan.
902 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
903 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
905 /* Move the coordinates to UD registers. */
906 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
907 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
910 if (key
->persample_msaa_dispatch
) {
911 switch (key
->rt_samples
) {
913 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
914 * Therefore, subspan 0 will represent sample 0, subspan 1 will
915 * represent sample 1, and so on.
917 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
918 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
919 * populate a temporary variable with the sequence (0, 1, 2, 3), and
920 * then copy from it using vstride=1, width=4, hstride=0.
922 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
923 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
924 /* Move to UD sample_index register. */
925 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
926 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
930 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
931 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
932 * subspan 1 will represent sample 1, and so on. We can find the
933 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
934 * Index") and multiplying by two (since samples are always delivered
935 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
938 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
939 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
940 * variable with the sequence (0, 1, 2, 3), and then reading from it
941 * using vstride=1, width=4, hstride=0.
943 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
944 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
945 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
946 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
947 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
948 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
949 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
950 stride(t2_uw1
, 1, 4, 0));
951 emit_add_8(offset(S
, 1),
952 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
953 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
957 unreachable("Unrecognized sample count in "
958 "brw_blorp_blit_program::compute_frag_coords()");
962 /* Either the destination surface is single-sampled, or the WM will be
963 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
964 * per pixel). In either case, it's not meaningful to compute a sample
965 * value. Just set it to 0.
972 * Emit code to compensate for the difference between Y and W tiling.
974 * This code modifies the X and Y coordinates according to the formula:
976 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
978 * (See brw_blorp_blit_program).
980 * It can only translate between W and Y tiling, so new_tiling and old_tiling
981 * are booleans where true represents W tiling and false represents Y tiling.
984 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
986 if (old_tiled_w
== new_tiled_w
)
989 /* In the code that follows, we can safely assume that S = 0, because W
990 * tiling formats always use IMS layout.
995 /* Given X and Y coordinates that describe an address using Y tiling,
996 * translate to the X and Y coordinates that describe the same address
999 * If we break down the low order bits of X and Y, using a
1000 * single letter to represent each low-order bit:
1002 * X = A << 7 | 0bBCDEFGH
1003 * Y = J << 5 | 0bKLMNP (1)
1005 * Then we can apply the Y tiling formula to see the memory offset being
1008 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1010 * If we apply the W detiling formula to this memory location, that the
1011 * corresponding X' and Y' coordinates are:
1013 * X' = A << 6 | 0bBCDPFH (3)
1014 * Y' = J << 6 | 0bKLMNEG
1016 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1017 * we need to make the following computation:
1019 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1020 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1022 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1023 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1024 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1025 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1026 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1027 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1028 emit_or(Xp
, t1
, t2
);
1029 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1030 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1031 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1032 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1033 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1034 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1035 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1036 emit_or(Yp
, t1
, t2
);
1039 /* Applying the same logic as above, but in reverse, we obtain the
1042 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1043 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1045 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1046 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1047 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1048 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1049 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1050 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1051 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1052 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1054 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1055 emit_or(Xp
, t1
, t2
);
1056 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1057 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1058 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1059 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1060 emit_or(Yp
, t1
, t2
);
1066 * Emit code to compensate for the difference between MSAA and non-MSAA
1069 * This code modifies the X and Y coordinates according to the formula:
1071 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1073 * (See brw_blorp_blit_program).
1076 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1077 intel_msaa_layout layout
)
1080 case INTEL_MSAA_LAYOUT_NONE
:
1081 /* No translation necessary, and S should already be zero. */
1084 case INTEL_MSAA_LAYOUT_CMS
:
1085 /* We can't compensate for compressed layout since at this point in the
1086 * program we haven't read from the MCS buffer.
1088 unreachable("Bad layout in encode_msaa");
1089 case INTEL_MSAA_LAYOUT_UMS
:
1090 /* No translation necessary. */
1092 case INTEL_MSAA_LAYOUT_IMS
:
1093 switch (num_samples
) {
1095 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1096 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1097 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1099 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1101 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1102 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1104 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1106 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1107 emit_or(Xp
, t1
, t2
);
1108 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1109 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1111 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1112 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1114 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1115 emit_or(Yp
, t1
, t2
);
1118 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1119 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1121 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1123 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1124 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1126 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1127 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1128 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1129 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1130 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1133 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1134 emit_or(Xp
, t1
, t2
);
1135 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1136 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1138 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1139 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1141 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1142 emit_or(Yp
, t1
, t2
);
1152 * Emit code to compensate for the difference between MSAA and non-MSAA
1155 * This code modifies the X and Y coordinates according to the formula:
1157 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1159 * (See brw_blorp_blit_program).
1162 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1163 intel_msaa_layout layout
)
1166 case INTEL_MSAA_LAYOUT_NONE
:
1167 /* No translation necessary, and S should already be zero. */
1170 case INTEL_MSAA_LAYOUT_CMS
:
1171 /* We can't compensate for compressed layout since at this point in the
1172 * program we don't have access to the MCS buffer.
1174 unreachable("Bad layout in encode_msaa");
1175 case INTEL_MSAA_LAYOUT_UMS
:
1176 /* No translation necessary. */
1178 case INTEL_MSAA_LAYOUT_IMS
:
1180 switch (num_samples
) {
1182 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1183 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1184 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1185 * S = (Y & 0b10) | (X & 0b10) >> 1
1187 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1188 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1189 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1190 emit_or(Xp
, t1
, t2
);
1191 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1192 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1193 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1194 emit_or(Yp
, t1
, t2
);
1195 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1196 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1197 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1201 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1202 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1203 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1204 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1206 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1207 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1208 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1209 emit_or(Xp
, t1
, t2
);
1210 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1211 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1212 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1213 emit_or(Yp
, t1
, t2
);
1214 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1215 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1216 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1217 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1218 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1229 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1233 brw_blorp_blit_program::translate_dst_to_src()
1235 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1236 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1237 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1238 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1240 /* Move the UD coordinates to float registers. */
1243 /* Scale and offset */
1244 emit_mul(X_f
, Xp_f
, x_transform
.multiplier
);
1245 emit_mul(Y_f
, Yp_f
, y_transform
.multiplier
);
1246 emit_add(X_f
, X_f
, x_transform
.offset
);
1247 emit_add(Y_f
, Y_f
, y_transform
.offset
);
1248 if (key
->blit_scaled
&& key
->blend
) {
1249 /* Translate coordinates to lay out the samples in a rectangular grid
1250 * roughly corresponding to sample locations.
1252 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1253 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1254 /* Adjust coordinates so that integers represent pixel centers rather
1257 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1258 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1260 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1261 * texels on texture edges.
1263 clamp_tex_coords(X_f
, Y_f
,
1264 brw_imm_f(0.0), brw_imm_f(0.0),
1265 rect_grid_x1
, rect_grid_y1
);
1267 /* Store the fractional parts to be used as bilinear interpolation
1270 emit_frc(x_frac
, X_f
);
1271 emit_frc(y_frac
, Y_f
);
1273 /* Round the float coordinates down to nearest integer */
1274 emit_rndd(Xp_f
, X_f
);
1275 emit_rndd(Yp_f
, Y_f
);
1276 emit_mul(X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1277 emit_mul(Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1279 } else if (!key
->bilinear_filter
) {
1280 /* Round the float coordinates down to nearest integer by moving to
1290 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1291 struct brw_reg regY
,
1292 struct brw_reg clampX0
,
1293 struct brw_reg clampY0
,
1294 struct brw_reg clampX1
,
1295 struct brw_reg clampY1
)
1297 emit_cond_mov(regX
, clampX0
, BRW_CONDITIONAL_L
, regX
, clampX0
);
1298 emit_cond_mov(regX
, clampX1
, BRW_CONDITIONAL_G
, regX
, clampX1
);
1299 emit_cond_mov(regY
, clampY0
, BRW_CONDITIONAL_L
, regY
, clampY0
);
1300 emit_cond_mov(regY
, clampY1
, BRW_CONDITIONAL_G
, regY
, clampY1
);
1304 * Emit code to transform the X and Y coordinates as needed for blending
1305 * together the different samples in an MSAA texture.
1308 brw_blorp_blit_program::single_to_blend()
1310 /* When looking up samples in an MSAA texture using the SAMPLE message,
1311 * Gen6 requires the texture coordinates to be odd integers (so that they
1312 * correspond to the center of a 2x2 block representing the four samples
1313 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1314 * each by 2 and then add 1.
1316 emit_shl(t1
, X
, brw_imm_w(1));
1317 emit_shl(t2
, Y
, brw_imm_w(1));
1318 emit_add(Xp
, t1
, brw_imm_w(1));
1319 emit_add(Yp
, t2
, brw_imm_w(1));
1325 * Count the number of trailing 1 bits in the given value. For example:
1327 * count_trailing_one_bits(0) == 0
1328 * count_trailing_one_bits(7) == 3
1329 * count_trailing_one_bits(11) == 2
1331 inline int count_trailing_one_bits(unsigned value
)
1333 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1334 return __builtin_ctz(~value
);
1336 return _mesa_bitcount(value
& ~(value
+ 1));
1342 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1344 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1347 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1349 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1351 * This ensures that when all samples have the same value, no numerical
1352 * precision is lost, since each addition operation always adds two equal
1353 * values, and summing two equal floating point values does not lose
1356 * We perform this computation by treating the texture_data array as a
1357 * stack and performing the following operations:
1359 * - push sample 0 onto stack
1360 * - push sample 1 onto stack
1361 * - add top two stack entries
1362 * - push sample 2 onto stack
1363 * - push sample 3 onto stack
1364 * - add top two stack entries
1365 * - add top two stack entries
1366 * - divide top stack entry by 4
1368 * Note that after pushing sample i onto the stack, the number of add
1369 * operations we do is equal to the number of trailing 1 bits in i. This
1370 * works provided the total number of samples is a power of two, which it
1371 * always is for i965.
1373 * For integer formats, we replace the add operations with average
1374 * operations and skip the final division.
1376 unsigned stack_depth
= 0;
1377 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1378 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1380 /* Push sample i onto the stack */
1381 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1386 emit_mov(vec16(S
), brw_imm_ud(i
));
1388 texel_fetch(texture_data
[stack_depth
++]);
1390 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1391 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1392 * suggests an optimization:
1394 * "A simple optimization with probable large return in
1395 * performance is to compare the MCS value to zero (indicating
1396 * all samples are on sample slice 0), and sample only from
1397 * sample slice 0 using ld2dss if MCS is zero."
1399 * Note that in the case where the MCS value is zero, sampling from
1400 * sample slice 0 using ld2dss and sampling from sample 0 using
1401 * ld2dms are equivalent (since all samples are on sample slice 0).
1402 * Since we have already sampled from sample 0, all we need to do is
1403 * skip the remaining fetches and averaging if MCS is zero.
1405 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1408 /* Do count_trailing_one_bits(i) times */
1409 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1410 assert(stack_depth
>= 2);
1413 /* TODO: should use a smaller loop bound for non_RGBA formats */
1414 for (int k
= 0; k
< 4; ++k
) {
1415 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1416 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1417 offset(texture_data
[stack_depth
- 1], 2*k
),
1418 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1419 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1424 /* We should have just 1 sample on the stack now. */
1425 assert(stack_depth
== 1);
1427 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1428 /* Scale the result down by a factor of num_samples */
1429 /* TODO: should use a smaller loop bound for non-RGBA formats */
1430 for (int j
= 0; j
< 4; ++j
) {
1431 emit_mul(offset(texture_data
[0], 2*j
),
1432 offset(vec8(texture_data
[0]), 2*j
),
1433 brw_imm_f(1.0/num_samples
));
1437 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1442 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1444 /* We do this computation by performing the following operations:
1446 * In case of 4x, 8x MSAA:
1447 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1448 * which are later used for interpolation
1449 * - linearly interpolate samples a and b in X
1450 * - linearly interpolate samples c and d in X
1451 * - linearly interpolate the results of last two operations in Y
1453 * result = lrp(lrp(a + b) + lrp(c + d))
1455 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1456 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1457 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1458 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1460 for (unsigned i
= 0; i
< 4; ++i
) {
1461 assert(i
< ARRAY_SIZE(texture_data
));
1464 /* Compute pixel coordinates */
1465 emit_add(vec16(x_sample_coords
), Xp_f
,
1466 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1467 emit_add(vec16(y_sample_coords
), Yp_f
,
1468 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1469 emit_mov(vec16(X
), x_sample_coords
);
1470 emit_mov(vec16(Y
), y_sample_coords
);
1472 /* The MCS value we fetch has to match up with the pixel that we're
1473 * sampling from. Since we sample from different pixels in each
1474 * iteration of this "for" loop, the call to mcs_fetch() should be
1475 * here inside the loop after computing the pixel coordinates.
1477 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1480 /* Compute sample index and map the sample index to a sample number.
1481 * Sample index layout shows the numbering of slots in a rectangular
1482 * grid of samples with in a pixel. Sample number layout shows the
1483 * rectangular grid of samples roughly corresponding to the real sample
1484 * locations with in a pixel.
1485 * In case of 4x MSAA, layout of sample indices matches the layout of
1493 * In case of 8x MSAA the two layouts don't match.
1494 * sample index layout : --------- sample number layout : ---------
1495 * | 0 | 1 | | 5 | 2 |
1496 * --------- ---------
1497 * | 2 | 3 | | 4 | 6 |
1498 * --------- ---------
1499 * | 4 | 5 | | 0 | 3 |
1500 * --------- ---------
1501 * | 6 | 7 | | 7 | 1 |
1502 * --------- ---------
1504 emit_frc(vec16(t1_f
), x_sample_coords
);
1505 emit_frc(vec16(t2_f
), y_sample_coords
);
1506 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1507 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1508 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1509 emit_mov(vec16(S
), t1_f
);
1511 if (num_samples
== 8) {
1512 /* Map the sample index to a sample number */
1513 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1515 emit_mov(vec16(t2
), brw_imm_d(5));
1516 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1517 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1518 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1522 emit_mov(vec16(t2
), brw_imm_d(0));
1523 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1524 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1525 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1528 emit_mov(vec16(S
), t2
);
1530 texel_fetch(texture_data
[i
]);
1533 #define SAMPLE(x, y) offset(texture_data[x], y)
1534 for (int index
= 3; index
> 0; ) {
1535 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1536 * Counter value of 8 in 'for' loop below is used to interpolate all
1537 * the color components.
1539 for (int k
= 0; k
< 8; k
+= 2)
1540 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1542 vec8(SAMPLE(index
, k
)),
1543 vec8(SAMPLE(index
- 1, k
)));
1546 for (int k
= 0; k
< 8; k
+= 2)
1547 emit_lrp(vec8(SAMPLE(0, k
)),
1550 vec8(SAMPLE(0, k
)));
1555 * Emit code to look up a value in the texture using the SAMPLE message (which
1556 * does blending of MSAA surfaces).
1559 brw_blorp_blit_program::sample(struct brw_reg dst
)
1561 static const sampler_message_arg args
[2] = {
1562 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1563 SAMPLER_MESSAGE_ARG_V_FLOAT
1566 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1570 * Emit code to look up a value in the texture using the SAMPLE_LD message
1571 * (which does a simple texel fetch).
1574 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1576 static const sampler_message_arg gen6_args
[5] = {
1577 SAMPLER_MESSAGE_ARG_U_INT
,
1578 SAMPLER_MESSAGE_ARG_V_INT
,
1579 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1580 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1581 SAMPLER_MESSAGE_ARG_SI_INT
1583 static const sampler_message_arg gen7_ld_args
[3] = {
1584 SAMPLER_MESSAGE_ARG_U_INT
,
1585 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1586 SAMPLER_MESSAGE_ARG_V_INT
1588 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1589 SAMPLER_MESSAGE_ARG_SI_INT
,
1590 SAMPLER_MESSAGE_ARG_U_INT
,
1591 SAMPLER_MESSAGE_ARG_V_INT
1593 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1594 SAMPLER_MESSAGE_ARG_SI_INT
,
1595 SAMPLER_MESSAGE_ARG_MCS_INT
,
1596 SAMPLER_MESSAGE_ARG_U_INT
,
1597 SAMPLER_MESSAGE_ARG_V_INT
1602 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1605 switch (key
->tex_layout
) {
1606 case INTEL_MSAA_LAYOUT_IMS
:
1607 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1610 * If this field is MSFMT_DEPTH_STENCIL
1611 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1612 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1614 * So fall through to emit the same message as we use for
1615 * INTEL_MSAA_LAYOUT_CMS.
1617 case INTEL_MSAA_LAYOUT_CMS
:
1618 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1619 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1621 case INTEL_MSAA_LAYOUT_UMS
:
1622 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1623 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1625 case INTEL_MSAA_LAYOUT_NONE
:
1627 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1628 ARRAY_SIZE(gen7_ld_args
));
1633 unreachable("Should not get here.");
1638 brw_blorp_blit_program::mcs_fetch()
1640 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1641 SAMPLER_MESSAGE_ARG_U_INT
,
1642 SAMPLER_MESSAGE_ARG_V_INT
1644 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1645 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1649 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1651 const sampler_message_arg
*args
,
1654 struct brw_reg mrf
=
1655 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1656 for (int arg
= 0; arg
< num_args
; ++arg
) {
1657 switch (args
[arg
]) {
1658 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1659 if (key
->bilinear_filter
)
1660 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1661 retype(X
, BRW_REGISTER_TYPE_F
));
1663 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1665 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1666 if (key
->bilinear_filter
)
1667 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1668 retype(Y
, BRW_REGISTER_TYPE_F
));
1670 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1672 case SAMPLER_MESSAGE_ARG_U_INT
:
1675 case SAMPLER_MESSAGE_ARG_V_INT
:
1678 case SAMPLER_MESSAGE_ARG_SI_INT
:
1679 /* Note: on Gen7, this code may be reached with s_is_zero==true
1680 * because in Gen7's ld2dss message, the sample index is the first
1681 * argument. When this happens, we need to move a 0 into the
1682 * appropriate message register.
1685 emit_mov(mrf
, brw_imm_ud(0));
1689 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1690 switch (key
->tex_layout
) {
1691 case INTEL_MSAA_LAYOUT_CMS
:
1692 emit_mov(mrf
, mcs_data
);
1694 case INTEL_MSAA_LAYOUT_IMS
:
1695 /* When sampling from an IMS surface, MCS data is not relevant,
1696 * and the hardware ignores it. So don't bother populating it.
1700 /* We shouldn't be trying to send MCS data with any other
1703 assert (!"Unsupported layout for MCS data");
1707 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1708 emit_mov(mrf
, brw_imm_ud(0));
1714 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1717 mrf
.nr
- base_mrf
/* msg_length */);
1725 #undef SWAP_XY_AND_XPYP
1728 brw_blorp_blit_program::render_target_write()
1730 struct brw_reg mrf_rt_write
=
1731 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1734 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1735 * so that the render target knows which pixels we killed.
1737 bool use_header
= key
->use_kill
;
1739 /* Copy R0/1 to MRF */
1740 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1741 retype(R0
, BRW_REGISTER_TYPE_UD
));
1745 /* Copy texture data to MRFs */
1746 for (int i
= 0; i
< 4; ++i
) {
1747 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1748 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1749 offset(vec8(texture_data
[0]), 2*i
));
1753 /* Now write to the render target and terminate the thread */
1754 emit_render_target_write(
1757 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1763 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1764 GLfloat dst0
, GLfloat dst1
,
1767 float scale
= (src1
- src0
) / (dst1
- dst0
);
1769 /* When not mirroring a coordinate (say, X), we need:
1770 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1772 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1774 * blorp program uses "round toward zero" to convert the
1775 * transformed floating point coordinates to integer coordinates,
1776 * whereas the behaviour we actually want is "round to nearest",
1777 * so 0.5 provides the necessary correction.
1780 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1782 /* When mirroring X we need:
1783 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1785 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1787 multiplier
= -scale
;
1788 offset
= src0
+ (dst1
- 0.5) * scale
;
1794 * Determine which MSAA layout the GPU pipeline should be configured for,
1795 * based on the chip generation, the number of samples, and the true layout of
1796 * the image in memory.
1798 inline intel_msaa_layout
1799 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1800 intel_msaa_layout true_layout
)
1802 if (num_samples
<= 1) {
1803 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1804 * format buffers, by transforming coordinates appropriately.
1806 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1807 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1808 return INTEL_MSAA_LAYOUT_NONE
;
1810 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1813 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1814 if (brw
->gen
== 6) {
1815 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1822 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1823 struct intel_mipmap_tree
*src_mt
,
1824 unsigned src_level
, unsigned src_layer
,
1825 struct intel_mipmap_tree
*dst_mt
,
1826 unsigned dst_level
, unsigned dst_layer
,
1827 GLfloat src_x0
, GLfloat src_y0
,
1828 GLfloat src_x1
, GLfloat src_y1
,
1829 GLfloat dst_x0
, GLfloat dst_y0
,
1830 GLfloat dst_x1
, GLfloat dst_y1
,
1832 bool mirror_x
, bool mirror_y
)
1834 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
1835 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
1837 /* Even though we do multisample resolves at the time of the blit, OpenGL
1838 * specification defines them as if they happen at the time of rendering,
1839 * which means that the type of averaging we do during the resolve should
1840 * only depend on the source format; the destination format should be
1841 * ignored. But, specification doesn't seem to be strict about it.
1843 * It has been observed that mulitisample resolves produce slightly better
1844 * looking images when averaging is done using destination format. NVIDIA's
1845 * proprietary OpenGL driver also follow this approach. So, we choose to
1846 * follow it in our driver.
1848 * When multisampling, if the source and destination formats are equal
1849 * (aside from the color space), we choose to blit in sRGB space to get
1850 * this higher quality image.
1852 if (src
.num_samples
> 1 &&
1853 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1854 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1855 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1856 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1857 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1860 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1861 * texture, the above code configures the source format for L32_FLOAT or
1862 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1863 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1864 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1865 * around the problem by using a source format of R32_FLOAT. This
1866 * shouldn't affect rendering correctness, since the destination format is
1867 * R32_FLOAT, so only the contents of the red channel matters.
1869 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1870 src_mt
->format
== dst_mt
->format
&&
1871 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1872 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1876 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1878 /* texture_data_type indicates the register type that should be used to
1879 * manipulate texture data.
1881 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1882 case GL_UNSIGNED_NORMALIZED
:
1883 case GL_SIGNED_NORMALIZED
:
1885 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1887 case GL_UNSIGNED_INT
:
1888 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1889 /* We process stencil as though it's an unsigned normalized color */
1890 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1892 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1896 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1899 unreachable("Unrecognized blorp format");
1903 /* Gen7's rendering hardware only supports the IMS layout for depth and
1904 * stencil render targets. Blorp always maps its destination surface as
1905 * a color render target (even if it's actually a depth or stencil
1906 * buffer). So if the destination is IMS, we'll have to map it as a
1907 * single-sampled texture and interleave the samples ourselves.
1909 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1910 dst
.num_samples
= 0;
1913 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1914 /* If the destination surface is a W-tiled multisampled stencil buffer
1915 * that we're mapping as Y tiled, then we need to arrange for the WM
1916 * program to run once per sample rather than once per pixel, because
1917 * the memory layout of related samples doesn't match between W and Y
1920 wm_prog_key
.persample_msaa_dispatch
= true;
1923 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1924 /* We are blitting from a multisample buffer to a multisample buffer, so
1925 * we must preserve samples within a pixel. This means we have to
1926 * arrange for the WM program to run once per sample rather than once
1929 wm_prog_key
.persample_msaa_dispatch
= true;
1932 /* Scaled blitting or not. */
1933 wm_prog_key
.blit_scaled
=
1934 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1935 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1937 /* Scaling factors used for bilinear filtering in multisample scaled
1940 wm_prog_key
.x_scale
= 2.0;
1941 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
1943 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
1944 wm_prog_key
.bilinear_filter
= true;
1946 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1947 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1948 base_format
!= GL_STENCIL_INDEX
&&
1949 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1950 /* We are downsampling a color buffer, so blend. */
1951 wm_prog_key
.blend
= true;
1954 /* src_samples and dst_samples are the true sample counts */
1955 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1956 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1958 /* tex_samples and rt_samples are the sample counts that are set up in
1961 wm_prog_key
.tex_samples
= src
.num_samples
;
1962 wm_prog_key
.rt_samples
= dst
.num_samples
;
1964 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1965 * use to access the source and destination surfaces.
1967 wm_prog_key
.tex_layout
=
1968 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1969 wm_prog_key
.rt_layout
=
1970 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1972 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1975 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1976 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1978 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1979 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1980 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1981 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1982 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1983 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1984 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
1985 wm_prog_key
.x_scale
- 1.0);
1986 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
1987 wm_prog_key
.y_scale
- 1.0);
1989 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
1990 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
1992 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
1993 /* We must expand the rectangle we send through the rendering pipeline,
1994 * to account for the fact that we are mapping the destination region as
1995 * single-sampled when it is in fact multisampled. We must also align
1996 * it to a multiple of the multisampling pattern, because the
1997 * differences between multisampled and single-sampled surface formats
1998 * will mean that pixels are scrambled within the multisampling pattern.
1999 * TODO: what if this makes the coordinates too large?
2001 * Note: this only works if the destination surface uses the IMS layout.
2002 * If it's UMS, then we have no choice but to set up the rendering
2003 * pipeline as multisampled.
2005 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2006 switch (dst_mt
->num_samples
) {
2008 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2009 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2010 x1
= ALIGN(x1
* 2, 4);
2011 y1
= ALIGN(y1
* 2, 4);
2014 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2015 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2016 x1
= ALIGN(x1
* 4, 8);
2017 y1
= ALIGN(y1
* 2, 4);
2020 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2022 wm_prog_key
.use_kill
= true;
2025 if (dst
.map_stencil_as_y_tiled
) {
2026 /* We must modify the rectangle we send through the rendering pipeline
2027 * (and the size and x/y offset of the destination surface), to account
2028 * for the fact that we are mapping it as Y-tiled when it is in fact
2031 * Both Y tiling and W tiling can be understood as organizations of
2032 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2033 * is different, but the layout of the 32-byte sub-tiles within the 4k
2034 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2035 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2036 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2038 * Therefore, to account for the layout differences within the 32-byte
2039 * sub-tiles, we must expand the rectangle so the X coordinates of its
2040 * edges are multiples of 8 (the W sub-tile width), and its Y
2041 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2042 * Then we need to scale the X and Y coordinates of the rectangle to
2043 * account for the differences in aspect ratio between the Y and W
2044 * sub-tiles. We need to modify the layer width and height similarly.
2046 * A correction needs to be applied when MSAA is in use: since
2047 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2048 * we need to align the Y coordinates to multiples of 8, so that when
2049 * they are divided by two they are still multiples of 4.
2051 * Note: Since the x/y offset of the surface will be applied using the
2052 * SURFACE_STATE command packet, it will be invisible to the swizzling
2053 * code in the shader; therefore it needs to be in a multiple of the
2054 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2055 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2056 * buffer), and the miplevel alignment used for stencil buffers is 8
2057 * pixels horizontally and either 4 or 8 pixels vertically (see
2058 * intel_horizontal_texture_alignment_unit() and
2059 * intel_vertical_texture_alignment_unit()).
2061 * Note: Also, since the SURFACE_STATE command packet can only apply
2062 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2063 * vertically, it is important that the offsets will be multiples of
2064 * these sizes after they are converted into Y-tiled coordinates.
2065 * Fortunately they will be, since we know from above that the offsets
2066 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2067 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2069 * TODO: what if this makes the coordinates (or the texture size) too
2072 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2073 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2074 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2075 x1
= ALIGN(x1
, x_align
) * 2;
2076 y1
= ALIGN(y1
, y_align
) / 2;
2077 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2078 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2081 wm_prog_key
.use_kill
= true;
2084 if (src
.map_stencil_as_y_tiled
) {
2085 /* We must modify the size and x/y offset of the source surface to
2086 * account for the fact that we are mapping it as Y-tiled when it is in
2089 * See the comments above concerning x/y offset alignment for the
2090 * destination surface.
2092 * TODO: what if this makes the texture size too large?
2094 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2095 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2096 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2103 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2104 brw_blorp_prog_data
**prog_data
) const
2106 uint32_t prog_offset
= 0;
2107 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2108 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2109 &prog_offset
, prog_data
)) {
2110 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
,
2111 INTEL_DEBUG
& DEBUG_BLORP
);
2112 GLuint program_size
;
2113 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2114 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2115 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2116 program
, program_size
,
2117 &prog
.prog_data
, sizeof(prog
.prog_data
),
2118 &prog_offset
, prog_data
);