2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
49 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
50 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
51 * the physical layer holding sample 0. So, for example, if
52 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
56 brw_blorp_blit_miptrees(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*src_mt
,
58 unsigned src_level
, unsigned src_layer
,
59 mesa_format src_format
,
60 struct intel_mipmap_tree
*dst_mt
,
61 unsigned dst_level
, unsigned dst_layer
,
62 mesa_format dst_format
,
63 float src_x0
, float src_y0
,
64 float src_x1
, float src_y1
,
65 float dst_x0
, float dst_y0
,
66 float dst_x1
, float dst_y1
,
67 GLenum filter
, bool mirror_x
, bool mirror_y
)
69 /* Get ready to blit. This includes depth resolving the src and dst
70 * buffers if necessary. Note: it's not necessary to do a color resolve on
71 * the destination buffer because we use the standard render path to render
72 * to destination color buffers, and the standard render path is
75 intel_miptree_resolve_color(brw
, src_mt
);
76 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
77 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
79 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
80 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
82 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
83 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
84 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
85 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
88 brw_blorp_blit_params
params(brw
,
89 src_mt
, src_level
, src_layer
, src_format
,
90 dst_mt
, dst_level
, dst_layer
, dst_format
,
95 filter
, mirror_x
, mirror_y
);
96 brw_blorp_exec(brw
, ¶ms
);
98 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
102 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
103 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
104 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
105 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
106 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
107 GLenum filter
, bool mirror_x
, bool mirror_y
)
109 /* Find source/dst miptrees */
110 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
111 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
114 brw_blorp_blit_miptrees(brw
,
115 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
117 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
119 srcX0
, srcY0
, srcX1
, srcY1
,
120 dstX0
, dstY0
, dstX1
, dstY1
,
121 filter
, mirror_x
, mirror_y
);
123 dst_irb
->need_downsample
= true;
127 try_blorp_blit(struct brw_context
*brw
,
128 const struct gl_framebuffer
*read_fb
,
129 const struct gl_framebuffer
*draw_fb
,
130 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
131 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
132 GLenum filter
, GLbitfield buffer_bit
)
134 struct gl_context
*ctx
= &brw
->ctx
;
136 /* Sync up the state of window system buffers. We need to do this before
137 * we go looking for the buffers.
139 intel_prepare_render(brw
);
141 bool mirror_x
, mirror_y
;
142 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
143 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
144 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
145 &mirror_x
, &mirror_y
))
149 struct intel_renderbuffer
*src_irb
;
150 struct intel_renderbuffer
*dst_irb
;
151 struct intel_mipmap_tree
*src_mt
;
152 struct intel_mipmap_tree
*dst_mt
;
153 switch (buffer_bit
) {
154 case GL_COLOR_BUFFER_BIT
:
155 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
156 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
157 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
159 do_blorp_blit(brw
, buffer_bit
,
160 src_irb
, src_irb
->Base
.Base
.Format
,
161 dst_irb
, dst_irb
->Base
.Base
.Format
,
162 srcX0
, srcY0
, srcX1
, srcY1
,
163 dstX0
, dstY0
, dstX1
, dstY1
,
164 filter
, mirror_x
, mirror_y
);
167 case GL_DEPTH_BUFFER_BIT
:
169 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
171 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
172 src_mt
= find_miptree(buffer_bit
, src_irb
);
173 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
175 /* We can't handle format conversions between Z24 and other formats
176 * since we have to lie about the surface format. See the comments in
177 * brw_blorp_surface_info::set().
179 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
180 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
183 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
184 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
185 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
186 filter
, mirror_x
, mirror_y
);
188 case GL_STENCIL_BUFFER_BIT
:
190 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
192 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
193 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
194 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
195 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
196 filter
, mirror_x
, mirror_y
);
199 unreachable("not reached");
206 brw_blorp_copytexsubimage(struct brw_context
*brw
,
207 struct gl_renderbuffer
*src_rb
,
208 struct gl_texture_image
*dst_image
,
210 int srcX0
, int srcY0
,
211 int dstX0
, int dstY0
,
212 int width
, int height
)
214 struct gl_context
*ctx
= &brw
->ctx
;
215 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
216 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
218 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
219 if (brw
->ctx
._ImageTransferState
)
222 /* Sync up the state of window system buffers. We need to do this before
223 * we go looking at the src renderbuffer's miptree.
225 intel_prepare_render(brw
);
227 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
228 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
230 /* BLORP is only supported for Gen6-7. */
231 if (brw
->gen
< 6 || brw
->gen
> 7)
234 if (_mesa_get_format_base_format(src_rb
->Format
) !=
235 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
239 /* We can't handle format conversions between Z24 and other formats since
240 * we have to lie about the surface format. See the comments in
241 * brw_blorp_surface_info::set().
243 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
244 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
248 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
251 /* Source clipping shouldn't be necessary, since copytexsubimage (in
252 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
255 * Destination clipping shouldn't be necessary since the restrictions on
256 * glCopyTexSubImage prevent the user from specifying a destination rectangle
257 * that falls outside the bounds of the destination texture.
258 * See error_check_subtexture_dimensions().
261 int srcY1
= srcY0
+ height
;
262 int srcX1
= srcX0
+ width
;
263 int dstX1
= dstX0
+ width
;
264 int dstY1
= dstY0
+ height
;
266 /* Account for the fact that in the system framebuffer, the origin is at
269 bool mirror_y
= false;
270 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
271 GLint tmp
= src_rb
->Height
- srcY0
;
272 srcY0
= src_rb
->Height
- srcY1
;
277 /* Account for face selection and texture view MinLayer */
278 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
279 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
281 brw_blorp_blit_miptrees(brw
,
282 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
284 dst_mt
, dst_level
, dst_slice
,
285 dst_image
->TexFormat
,
286 srcX0
, srcY0
, srcX1
, srcY1
,
287 dstX0
, dstY0
, dstX1
, dstY1
,
288 GL_NEAREST
, false, mirror_y
);
290 /* If we're copying to a packed depth stencil texture and the source
291 * framebuffer has separate stencil, we need to also copy the stencil data
294 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
295 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
297 src_irb
= intel_renderbuffer(src_rb
);
298 src_mt
= src_irb
->mt
;
300 if (src_mt
->stencil_mt
)
301 src_mt
= src_mt
->stencil_mt
;
302 if (dst_mt
->stencil_mt
)
303 dst_mt
= dst_mt
->stencil_mt
;
305 if (src_mt
!= dst_mt
) {
306 brw_blorp_blit_miptrees(brw
,
307 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
309 dst_mt
, dst_level
, dst_slice
,
311 srcX0
, srcY0
, srcX1
, srcY1
,
312 dstX0
, dstY0
, dstX1
, dstY1
,
313 GL_NEAREST
, false, mirror_y
);
322 brw_blorp_framebuffer(struct brw_context
*brw
,
323 struct gl_framebuffer
*readFb
,
324 struct gl_framebuffer
*drawFb
,
325 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
326 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
327 GLbitfield mask
, GLenum filter
)
329 /* BLORP is not supported before Gen6. */
330 if (brw
->gen
< 6 || brw
->gen
>= 8)
333 static GLbitfield buffer_bits
[] = {
336 GL_STENCIL_BUFFER_BIT
,
339 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
340 if ((mask
& buffer_bits
[i
]) &&
341 try_blorp_blit(brw
, readFb
, drawFb
,
342 srcX0
, srcY0
, srcX1
, srcY1
,
343 dstX0
, dstY0
, dstX1
, dstY1
,
344 filter
, buffer_bits
[i
])) {
345 mask
&= ~buffer_bits
[i
];
354 * Enum to specify the order of arguments in a sampler message
356 enum sampler_message_arg
358 SAMPLER_MESSAGE_ARG_U_FLOAT
,
359 SAMPLER_MESSAGE_ARG_V_FLOAT
,
360 SAMPLER_MESSAGE_ARG_U_INT
,
361 SAMPLER_MESSAGE_ARG_V_INT
,
362 SAMPLER_MESSAGE_ARG_SI_INT
,
363 SAMPLER_MESSAGE_ARG_MCS_INT
,
364 SAMPLER_MESSAGE_ARG_ZERO_INT
,
368 * Generator for WM programs used in BLORP blits.
370 * The bulk of the work done by the WM program is to wrap and unwrap the
371 * coordinate transformations used by the hardware to store surfaces in
372 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
373 * sample index for a multisampled surface) to a memory offset by the
374 * following formulas:
376 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
377 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
379 * For a single-sampled surface, or for a multisampled surface using
380 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
383 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
384 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
385 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
386 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
388 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
389 * embeds the sample number into bit 1 of the X and Y coordinates:
391 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
392 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
393 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
394 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
395 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
396 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
397 * S = (Y & 0b10) | (X & 0b10) >> 1
399 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
400 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
403 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
404 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
405 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
406 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
407 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
408 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
409 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
411 * For X tiling, tile() combines together the low-order bits of the X and Y
412 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
413 * bytes wide and 8 rows high:
415 * tile(x_tiled, X, Y, S) = A
416 * where A = tile_num << 12 | offset
417 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
418 * offset = (Y' & 0b111) << 9
419 * | (X & 0b111111111)
421 * Y' = Y + S * qpitch
422 * detile(x_tiled, A) = (X, Y, S)
426 * Y' = (tile_num / tile_pitch) << 3
427 * | (A & 0b111000000000) >> 9
428 * X' = (tile_num % tile_pitch) << 9
429 * | (A & 0b111111111)
431 * (In all tiling formulas, cpp is the number of bytes occupied by a single
432 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
433 * to fill the width of the surface, and qpitch is the spacing (in rows)
434 * between array slices).
436 * For Y tiling, tile() combines together the low-order bits of the X and Y
437 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
438 * bytes wide and 32 rows high:
440 * tile(y_tiled, X, Y, S) = A
441 * where A = tile_num << 12 | offset
442 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
443 * offset = (X' & 0b1110000) << 5
444 * | (Y' & 0b11111) << 4
447 * Y' = Y + S * qpitch
448 * detile(y_tiled, A) = (X, Y, S)
452 * Y' = (tile_num / tile_pitch) << 5
453 * | (A & 0b111110000) >> 4
454 * X' = (tile_num % tile_pitch) << 7
455 * | (A & 0b111000000000) >> 5
458 * For W tiling, tile() combines together the low-order bits of the X and Y
459 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
460 * bytes wide and 64 rows high (note that W tiling is only used for stencil
461 * buffers, which always have cpp = 1 and S=0):
463 * tile(w_tiled, X, Y, S) = A
464 * where A = tile_num << 12 | offset
465 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
466 * offset = (X' & 0b111000) << 6
467 * | (Y' & 0b111100) << 3
468 * | (X' & 0b100) << 2
474 * Y' = Y + S * qpitch
475 * detile(w_tiled, A) = (X, Y, S)
476 * where X = X' / cpp = X'
477 * Y = Y' % qpitch = Y'
479 * Y' = (tile_num / tile_pitch) << 6
480 * | (A & 0b111100000) >> 3
481 * | (A & 0b1000) >> 2
483 * X' = (tile_num % tile_pitch) << 6
484 * | (A & 0b111000000000) >> 6
485 * | (A & 0b10000) >> 2
489 * Finally, for a non-tiled surface, tile() simply combines together the X and
490 * Y coordinates in the natural way:
492 * tile(untiled, X, Y, S) = A
493 * where A = Y * pitch + X'
495 * Y' = Y + S * qpitch
496 * detile(untiled, A) = (X, Y, S)
503 * (In these formulas, pitch is the number of bytes occupied by a single row
506 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
509 brw_blorp_blit_program(struct brw_context
*brw
,
510 const brw_blorp_blit_prog_key
*key
, bool debug_flag
);
512 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
514 brw_blorp_prog_data prog_data
;
518 void alloc_push_const_regs(int base_reg
);
519 void compute_frag_coords();
520 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
521 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
522 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
523 void translate_dst_to_src();
524 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
525 struct brw_reg clampX0
, struct brw_reg clampY0
,
526 struct brw_reg clampX1
, struct brw_reg clampY1
);
527 void single_to_blend();
528 void manual_blend_average(unsigned num_samples
);
529 void manual_blend_bilinear(unsigned num_samples
);
530 void sample(struct brw_reg dst
);
531 void texel_fetch(struct brw_reg dst
);
533 void texture_lookup(struct brw_reg dst
, enum opcode op
,
534 const sampler_message_arg
*args
, int num_args
);
535 void render_target_write();
538 * Base-2 logarithm of the maximum number of samples that can be blended.
540 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
542 struct brw_context
*brw
;
543 const brw_blorp_blit_prog_key
*key
;
545 /* Thread dispatch header */
548 /* Pixel X/Y coordinates (always in R1). */
552 struct brw_reg dst_x0
;
553 struct brw_reg dst_x1
;
554 struct brw_reg dst_y0
;
555 struct brw_reg dst_y1
;
556 /* Top right coordinates of the rectangular grid used for scaled blitting */
557 struct brw_reg rect_grid_x1
;
558 struct brw_reg rect_grid_y1
;
560 struct brw_reg multiplier
;
561 struct brw_reg offset
;
562 } x_transform
, y_transform
;
564 /* Data read from texture (4 vec16's per array element) */
565 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
567 /* Auxiliary storage for the contents of the MCS surface.
569 * Since the sampler always returns 8 registers worth of data, this is 8
570 * registers wide, even though we only use the first 2 registers of it.
572 struct brw_reg mcs_data
;
574 /* X coordinates. We have two of them so that we can perform coordinate
575 * transformations easily.
577 struct brw_reg x_coords
[2];
579 /* Y coordinates. We have two of them so that we can perform coordinate
580 * transformations easily.
582 struct brw_reg y_coords
[2];
584 /* X, Y coordinates of the pixel from which we need to fetch the specific
585 * sample. These are used for multisample scaled blitting.
587 struct brw_reg x_sample_coords
;
588 struct brw_reg y_sample_coords
;
590 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
591 struct brw_reg x_frac
;
592 struct brw_reg y_frac
;
594 /* Which element of x_coords and y_coords is currently in use.
598 /* True if, at the point in the program currently being compiled, the
599 * sample index is known to be zero.
603 /* Register storing the sample index when s_is_zero is false. */
604 struct brw_reg sample_index
;
610 /* MRF used for sampling and render target writes */
614 brw_blorp_blit_program::brw_blorp_blit_program(
615 struct brw_context
*brw
,
616 const brw_blorp_blit_prog_key
*key
,
618 : brw_blorp_eu_emitter(brw
, debug_flag
),
625 brw_blorp_blit_program::compile(struct brw_context
*brw
,
626 GLuint
*program_size
)
629 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
630 /* If the destination image is W tiled and multisampled, then the thread
631 * must be dispatched once per sample, not once per pixel. This is
632 * necessary because after conversion between W and Y tiling, there's no
633 * guarantee that all samples corresponding to a single pixel will still
636 assert(key
->persample_msaa_dispatch
);
640 /* We are blending, which means we won't have an opportunity to
641 * translate the tiling and sample count for the texture surface. So
642 * the surface state for the texture must be configured with the correct
643 * tiling and sample count.
645 assert(!key
->src_tiled_w
);
646 assert(key
->tex_samples
== key
->src_samples
);
647 assert(key
->tex_layout
== key
->src_layout
);
648 assert(key
->tex_samples
> 0);
651 if (key
->persample_msaa_dispatch
) {
652 /* It only makes sense to do persample dispatch if the render target is
653 * configured as multisampled.
655 assert(key
->rt_samples
> 0);
658 /* Make sure layout is consistent with sample count */
659 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
660 (key
->tex_samples
== 0));
661 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
662 (key
->rt_samples
== 0));
663 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
664 (key
->src_samples
== 0));
665 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
666 (key
->dst_samples
== 0));
668 /* Set up prog_data */
669 memset(&prog_data
, 0, sizeof(prog_data
));
670 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
673 compute_frag_coords();
675 /* Render target and texture hardware don't support W tiling. */
676 const bool rt_tiled_w
= false;
677 const bool tex_tiled_w
= false;
679 /* The address that data will be written to is determined by the
680 * coordinates supplied to the WM thread and the tiling and sample count of
681 * the render target, according to the formula:
683 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
685 * If the actual tiling and sample count of the destination surface are not
686 * the same as the configuration of the render target, then these
687 * coordinates are wrong and we have to adjust them to compensate for the
690 if (rt_tiled_w
!= key
->dst_tiled_w
||
691 key
->rt_samples
!= key
->dst_samples
||
692 key
->rt_layout
!= key
->dst_layout
) {
693 encode_msaa(key
->rt_samples
, key
->rt_layout
);
694 /* Now (X, Y, S) = detile(rt_tiling, offset) */
695 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
696 /* Now (X, Y, S) = detile(dst_tiling, offset) */
697 decode_msaa(key
->dst_samples
, key
->dst_layout
);
700 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
702 * That is: X, Y and S now contain the true coordinates and sample index of
703 * the data that the WM thread should output.
705 * If we need to kill pixels that are outside the destination rectangle,
706 * now is the time to do it.
710 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
711 y_coords
[xy_coord_index
],
712 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
714 /* Next, apply a translation to obtain coordinates in the source image. */
715 translate_dst_to_src();
717 /* If the source image is not multisampled, then we want to fetch sample
718 * number 0, because that's the only sample there is.
720 if (key
->src_samples
== 0)
723 /* X, Y, and S are now the coordinates of the pixel in the source image
724 * that we want to texture from. Exception: if we are blending, then S is
725 * irrelevant, because we are going to fetch all samples.
727 if (key
->blend
&& !key
->blit_scaled
) {
729 /* Gen6 hardware an automatically blend using the SAMPLE message */
731 sample(texture_data
[0]);
733 /* Gen7+ hardware doesn't automaticaly blend. */
734 manual_blend_average(key
->src_samples
);
736 } else if(key
->blend
&& key
->blit_scaled
) {
737 manual_blend_bilinear(key
->src_samples
);
739 /* We aren't blending, which means we just want to fetch a single sample
740 * from the source surface. The address that we want to fetch from is
741 * related to the X, Y and S values according to the formula:
743 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
745 * If the actual tiling and sample count of the source surface are not
746 * the same as the configuration of the texture, then we need to adjust
747 * the coordinates to compensate for the difference.
749 if ((tex_tiled_w
!= key
->src_tiled_w
||
750 key
->tex_samples
!= key
->src_samples
||
751 key
->tex_layout
!= key
->src_layout
) &&
752 !key
->bilinear_filter
) {
753 encode_msaa(key
->src_samples
, key
->src_layout
);
754 /* Now (X, Y, S) = detile(src_tiling, offset) */
755 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
756 /* Now (X, Y, S) = detile(tex_tiling, offset) */
757 decode_msaa(key
->tex_samples
, key
->tex_layout
);
760 if (key
->bilinear_filter
) {
761 sample(texture_data
[0]);
764 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
766 * In other words: X, Y, and S now contain values which, when passed to
767 * the texturing unit, will cause data to be read from the correct
768 * memory location. So we can fetch the texel now.
770 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
772 texel_fetch(texture_data
[0]);
776 /* Finally, write the fetched (or blended) value to the render target and
777 * terminate the thread.
779 render_target_write();
781 return get_program(program_size
);
785 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
787 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
788 #define ALLOC_REG(name, type) \
790 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
791 base_reg + CONST_LOC(name) / 32, \
792 (CONST_LOC(name) % 32) / 4), type)
794 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
795 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
796 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
797 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
798 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
799 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
800 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
801 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
802 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
803 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
809 brw_blorp_blit_program::alloc_regs()
812 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
813 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
814 prog_data
.first_curbe_grf
= reg
;
815 alloc_push_const_regs(reg
);
816 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
817 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
818 this->texture_data
[i
] =
819 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
823 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
825 for (int i
= 0; i
< 2; ++i
) {
827 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
830 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
834 if (key
->blit_scaled
&& key
->blend
) {
835 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
837 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
839 this->x_frac
= brw_vec8_grf(reg
, 0);
841 this->y_frac
= brw_vec8_grf(reg
, 0);
845 this->xy_coord_index
= 0;
847 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
849 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
851 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
854 /* Make sure we didn't run out of registers */
855 assert(reg
<= GEN7_MRF_HACK_START
);
858 this->base_mrf
= mrf
;
861 /* In the code that follows, X and Y can be used to quickly refer to the
862 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
863 * prime") to the inactive elements.
865 * S can be used to quickly refer to sample_index.
867 #define X x_coords[xy_coord_index]
868 #define Y y_coords[xy_coord_index]
869 #define Xp x_coords[!xy_coord_index]
870 #define Yp y_coords[!xy_coord_index]
871 #define S sample_index
873 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
874 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
876 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
879 * Emit code to compute the X and Y coordinates of the pixels being rendered
880 * by this WM invocation.
882 * Assuming the render target is set up for Y tiling, these (X, Y) values are
883 * related to the address offset where outputs will be written by the formula:
885 * (X, Y, S) = decode_msaa(detile(offset)).
887 * (See brw_blorp_blit_program).
890 brw_blorp_blit_program::compute_frag_coords()
892 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
893 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
894 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
895 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
897 * Pixels within a subspan are laid out in this arrangement:
901 * So, to compute the coordinates of each pixel, we need to read every 2nd
902 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
903 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
904 * In other words, the data we want to access is R1.4<2;4,0>UW.
906 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
907 * result, since pixels n+1 and n+3 are in the right half of the subspan.
909 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
910 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
912 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
913 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
914 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
917 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
918 * pixels n+2 and n+3 are in the bottom half of the subspan.
920 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
921 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
923 /* Move the coordinates to UD registers. */
924 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
925 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
928 if (key
->persample_msaa_dispatch
) {
929 switch (key
->rt_samples
) {
931 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
932 * Therefore, subspan 0 will represent sample 0, subspan 1 will
933 * represent sample 1, and so on.
935 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
936 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
937 * populate a temporary variable with the sequence (0, 1, 2, 3), and
938 * then copy from it using vstride=1, width=4, hstride=0.
940 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
941 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
942 /* Move to UD sample_index register. */
943 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
944 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
948 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
949 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
950 * subspan 1 will represent sample 1, and so on. We can find the
951 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
952 * Index") and multiplying by two (since samples are always delivered
953 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
956 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
957 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
958 * variable with the sequence (0, 1, 2, 3), and then reading from it
959 * using vstride=1, width=4, hstride=0.
961 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
962 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
963 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
964 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
965 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
966 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
967 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
968 stride(t2_uw1
, 1, 4, 0));
969 emit_add_8(offset(S
, 1),
970 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
971 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
975 unreachable("Unrecognized sample count in "
976 "brw_blorp_blit_program::compute_frag_coords()");
980 /* Either the destination surface is single-sampled, or the WM will be
981 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
982 * per pixel). In either case, it's not meaningful to compute a sample
983 * value. Just set it to 0.
990 * Emit code to compensate for the difference between Y and W tiling.
992 * This code modifies the X and Y coordinates according to the formula:
994 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
996 * (See brw_blorp_blit_program).
998 * It can only translate between W and Y tiling, so new_tiling and old_tiling
999 * are booleans where true represents W tiling and false represents Y tiling.
1002 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1004 if (old_tiled_w
== new_tiled_w
)
1007 /* In the code that follows, we can safely assume that S = 0, because W
1008 * tiling formats always use IMS layout.
1013 /* Given X and Y coordinates that describe an address using Y tiling,
1014 * translate to the X and Y coordinates that describe the same address
1017 * If we break down the low order bits of X and Y, using a
1018 * single letter to represent each low-order bit:
1020 * X = A << 7 | 0bBCDEFGH
1021 * Y = J << 5 | 0bKLMNP (1)
1023 * Then we can apply the Y tiling formula to see the memory offset being
1026 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1028 * If we apply the W detiling formula to this memory location, that the
1029 * corresponding X' and Y' coordinates are:
1031 * X' = A << 6 | 0bBCDPFH (3)
1032 * Y' = J << 6 | 0bKLMNEG
1034 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1035 * we need to make the following computation:
1037 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1038 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1040 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1041 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1042 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1043 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1044 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1045 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1046 emit_or(Xp
, t1
, t2
);
1047 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1048 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1049 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1050 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1051 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1052 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1053 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1054 emit_or(Yp
, t1
, t2
);
1057 /* Applying the same logic as above, but in reverse, we obtain the
1060 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1061 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1063 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1064 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1065 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1066 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1067 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1068 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1069 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1070 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1072 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1073 emit_or(Xp
, t1
, t2
);
1074 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1075 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1076 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1077 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1078 emit_or(Yp
, t1
, t2
);
1084 * Emit code to compensate for the difference between MSAA and non-MSAA
1087 * This code modifies the X and Y coordinates according to the formula:
1089 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1091 * (See brw_blorp_blit_program).
1094 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1095 intel_msaa_layout layout
)
1098 case INTEL_MSAA_LAYOUT_NONE
:
1099 /* No translation necessary, and S should already be zero. */
1102 case INTEL_MSAA_LAYOUT_CMS
:
1103 /* We can't compensate for compressed layout since at this point in the
1104 * program we haven't read from the MCS buffer.
1106 unreachable("Bad layout in encode_msaa");
1107 case INTEL_MSAA_LAYOUT_UMS
:
1108 /* No translation necessary. */
1110 case INTEL_MSAA_LAYOUT_IMS
:
1111 switch (num_samples
) {
1113 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1114 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1115 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1117 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1119 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1120 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1122 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1124 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1125 emit_or(Xp
, t1
, t2
);
1126 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1127 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1129 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1130 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1132 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1133 emit_or(Yp
, t1
, t2
);
1136 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1137 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1139 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1141 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1142 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1144 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1145 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1146 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1147 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1148 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1151 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1152 emit_or(Xp
, t1
, t2
);
1153 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1154 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1156 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1157 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1159 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1160 emit_or(Yp
, t1
, t2
);
1170 * Emit code to compensate for the difference between MSAA and non-MSAA
1173 * This code modifies the X and Y coordinates according to the formula:
1175 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1177 * (See brw_blorp_blit_program).
1180 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1181 intel_msaa_layout layout
)
1184 case INTEL_MSAA_LAYOUT_NONE
:
1185 /* No translation necessary, and S should already be zero. */
1188 case INTEL_MSAA_LAYOUT_CMS
:
1189 /* We can't compensate for compressed layout since at this point in the
1190 * program we don't have access to the MCS buffer.
1192 unreachable("Bad layout in encode_msaa");
1193 case INTEL_MSAA_LAYOUT_UMS
:
1194 /* No translation necessary. */
1196 case INTEL_MSAA_LAYOUT_IMS
:
1198 switch (num_samples
) {
1200 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1201 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1202 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1203 * S = (Y & 0b10) | (X & 0b10) >> 1
1205 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1206 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1207 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1208 emit_or(Xp
, t1
, t2
);
1209 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1210 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1211 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1212 emit_or(Yp
, t1
, t2
);
1213 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1214 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1215 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1219 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1220 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1221 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1222 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1224 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1225 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1226 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1227 emit_or(Xp
, t1
, t2
);
1228 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1229 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1230 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1231 emit_or(Yp
, t1
, t2
);
1232 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1233 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1234 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1235 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1236 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1247 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1251 brw_blorp_blit_program::translate_dst_to_src()
1253 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1254 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1255 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1256 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1258 /* Move the UD coordinates to float registers. */
1261 /* Scale and offset */
1262 emit_mad(X_f
, x_transform
.offset
, Xp_f
, x_transform
.multiplier
);
1263 emit_mad(Y_f
, y_transform
.offset
, Yp_f
, y_transform
.multiplier
);
1264 if (key
->blit_scaled
&& key
->blend
) {
1265 /* Translate coordinates to lay out the samples in a rectangular grid
1266 * roughly corresponding to sample locations.
1268 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1269 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1270 /* Adjust coordinates so that integers represent pixel centers rather
1273 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1274 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1276 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1277 * texels on texture edges.
1279 clamp_tex_coords(X_f
, Y_f
,
1280 brw_imm_f(0.0), brw_imm_f(0.0),
1281 rect_grid_x1
, rect_grid_y1
);
1283 /* Store the fractional parts to be used as bilinear interpolation
1286 emit_frc(x_frac
, X_f
);
1287 emit_frc(y_frac
, Y_f
);
1289 /* Round the float coordinates down to nearest integer */
1290 emit_rndd(Xp_f
, X_f
);
1291 emit_rndd(Yp_f
, Y_f
);
1292 emit_mul(X_f
, Xp_f
, brw_imm_f(1.0f
/ key
->x_scale
));
1293 emit_mul(Y_f
, Yp_f
, brw_imm_f(1.0f
/ key
->y_scale
));
1295 } else if (!key
->bilinear_filter
) {
1296 /* Round the float coordinates down to nearest integer by moving to
1306 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1307 struct brw_reg regY
,
1308 struct brw_reg clampX0
,
1309 struct brw_reg clampY0
,
1310 struct brw_reg clampX1
,
1311 struct brw_reg clampY1
)
1313 emit_max(regX
, regX
, clampX0
);
1314 emit_max(regY
, regY
, clampY0
);
1315 emit_min(regX
, regX
, clampX1
);
1316 emit_min(regY
, regY
, clampY1
);
1320 * Emit code to transform the X and Y coordinates as needed for blending
1321 * together the different samples in an MSAA texture.
1324 brw_blorp_blit_program::single_to_blend()
1326 /* When looking up samples in an MSAA texture using the SAMPLE message,
1327 * Gen6 requires the texture coordinates to be odd integers (so that they
1328 * correspond to the center of a 2x2 block representing the four samples
1329 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1330 * each by 2 and then add 1.
1332 emit_shl(t1
, X
, brw_imm_w(1));
1333 emit_shl(t2
, Y
, brw_imm_w(1));
1334 emit_add(Xp
, t1
, brw_imm_w(1));
1335 emit_add(Yp
, t2
, brw_imm_w(1));
1341 * Count the number of trailing 1 bits in the given value. For example:
1343 * count_trailing_one_bits(0) == 0
1344 * count_trailing_one_bits(7) == 3
1345 * count_trailing_one_bits(11) == 2
1347 inline int count_trailing_one_bits(unsigned value
)
1349 #ifdef HAVE___BUILTIN_CTZ
1350 return __builtin_ctz(~value
);
1352 return _mesa_bitcount(value
& ~(value
+ 1));
1358 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1360 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1363 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1365 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1367 * This ensures that when all samples have the same value, no numerical
1368 * precision is lost, since each addition operation always adds two equal
1369 * values, and summing two equal floating point values does not lose
1372 * We perform this computation by treating the texture_data array as a
1373 * stack and performing the following operations:
1375 * - push sample 0 onto stack
1376 * - push sample 1 onto stack
1377 * - add top two stack entries
1378 * - push sample 2 onto stack
1379 * - push sample 3 onto stack
1380 * - add top two stack entries
1381 * - add top two stack entries
1382 * - divide top stack entry by 4
1384 * Note that after pushing sample i onto the stack, the number of add
1385 * operations we do is equal to the number of trailing 1 bits in i. This
1386 * works provided the total number of samples is a power of two, which it
1387 * always is for i965.
1389 * For integer formats, we replace the add operations with average
1390 * operations and skip the final division.
1392 unsigned stack_depth
= 0;
1393 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1394 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1396 /* Push sample i onto the stack */
1397 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1402 emit_mov(vec16(S
), brw_imm_ud(i
));
1404 texel_fetch(texture_data
[stack_depth
++]);
1406 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1407 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1408 * suggests an optimization:
1410 * "A simple optimization with probable large return in
1411 * performance is to compare the MCS value to zero (indicating
1412 * all samples are on sample slice 0), and sample only from
1413 * sample slice 0 using ld2dss if MCS is zero."
1415 * Note that in the case where the MCS value is zero, sampling from
1416 * sample slice 0 using ld2dss and sampling from sample 0 using
1417 * ld2dms are equivalent (since all samples are on sample slice 0).
1418 * Since we have already sampled from sample 0, all we need to do is
1419 * skip the remaining fetches and averaging if MCS is zero.
1421 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1424 /* Do count_trailing_one_bits(i) times */
1425 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1426 assert(stack_depth
>= 2);
1429 /* TODO: should use a smaller loop bound for non_RGBA formats */
1430 for (int k
= 0; k
< 4; ++k
) {
1431 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1432 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1433 offset(texture_data
[stack_depth
- 1], 2*k
),
1434 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1435 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1440 /* We should have just 1 sample on the stack now. */
1441 assert(stack_depth
== 1);
1443 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1444 /* Scale the result down by a factor of num_samples */
1445 /* TODO: should use a smaller loop bound for non-RGBA formats */
1446 for (int j
= 0; j
< 4; ++j
) {
1447 emit_mul(offset(texture_data
[0], 2*j
),
1448 offset(vec8(texture_data
[0]), 2*j
),
1449 brw_imm_f(1.0f
/ num_samples
));
1453 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1458 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1460 /* We do this computation by performing the following operations:
1462 * In case of 4x, 8x MSAA:
1463 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1464 * which are later used for interpolation
1465 * - linearly interpolate samples a and b in X
1466 * - linearly interpolate samples c and d in X
1467 * - linearly interpolate the results of last two operations in Y
1469 * result = lrp(lrp(a + b) + lrp(c + d))
1471 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1472 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1473 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1474 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1476 for (unsigned i
= 0; i
< 4; ++i
) {
1477 assert(i
< ARRAY_SIZE(texture_data
));
1480 /* Compute pixel coordinates */
1481 emit_add(vec16(x_sample_coords
), Xp_f
,
1482 brw_imm_f((float)(i
& 0x1) * (1.0f
/ key
->x_scale
)));
1483 emit_add(vec16(y_sample_coords
), Yp_f
,
1484 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0f
/ key
->y_scale
)));
1485 emit_mov(vec16(X
), x_sample_coords
);
1486 emit_mov(vec16(Y
), y_sample_coords
);
1488 /* The MCS value we fetch has to match up with the pixel that we're
1489 * sampling from. Since we sample from different pixels in each
1490 * iteration of this "for" loop, the call to mcs_fetch() should be
1491 * here inside the loop after computing the pixel coordinates.
1493 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1496 /* Compute sample index and map the sample index to a sample number.
1497 * Sample index layout shows the numbering of slots in a rectangular
1498 * grid of samples with in a pixel. Sample number layout shows the
1499 * rectangular grid of samples roughly corresponding to the real sample
1500 * locations with in a pixel.
1501 * In case of 4x MSAA, layout of sample indices matches the layout of
1509 * In case of 8x MSAA the two layouts don't match.
1510 * sample index layout : --------- sample number layout : ---------
1511 * | 0 | 1 | | 5 | 2 |
1512 * --------- ---------
1513 * | 2 | 3 | | 4 | 6 |
1514 * --------- ---------
1515 * | 4 | 5 | | 0 | 3 |
1516 * --------- ---------
1517 * | 6 | 7 | | 7 | 1 |
1518 * --------- ---------
1520 emit_frc(vec16(t1_f
), x_sample_coords
);
1521 emit_frc(vec16(t2_f
), y_sample_coords
);
1522 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1523 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1524 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1525 emit_mov(vec16(S
), t1_f
);
1527 if (num_samples
== 8) {
1528 /* Map the sample index to a sample number */
1529 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1531 emit_mov(vec16(t2
), brw_imm_d(5));
1532 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1533 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1534 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1538 emit_mov(vec16(t2
), brw_imm_d(0));
1539 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1540 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1541 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1544 emit_mov(vec16(S
), t2
);
1546 texel_fetch(texture_data
[i
]);
1549 #define SAMPLE(x, y) offset(texture_data[x], y)
1550 for (int index
= 3; index
> 0; ) {
1551 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1552 * Counter value of 8 in 'for' loop below is used to interpolate all
1553 * the color components.
1555 for (int k
= 0; k
< 8; k
+= 2)
1556 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1558 vec8(SAMPLE(index
, k
)),
1559 vec8(SAMPLE(index
- 1, k
)));
1562 for (int k
= 0; k
< 8; k
+= 2)
1563 emit_lrp(vec8(SAMPLE(0, k
)),
1566 vec8(SAMPLE(0, k
)));
1571 * Emit code to look up a value in the texture using the SAMPLE message (which
1572 * does blending of MSAA surfaces).
1575 brw_blorp_blit_program::sample(struct brw_reg dst
)
1577 static const sampler_message_arg args
[2] = {
1578 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1579 SAMPLER_MESSAGE_ARG_V_FLOAT
1582 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1586 * Emit code to look up a value in the texture using the SAMPLE_LD message
1587 * (which does a simple texel fetch).
1590 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1592 static const sampler_message_arg gen6_args
[5] = {
1593 SAMPLER_MESSAGE_ARG_U_INT
,
1594 SAMPLER_MESSAGE_ARG_V_INT
,
1595 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1596 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1597 SAMPLER_MESSAGE_ARG_SI_INT
1599 static const sampler_message_arg gen7_ld_args
[3] = {
1600 SAMPLER_MESSAGE_ARG_U_INT
,
1601 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1602 SAMPLER_MESSAGE_ARG_V_INT
1604 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1605 SAMPLER_MESSAGE_ARG_SI_INT
,
1606 SAMPLER_MESSAGE_ARG_U_INT
,
1607 SAMPLER_MESSAGE_ARG_V_INT
1609 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1610 SAMPLER_MESSAGE_ARG_SI_INT
,
1611 SAMPLER_MESSAGE_ARG_MCS_INT
,
1612 SAMPLER_MESSAGE_ARG_U_INT
,
1613 SAMPLER_MESSAGE_ARG_V_INT
1618 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1621 switch (key
->tex_layout
) {
1622 case INTEL_MSAA_LAYOUT_IMS
:
1623 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1626 * If this field is MSFMT_DEPTH_STENCIL
1627 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1628 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1630 * So fall through to emit the same message as we use for
1631 * INTEL_MSAA_LAYOUT_CMS.
1633 case INTEL_MSAA_LAYOUT_CMS
:
1634 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1635 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1637 case INTEL_MSAA_LAYOUT_UMS
:
1638 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1639 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1641 case INTEL_MSAA_LAYOUT_NONE
:
1643 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1644 ARRAY_SIZE(gen7_ld_args
));
1649 unreachable("Should not get here.");
1654 brw_blorp_blit_program::mcs_fetch()
1656 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1657 SAMPLER_MESSAGE_ARG_U_INT
,
1658 SAMPLER_MESSAGE_ARG_V_INT
1660 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1661 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1665 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1667 const sampler_message_arg
*args
,
1670 struct brw_reg mrf
=
1671 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1672 for (int arg
= 0; arg
< num_args
; ++arg
) {
1673 switch (args
[arg
]) {
1674 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1675 if (key
->bilinear_filter
)
1676 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1677 retype(X
, BRW_REGISTER_TYPE_F
));
1679 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1681 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1682 if (key
->bilinear_filter
)
1683 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1684 retype(Y
, BRW_REGISTER_TYPE_F
));
1686 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1688 case SAMPLER_MESSAGE_ARG_U_INT
:
1691 case SAMPLER_MESSAGE_ARG_V_INT
:
1694 case SAMPLER_MESSAGE_ARG_SI_INT
:
1695 /* Note: on Gen7, this code may be reached with s_is_zero==true
1696 * because in Gen7's ld2dss message, the sample index is the first
1697 * argument. When this happens, we need to move a 0 into the
1698 * appropriate message register.
1701 emit_mov(mrf
, brw_imm_ud(0));
1705 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1706 switch (key
->tex_layout
) {
1707 case INTEL_MSAA_LAYOUT_CMS
:
1708 emit_mov(mrf
, mcs_data
);
1710 case INTEL_MSAA_LAYOUT_IMS
:
1711 /* When sampling from an IMS surface, MCS data is not relevant,
1712 * and the hardware ignores it. So don't bother populating it.
1716 /* We shouldn't be trying to send MCS data with any other
1719 assert (!"Unsupported layout for MCS data");
1723 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1724 emit_mov(mrf
, brw_imm_ud(0));
1730 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1733 mrf
.nr
- base_mrf
/* msg_length */);
1741 #undef SWAP_XY_AND_XPYP
1744 brw_blorp_blit_program::render_target_write()
1746 struct brw_reg mrf_rt_write
=
1747 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1750 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1751 * so that the render target knows which pixels we killed.
1753 bool use_header
= key
->use_kill
;
1755 /* Copy R0/1 to MRF */
1756 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1757 retype(R0
, BRW_REGISTER_TYPE_UD
));
1761 /* Copy texture data to MRFs */
1762 for (int i
= 0; i
< 4; ++i
) {
1763 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1764 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1765 offset(vec8(texture_data
[0]), 2*i
));
1769 /* Now write to the render target and terminate the thread */
1770 emit_render_target_write(
1773 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1779 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1780 GLfloat dst0
, GLfloat dst1
,
1783 float scale
= (src1
- src0
) / (dst1
- dst0
);
1785 /* When not mirroring a coordinate (say, X), we need:
1786 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1788 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1790 * blorp program uses "round toward zero" to convert the
1791 * transformed floating point coordinates to integer coordinates,
1792 * whereas the behaviour we actually want is "round to nearest",
1793 * so 0.5 provides the necessary correction.
1796 offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
1798 /* When mirroring X we need:
1799 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1801 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1803 multiplier
= -scale
;
1804 offset
= src0
+ (dst1
- 0.5f
) * scale
;
1810 * Determine which MSAA layout the GPU pipeline should be configured for,
1811 * based on the chip generation, the number of samples, and the true layout of
1812 * the image in memory.
1814 inline intel_msaa_layout
1815 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1816 intel_msaa_layout true_layout
)
1818 if (num_samples
<= 1) {
1819 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1820 * format buffers, by transforming coordinates appropriately.
1822 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1823 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1824 return INTEL_MSAA_LAYOUT_NONE
;
1826 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1829 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1830 if (brw
->gen
== 6) {
1831 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1838 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*src_mt
,
1840 unsigned src_level
, unsigned src_layer
,
1841 mesa_format src_format
,
1842 struct intel_mipmap_tree
*dst_mt
,
1843 unsigned dst_level
, unsigned dst_layer
,
1844 mesa_format dst_format
,
1845 GLfloat src_x0
, GLfloat src_y0
,
1846 GLfloat src_x1
, GLfloat src_y1
,
1847 GLfloat dst_x0
, GLfloat dst_y0
,
1848 GLfloat dst_x1
, GLfloat dst_y1
,
1850 bool mirror_x
, bool mirror_y
)
1852 src
.set(brw
, src_mt
, src_level
, src_layer
, src_format
, false);
1853 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, dst_format
, true);
1855 /* Even though we do multisample resolves at the time of the blit, OpenGL
1856 * specification defines them as if they happen at the time of rendering,
1857 * which means that the type of averaging we do during the resolve should
1858 * only depend on the source format; the destination format should be
1859 * ignored. But, specification doesn't seem to be strict about it.
1861 * It has been observed that mulitisample resolves produce slightly better
1862 * looking images when averaging is done using destination format. NVIDIA's
1863 * proprietary OpenGL driver also follow this approach. So, we choose to
1864 * follow it in our driver.
1866 * When multisampling, if the source and destination formats are equal
1867 * (aside from the color space), we choose to blit in sRGB space to get
1868 * this higher quality image.
1870 if (src
.num_samples
> 1 &&
1871 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1872 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1873 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1874 assert(brw
->format_supported_as_render_target
[dst_mt
->format
]);
1875 dst
.brw_surfaceformat
= brw
->render_target_format
[dst_mt
->format
];
1876 src
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1879 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1880 * texture, the above code configures the source format for L32_FLOAT or
1881 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1882 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1883 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1884 * around the problem by using a source format of R32_FLOAT. This
1885 * shouldn't affect rendering correctness, since the destination format is
1886 * R32_FLOAT, so only the contents of the red channel matters.
1888 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1889 src_mt
->format
== dst_mt
->format
&&
1890 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1891 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1895 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1897 /* texture_data_type indicates the register type that should be used to
1898 * manipulate texture data.
1900 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1901 case GL_UNSIGNED_NORMALIZED
:
1902 case GL_SIGNED_NORMALIZED
:
1904 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1906 case GL_UNSIGNED_INT
:
1907 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1908 /* We process stencil as though it's an unsigned normalized color */
1909 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1911 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1915 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1918 unreachable("Unrecognized blorp format");
1922 /* Gen7's rendering hardware only supports the IMS layout for depth and
1923 * stencil render targets. Blorp always maps its destination surface as
1924 * a color render target (even if it's actually a depth or stencil
1925 * buffer). So if the destination is IMS, we'll have to map it as a
1926 * single-sampled texture and interleave the samples ourselves.
1928 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1929 dst
.num_samples
= 0;
1932 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1933 /* If the destination surface is a W-tiled multisampled stencil buffer
1934 * that we're mapping as Y tiled, then we need to arrange for the WM
1935 * program to run once per sample rather than once per pixel, because
1936 * the memory layout of related samples doesn't match between W and Y
1939 wm_prog_key
.persample_msaa_dispatch
= true;
1942 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1943 /* We are blitting from a multisample buffer to a multisample buffer, so
1944 * we must preserve samples within a pixel. This means we have to
1945 * arrange for the WM program to run once per sample rather than once
1948 wm_prog_key
.persample_msaa_dispatch
= true;
1951 /* Scaled blitting or not. */
1952 wm_prog_key
.blit_scaled
=
1953 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1954 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1956 /* Scaling factors used for bilinear filtering in multisample scaled
1959 wm_prog_key
.x_scale
= 2.0f
;
1960 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0f
;
1962 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
1963 wm_prog_key
.bilinear_filter
= true;
1965 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1966 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1967 base_format
!= GL_STENCIL_INDEX
&&
1968 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1969 /* We are downsampling a color buffer, so blend. */
1970 wm_prog_key
.blend
= true;
1973 /* src_samples and dst_samples are the true sample counts */
1974 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1975 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1977 /* tex_samples and rt_samples are the sample counts that are set up in
1980 wm_prog_key
.tex_samples
= src
.num_samples
;
1981 wm_prog_key
.rt_samples
= dst
.num_samples
;
1983 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1984 * use to access the source and destination surfaces.
1986 wm_prog_key
.tex_layout
=
1987 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1988 wm_prog_key
.rt_layout
=
1989 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1991 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1994 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1995 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1997 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1998 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1999 /* Round floating point values to nearest integer to avoid "off by one texel"
2000 * kind of errors when blitting.
2002 x0
= wm_push_consts
.dst_x0
= roundf(dst_x0
);
2003 y0
= wm_push_consts
.dst_y0
= roundf(dst_y0
);
2004 x1
= wm_push_consts
.dst_x1
= roundf(dst_x1
);
2005 y1
= wm_push_consts
.dst_y1
= roundf(dst_y1
);
2006 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
2007 wm_prog_key
.x_scale
- 1.0f
);
2008 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
2009 wm_prog_key
.y_scale
- 1.0f
);
2011 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2012 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2014 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2015 /* We must expand the rectangle we send through the rendering pipeline,
2016 * to account for the fact that we are mapping the destination region as
2017 * single-sampled when it is in fact multisampled. We must also align
2018 * it to a multiple of the multisampling pattern, because the
2019 * differences between multisampled and single-sampled surface formats
2020 * will mean that pixels are scrambled within the multisampling pattern.
2021 * TODO: what if this makes the coordinates too large?
2023 * Note: this only works if the destination surface uses the IMS layout.
2024 * If it's UMS, then we have no choice but to set up the rendering
2025 * pipeline as multisampled.
2027 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2028 switch (dst_mt
->num_samples
) {
2030 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2031 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2032 x1
= ALIGN(x1
* 2, 4);
2033 y1
= ALIGN(y1
* 2, 4);
2036 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2037 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2038 x1
= ALIGN(x1
* 4, 8);
2039 y1
= ALIGN(y1
* 2, 4);
2042 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2044 wm_prog_key
.use_kill
= true;
2047 if (dst
.map_stencil_as_y_tiled
) {
2048 /* We must modify the rectangle we send through the rendering pipeline
2049 * (and the size and x/y offset of the destination surface), to account
2050 * for the fact that we are mapping it as Y-tiled when it is in fact
2053 * Both Y tiling and W tiling can be understood as organizations of
2054 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2055 * is different, but the layout of the 32-byte sub-tiles within the 4k
2056 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2057 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2058 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2060 * Therefore, to account for the layout differences within the 32-byte
2061 * sub-tiles, we must expand the rectangle so the X coordinates of its
2062 * edges are multiples of 8 (the W sub-tile width), and its Y
2063 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2064 * Then we need to scale the X and Y coordinates of the rectangle to
2065 * account for the differences in aspect ratio between the Y and W
2066 * sub-tiles. We need to modify the layer width and height similarly.
2068 * A correction needs to be applied when MSAA is in use: since
2069 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2070 * we need to align the Y coordinates to multiples of 8, so that when
2071 * they are divided by two they are still multiples of 4.
2073 * Note: Since the x/y offset of the surface will be applied using the
2074 * SURFACE_STATE command packet, it will be invisible to the swizzling
2075 * code in the shader; therefore it needs to be in a multiple of the
2076 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2077 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2078 * buffer), and the miplevel alignment used for stencil buffers is 8
2079 * pixels horizontally and either 4 or 8 pixels vertically (see
2080 * intel_horizontal_texture_alignment_unit() and
2081 * intel_vertical_texture_alignment_unit()).
2083 * Note: Also, since the SURFACE_STATE command packet can only apply
2084 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2085 * vertically, it is important that the offsets will be multiples of
2086 * these sizes after they are converted into Y-tiled coordinates.
2087 * Fortunately they will be, since we know from above that the offsets
2088 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2089 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2091 * TODO: what if this makes the coordinates (or the texture size) too
2094 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2095 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2096 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2097 x1
= ALIGN(x1
, x_align
) * 2;
2098 y1
= ALIGN(y1
, y_align
) / 2;
2099 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2100 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2103 wm_prog_key
.use_kill
= true;
2106 if (src
.map_stencil_as_y_tiled
) {
2107 /* We must modify the size and x/y offset of the source surface to
2108 * account for the fact that we are mapping it as Y-tiled when it is in
2111 * See the comments above concerning x/y offset alignment for the
2112 * destination surface.
2114 * TODO: what if this makes the texture size too large?
2116 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2117 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2118 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2125 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2126 brw_blorp_prog_data
**prog_data
) const
2128 uint32_t prog_offset
= 0;
2129 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_BLIT_PROG
,
2130 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2131 &prog_offset
, prog_data
)) {
2132 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
,
2133 INTEL_DEBUG
& DEBUG_BLORP
);
2134 GLuint program_size
;
2135 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2136 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_BLIT_PROG
,
2137 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2138 program
, program_size
,
2139 &prog
.prog_data
, sizeof(prog
.prog_data
),
2140 &prog_offset
, prog_data
);