2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
37 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 * Helper function for handling mirror image blits.
42 * If coord0 > coord1, swap them and invert the "mirror" boolean.
45 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
47 if (coord0
> coord1
) {
57 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
58 * destination coordinates.
60 * Return true if there is still blitting to do, false if all pixels got
61 * rejected by the clip and/or scissor.
63 * For clarity, the nomenclature of this function assumes we are clipping and
64 * scissoring the X coordinate; the exact same logic applies for Y
67 * Note: this function may also be used to account for clipping of source
68 * coordinates, by swapping the roles of src and dst.
71 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
72 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
74 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
75 /* If we are going to scissor everything away, stop. */
76 if (!(fb_xmin
< fb_xmax
&&
83 /* Clip the destination rectangle, and keep track of how many pixels we
84 * clipped off of the left and right sides of it.
86 GLint pixels_clipped_left
= 0;
87 GLint pixels_clipped_right
= 0;
88 if (dst_x0
< fb_xmin
) {
89 pixels_clipped_left
= fb_xmin
- dst_x0
;
92 if (fb_xmax
< dst_x1
) {
93 pixels_clipped_right
= dst_x1
- fb_xmax
;
97 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
98 * the source coordinates, we need to flip them to account for the
102 GLint tmp
= pixels_clipped_left
;
103 pixels_clipped_left
= pixels_clipped_right
;
104 pixels_clipped_right
= tmp
;
107 /* Adjust the source rectangle to remove the pixels corresponding to those
108 * that were clipped/scissored out of the destination rectangle.
110 src_x0
+= pixels_clipped_left
* scale
;
111 src_x1
-= pixels_clipped_right
* scale
;
117 static struct intel_mipmap_tree
*
118 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
120 struct intel_mipmap_tree
*mt
= irb
->mt
;
121 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
128 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
129 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
130 * the physical layer holding sample 0. So, for example, if
131 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
135 brw_blorp_blit_miptrees(struct brw_context
*brw
,
136 struct intel_mipmap_tree
*src_mt
,
137 unsigned src_level
, unsigned src_layer
,
138 struct intel_mipmap_tree
*dst_mt
,
139 unsigned dst_level
, unsigned dst_layer
,
140 float src_x0
, float src_y0
,
141 float src_x1
, float src_y1
,
142 float dst_x0
, float dst_y0
,
143 float dst_x1
, float dst_y1
,
144 GLenum filter
, bool mirror_x
, bool mirror_y
)
146 /* Get ready to blit. This includes depth resolving the src and dst
147 * buffers if necessary. Note: it's not necessary to do a color resolve on
148 * the destination buffer because we use the standard render path to render
149 * to destination color buffers, and the standard render path is
152 intel_miptree_resolve_color(brw
, src_mt
);
153 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
154 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
156 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
157 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
159 _mesa_get_format_name(src_mt
->format
), src_mt
,
160 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
161 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
162 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
165 brw_blorp_blit_params
params(brw
,
166 src_mt
, src_level
, src_layer
,
167 dst_mt
, dst_level
, dst_layer
,
172 filter
, mirror_x
, mirror_y
);
173 brw_blorp_exec(brw
, ¶ms
);
175 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
179 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
180 struct intel_renderbuffer
*src_irb
,
181 struct intel_renderbuffer
*dst_irb
,
182 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
183 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
184 GLenum filter
, bool mirror_x
, bool mirror_y
)
186 /* Find source/dst miptrees */
187 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
188 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
191 brw_blorp_blit_miptrees(brw
,
192 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
193 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
194 srcX0
, srcY0
, srcX1
, srcY1
,
195 dstX0
, dstY0
, dstX1
, dstY1
,
196 filter
, mirror_x
, mirror_y
);
198 intel_renderbuffer_set_needs_downsample(dst_irb
);
202 color_formats_match(gl_format src_format
, gl_format dst_format
)
204 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
205 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
207 /* Normally, we require the formats to be equal. However, we also support
208 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
209 * (overriding alpha to 1.0 via blending).
211 return linear_src_format
== linear_dst_format
||
212 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
213 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
214 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
215 linear_dst_format
== MESA_FORMAT_XRGB8888
);
219 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
220 struct intel_renderbuffer
*dst_irb
)
222 /* Note: don't just check gl_renderbuffer::Format, because in some cases
223 * multiple gl_formats resolve to the same native type in the miptree (for
224 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
225 * between those formats.
227 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
228 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
230 return color_formats_match(src_format
, dst_format
);
234 try_blorp_blit(struct brw_context
*brw
,
235 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
236 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
237 GLenum filter
, GLbitfield buffer_bit
)
239 struct gl_context
*ctx
= &brw
->ctx
;
241 /* Sync up the state of window system buffers. We need to do this before
242 * we go looking for the buffers.
244 intel_prepare_render(brw
);
246 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
247 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
249 /* Detect if the blit needs to be mirrored */
250 bool mirror_x
= false, mirror_y
= false;
251 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
252 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
253 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
254 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
256 /* If the destination rectangle needs to be clipped or scissored, do so.
258 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
259 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
260 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
261 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
262 /* Everything got clipped/scissored away, so the blit was successful. */
266 /* If the source rectangle needs to be clipped or scissored, do so. */
267 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
268 0, read_fb
->Width
) &&
269 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
270 0, read_fb
->Height
))) {
271 /* Everything got clipped/scissored away, so the blit was successful. */
275 /* Account for the fact that in the system framebuffer, the origin is at
278 if (_mesa_is_winsys_fbo(read_fb
)) {
279 GLint tmp
= read_fb
->Height
- srcY0
;
280 srcY0
= read_fb
->Height
- srcY1
;
282 mirror_y
= !mirror_y
;
284 if (_mesa_is_winsys_fbo(draw_fb
)) {
285 GLint tmp
= draw_fb
->Height
- dstY0
;
286 dstY0
= draw_fb
->Height
- dstY1
;
288 mirror_y
= !mirror_y
;
292 struct intel_renderbuffer
*src_irb
;
293 struct intel_renderbuffer
*dst_irb
;
294 switch (buffer_bit
) {
295 case GL_COLOR_BUFFER_BIT
:
296 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
297 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
298 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
299 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
302 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
303 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
305 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
306 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
307 filter
, mirror_x
, mirror_y
);
310 case GL_DEPTH_BUFFER_BIT
:
312 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
314 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
315 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
317 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
318 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
319 filter
, mirror_x
, mirror_y
);
321 case GL_STENCIL_BUFFER_BIT
:
323 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
325 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
326 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
328 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
329 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
330 filter
, mirror_x
, mirror_y
);
340 brw_blorp_copytexsubimage(struct brw_context
*brw
,
341 struct gl_renderbuffer
*src_rb
,
342 struct gl_texture_image
*dst_image
,
344 int srcX0
, int srcY0
,
345 int dstX0
, int dstY0
,
346 int width
, int height
)
348 struct gl_context
*ctx
= &brw
->ctx
;
349 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
350 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
352 /* Sync up the state of window system buffers. We need to do this before
353 * we go looking at the src renderbuffer's miptree.
355 intel_prepare_render(brw
);
357 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
358 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
360 /* BLORP is not supported before Gen6. */
361 if (brw
->gen
< 6 || brw
->gen
>= 8)
364 if (_mesa_get_format_base_format(src_mt
->format
) !=
365 _mesa_get_format_base_format(dst_mt
->format
)) {
369 /* We can't handle format conversions between Z24 and other formats since
370 * we have to lie about the surface format. See the comments in
371 * brw_blorp_surface_info::set().
373 if ((src_mt
->format
== MESA_FORMAT_X8_Z24
) !=
374 (dst_mt
->format
== MESA_FORMAT_X8_Z24
)) {
378 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
381 /* Source clipping shouldn't be necessary, since copytexsubimage (in
382 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
385 * Destination clipping shouldn't be necessary since the restrictions on
386 * glCopyTexSubImage prevent the user from specifying a destination rectangle
387 * that falls outside the bounds of the destination texture.
388 * See error_check_subtexture_dimensions().
391 int srcY1
= srcY0
+ height
;
392 int srcX1
= srcX0
+ width
;
393 int dstX1
= dstX0
+ width
;
394 int dstY1
= dstY0
+ height
;
396 /* Account for the fact that in the system framebuffer, the origin is at
399 bool mirror_y
= false;
400 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
401 GLint tmp
= src_rb
->Height
- srcY0
;
402 srcY0
= src_rb
->Height
- srcY1
;
407 brw_blorp_blit_miptrees(brw
,
408 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
409 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
410 srcX0
, srcY0
, srcX1
, srcY1
,
411 dstX0
, dstY0
, dstX1
, dstY1
,
412 GL_NEAREST
, false, mirror_y
);
414 /* If we're copying to a packed depth stencil texture and the source
415 * framebuffer has separate stencil, we need to also copy the stencil data
418 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
419 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
421 src_irb
= intel_renderbuffer(src_rb
);
422 src_mt
= src_irb
->mt
;
424 if (src_mt
->stencil_mt
)
425 src_mt
= src_mt
->stencil_mt
;
426 if (dst_mt
->stencil_mt
)
427 dst_mt
= dst_mt
->stencil_mt
;
429 if (src_mt
!= dst_mt
) {
430 brw_blorp_blit_miptrees(brw
,
431 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
432 dst_mt
, dst_image
->Level
,
433 dst_image
->Face
+ slice
,
434 srcX0
, srcY0
, srcX1
, srcY1
,
435 dstX0
, dstY0
, dstX1
, dstY1
,
436 GL_NEAREST
, false, mirror_y
);
445 brw_blorp_framebuffer(struct brw_context
*brw
,
446 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
447 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
448 GLbitfield mask
, GLenum filter
)
450 /* BLORP is not supported before Gen6. */
451 if (brw
->gen
< 6 || brw
->gen
>= 8)
454 static GLbitfield buffer_bits
[] = {
457 GL_STENCIL_BUFFER_BIT
,
460 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
461 if ((mask
& buffer_bits
[i
]) &&
463 srcX0
, srcY0
, srcX1
, srcY1
,
464 dstX0
, dstY0
, dstX1
, dstY1
,
465 filter
, buffer_bits
[i
])) {
466 mask
&= ~buffer_bits
[i
];
475 * Enum to specify the order of arguments in a sampler message
477 enum sampler_message_arg
479 SAMPLER_MESSAGE_ARG_U_FLOAT
,
480 SAMPLER_MESSAGE_ARG_V_FLOAT
,
481 SAMPLER_MESSAGE_ARG_U_INT
,
482 SAMPLER_MESSAGE_ARG_V_INT
,
483 SAMPLER_MESSAGE_ARG_SI_INT
,
484 SAMPLER_MESSAGE_ARG_MCS_INT
,
485 SAMPLER_MESSAGE_ARG_ZERO_INT
,
489 * Generator for WM programs used in BLORP blits.
491 * The bulk of the work done by the WM program is to wrap and unwrap the
492 * coordinate transformations used by the hardware to store surfaces in
493 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
494 * sample index for a multisampled surface) to a memory offset by the
495 * following formulas:
497 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
498 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
500 * For a single-sampled surface, or for a multisampled surface using
501 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
504 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
505 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
506 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
507 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
509 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
510 * embeds the sample number into bit 1 of the X and Y coordinates:
512 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
513 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
514 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
515 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
516 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
517 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
518 * S = (Y & 0b10) | (X & 0b10) >> 1
520 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
521 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
524 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
525 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
526 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
527 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
528 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
529 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
530 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
532 * For X tiling, tile() combines together the low-order bits of the X and Y
533 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
534 * bytes wide and 8 rows high:
536 * tile(x_tiled, X, Y, S) = A
537 * where A = tile_num << 12 | offset
538 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
539 * offset = (Y' & 0b111) << 9
540 * | (X & 0b111111111)
542 * Y' = Y + S * qpitch
543 * detile(x_tiled, A) = (X, Y, S)
547 * Y' = (tile_num / tile_pitch) << 3
548 * | (A & 0b111000000000) >> 9
549 * X' = (tile_num % tile_pitch) << 9
550 * | (A & 0b111111111)
552 * (In all tiling formulas, cpp is the number of bytes occupied by a single
553 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
554 * to fill the width of the surface, and qpitch is the spacing (in rows)
555 * between array slices).
557 * For Y tiling, tile() combines together the low-order bits of the X and Y
558 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
559 * bytes wide and 32 rows high:
561 * tile(y_tiled, X, Y, S) = A
562 * where A = tile_num << 12 | offset
563 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
564 * offset = (X' & 0b1110000) << 5
565 * | (Y' & 0b11111) << 4
568 * Y' = Y + S * qpitch
569 * detile(y_tiled, A) = (X, Y, S)
573 * Y' = (tile_num / tile_pitch) << 5
574 * | (A & 0b111110000) >> 4
575 * X' = (tile_num % tile_pitch) << 7
576 * | (A & 0b111000000000) >> 5
579 * For W tiling, tile() combines together the low-order bits of the X and Y
580 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
581 * bytes wide and 64 rows high (note that W tiling is only used for stencil
582 * buffers, which always have cpp = 1 and S=0):
584 * tile(w_tiled, X, Y, S) = A
585 * where A = tile_num << 12 | offset
586 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
587 * offset = (X' & 0b111000) << 6
588 * | (Y' & 0b111100) << 3
589 * | (X' & 0b100) << 2
595 * Y' = Y + S * qpitch
596 * detile(w_tiled, A) = (X, Y, S)
597 * where X = X' / cpp = X'
598 * Y = Y' % qpitch = Y'
600 * Y' = (tile_num / tile_pitch) << 6
601 * | (A & 0b111100000) >> 3
602 * | (A & 0b1000) >> 2
604 * X' = (tile_num % tile_pitch) << 6
605 * | (A & 0b111000000000) >> 6
606 * | (A & 0b10000) >> 2
610 * Finally, for a non-tiled surface, tile() simply combines together the X and
611 * Y coordinates in the natural way:
613 * tile(untiled, X, Y, S) = A
614 * where A = Y * pitch + X'
616 * Y' = Y + S * qpitch
617 * detile(untiled, A) = (X, Y, S)
624 * (In these formulas, pitch is the number of bytes occupied by a single row
627 class brw_blorp_blit_program
630 brw_blorp_blit_program(struct brw_context
*brw
,
631 const brw_blorp_blit_prog_key
*key
);
632 ~brw_blorp_blit_program();
634 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
,
635 FILE *dump_file
= stdout
);
637 brw_blorp_prog_data prog_data
;
641 void alloc_push_const_regs(int base_reg
);
642 void compute_frag_coords();
643 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
644 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
645 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
646 void kill_if_outside_dst_rect();
647 void translate_dst_to_src();
648 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
649 struct brw_reg clampX0
, struct brw_reg clampY0
,
650 struct brw_reg clampX1
, struct brw_reg clampY1
);
651 void single_to_blend();
652 void manual_blend_average(unsigned num_samples
);
653 void manual_blend_bilinear(unsigned num_samples
);
654 void sample(struct brw_reg dst
);
655 void texel_fetch(struct brw_reg dst
);
657 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
658 const sampler_message_arg
*args
, int num_args
);
659 void render_target_write();
662 * Base-2 logarithm of the maximum number of samples that can be blended.
664 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
667 struct brw_context
*brw
;
668 const brw_blorp_blit_prog_key
*key
;
669 struct brw_compile func
;
671 /* Thread dispatch header */
674 /* Pixel X/Y coordinates (always in R1). */
678 struct brw_reg dst_x0
;
679 struct brw_reg dst_x1
;
680 struct brw_reg dst_y0
;
681 struct brw_reg dst_y1
;
682 /* Top right coordinates of the rectangular grid used for scaled blitting */
683 struct brw_reg rect_grid_x1
;
684 struct brw_reg rect_grid_y1
;
686 struct brw_reg multiplier
;
687 struct brw_reg offset
;
688 } x_transform
, y_transform
;
690 /* Data read from texture (4 vec16's per array element) */
691 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
693 /* Auxiliary storage for the contents of the MCS surface.
695 * Since the sampler always returns 8 registers worth of data, this is 8
696 * registers wide, even though we only use the first 2 registers of it.
698 struct brw_reg mcs_data
;
700 /* X coordinates. We have two of them so that we can perform coordinate
701 * transformations easily.
703 struct brw_reg x_coords
[2];
705 /* Y coordinates. We have two of them so that we can perform coordinate
706 * transformations easily.
708 struct brw_reg y_coords
[2];
710 /* X, Y coordinates of the pixel from which we need to fetch the specific
711 * sample. These are used for multisample scaled blitting.
713 struct brw_reg x_sample_coords
;
714 struct brw_reg y_sample_coords
;
716 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
717 struct brw_reg x_frac
;
718 struct brw_reg y_frac
;
720 /* Which element of x_coords and y_coords is currently in use.
724 /* True if, at the point in the program currently being compiled, the
725 * sample index is known to be zero.
729 /* Register storing the sample index when s_is_zero is false. */
730 struct brw_reg sample_index
;
736 /* MRF used for sampling and render target writes */
740 brw_blorp_blit_program::brw_blorp_blit_program(
741 struct brw_context
*brw
,
742 const brw_blorp_blit_prog_key
*key
)
743 : mem_ctx(ralloc_context(NULL
)),
747 brw_init_compile(brw
, &func
, mem_ctx
);
750 brw_blorp_blit_program::~brw_blorp_blit_program()
752 ralloc_free(mem_ctx
);
756 brw_blorp_blit_program::compile(struct brw_context
*brw
,
757 GLuint
*program_size
,
761 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
762 /* If the destination image is W tiled and multisampled, then the thread
763 * must be dispatched once per sample, not once per pixel. This is
764 * necessary because after conversion between W and Y tiling, there's no
765 * guarantee that all samples corresponding to a single pixel will still
768 assert(key
->persample_msaa_dispatch
);
772 /* We are blending, which means we won't have an opportunity to
773 * translate the tiling and sample count for the texture surface. So
774 * the surface state for the texture must be configured with the correct
775 * tiling and sample count.
777 assert(!key
->src_tiled_w
);
778 assert(key
->tex_samples
== key
->src_samples
);
779 assert(key
->tex_layout
== key
->src_layout
);
780 assert(key
->tex_samples
> 0);
783 if (key
->persample_msaa_dispatch
) {
784 /* It only makes sense to do persample dispatch if the render target is
785 * configured as multisampled.
787 assert(key
->rt_samples
> 0);
790 /* Make sure layout is consistent with sample count */
791 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
792 (key
->tex_samples
== 0));
793 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
794 (key
->rt_samples
== 0));
795 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
796 (key
->src_samples
== 0));
797 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
798 (key
->dst_samples
== 0));
800 /* Set up prog_data */
801 memset(&prog_data
, 0, sizeof(prog_data
));
802 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
805 * By default everything is emitted as 16-wide with only a few exceptions
806 * handled explicitly either here in the compiler or by one of the specific
807 * code emission calls.
808 * It should be also noted that here in this file any alterations of the
809 * compression control settings are only used to affect the execution size
810 * of the instructions. The instruction template used to initialise all the
811 * instructions is effectively not altered -- the value stays at zero
812 * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
814 * If any other settings are used in the instruction headers, they are set
815 * elsewhere by the individual code emission calls.
817 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
820 compute_frag_coords();
822 /* Render target and texture hardware don't support W tiling. */
823 const bool rt_tiled_w
= false;
824 const bool tex_tiled_w
= false;
826 /* The address that data will be written to is determined by the
827 * coordinates supplied to the WM thread and the tiling and sample count of
828 * the render target, according to the formula:
830 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
832 * If the actual tiling and sample count of the destination surface are not
833 * the same as the configuration of the render target, then these
834 * coordinates are wrong and we have to adjust them to compensate for the
837 if (rt_tiled_w
!= key
->dst_tiled_w
||
838 key
->rt_samples
!= key
->dst_samples
||
839 key
->rt_layout
!= key
->dst_layout
) {
840 encode_msaa(key
->rt_samples
, key
->rt_layout
);
841 /* Now (X, Y, S) = detile(rt_tiling, offset) */
842 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
843 /* Now (X, Y, S) = detile(dst_tiling, offset) */
844 decode_msaa(key
->dst_samples
, key
->dst_layout
);
847 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
849 * That is: X, Y and S now contain the true coordinates and sample index of
850 * the data that the WM thread should output.
852 * If we need to kill pixels that are outside the destination rectangle,
853 * now is the time to do it.
857 kill_if_outside_dst_rect();
859 /* Next, apply a translation to obtain coordinates in the source image. */
860 translate_dst_to_src();
862 /* If the source image is not multisampled, then we want to fetch sample
863 * number 0, because that's the only sample there is.
865 if (key
->src_samples
== 0)
868 /* X, Y, and S are now the coordinates of the pixel in the source image
869 * that we want to texture from. Exception: if we are blending, then S is
870 * irrelevant, because we are going to fetch all samples.
872 if (key
->blend
&& !key
->blit_scaled
) {
874 /* Gen6 hardware an automatically blend using the SAMPLE message */
876 sample(texture_data
[0]);
878 /* Gen7+ hardware doesn't automaticaly blend. */
879 manual_blend_average(key
->src_samples
);
881 } else if(key
->blend
&& key
->blit_scaled
) {
882 manual_blend_bilinear(key
->src_samples
);
884 /* We aren't blending, which means we just want to fetch a single sample
885 * from the source surface. The address that we want to fetch from is
886 * related to the X, Y and S values according to the formula:
888 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
890 * If the actual tiling and sample count of the source surface are not
891 * the same as the configuration of the texture, then we need to adjust
892 * the coordinates to compensate for the difference.
894 if ((tex_tiled_w
!= key
->src_tiled_w
||
895 key
->tex_samples
!= key
->src_samples
||
896 key
->tex_layout
!= key
->src_layout
) &&
897 !key
->bilinear_filter
) {
898 encode_msaa(key
->src_samples
, key
->src_layout
);
899 /* Now (X, Y, S) = detile(src_tiling, offset) */
900 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
901 /* Now (X, Y, S) = detile(tex_tiling, offset) */
902 decode_msaa(key
->tex_samples
, key
->tex_layout
);
905 if (key
->bilinear_filter
) {
906 sample(texture_data
[0]);
909 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
911 * In other words: X, Y, and S now contain values which, when passed to
912 * the texturing unit, will cause data to be read from the correct
913 * memory location. So we can fetch the texel now.
915 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
917 texel_fetch(texture_data
[0]);
921 /* Finally, write the fetched (or blended) value to the render target and
922 * terminate the thread.
924 render_target_write();
926 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
927 printf("Native code for BLORP blit:\n");
928 brw_dump_compile(&func
, dump_file
, 0, func
.next_insn_offset
);
931 return brw_get_program(&func
, program_size
);
935 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
937 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
938 #define ALLOC_REG(name, type) \
940 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
941 base_reg + CONST_LOC(name) / 32, \
942 (CONST_LOC(name) % 32) / 4), type)
944 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
945 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
946 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
947 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
948 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
949 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
950 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
951 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
952 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
953 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
959 brw_blorp_blit_program::alloc_regs()
962 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
963 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
964 prog_data
.first_curbe_grf
= reg
;
965 alloc_push_const_regs(reg
);
966 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
967 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
968 this->texture_data
[i
] =
969 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
973 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
975 for (int i
= 0; i
< 2; ++i
) {
977 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
980 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
984 if (key
->blit_scaled
&& key
->blend
) {
985 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
987 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
989 this->x_frac
= brw_vec8_grf(reg
, 0);
991 this->y_frac
= brw_vec8_grf(reg
, 0);
995 this->xy_coord_index
= 0;
997 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
999 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1001 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1004 /* Make sure we didn't run out of registers */
1005 assert(reg
<= GEN7_MRF_HACK_START
);
1008 this->base_mrf
= mrf
;
1011 /* In the code that follows, X and Y can be used to quickly refer to the
1012 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
1013 * prime") to the inactive elements.
1015 * S can be used to quickly refer to sample_index.
1017 #define X x_coords[xy_coord_index]
1018 #define Y y_coords[xy_coord_index]
1019 #define Xp x_coords[!xy_coord_index]
1020 #define Yp y_coords[!xy_coord_index]
1021 #define S sample_index
1023 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
1024 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
1026 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
1029 * Emit code to compute the X and Y coordinates of the pixels being rendered
1030 * by this WM invocation.
1032 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1033 * related to the address offset where outputs will be written by the formula:
1035 * (X, Y, S) = decode_msaa(detile(offset)).
1037 * (See brw_blorp_blit_program).
1040 brw_blorp_blit_program::compute_frag_coords()
1042 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1043 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1044 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1045 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1047 * Pixels within a subspan are laid out in this arrangement:
1051 * So, to compute the coordinates of each pixel, we need to read every 2nd
1052 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1053 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1054 * In other words, the data we want to access is R1.4<2;4,0>UW.
1056 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1057 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1059 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1060 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1062 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1063 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1064 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1067 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1068 * pixels n+2 and n+3 are in the bottom half of the subspan.
1070 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1071 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1073 /* Move the coordinates to UD registers. */
1074 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1075 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1078 if (key
->persample_msaa_dispatch
) {
1079 switch (key
->rt_samples
) {
1081 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1082 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1083 * represent sample 1, and so on.
1085 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1086 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1087 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1088 * then copy from it using vstride=1, width=4, hstride=0.
1090 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1091 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1092 /* Move to UD sample_index register. */
1093 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1094 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1095 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1096 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1100 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1101 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1102 * subspan 1 will represent sample 1, and so on. We can find the
1103 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1104 * Index") and multiplying by two (since samples are always delivered
1105 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1108 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1109 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1110 * variable with the sequence (0, 1, 2, 3), and then reading from it
1111 * using vstride=1, width=4, hstride=0.
1113 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1114 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1115 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1116 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1117 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1118 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1119 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1120 stride(t2_uw1
, 1, 4, 0));
1121 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1122 brw_ADD(&func
, offset(S
, 1),
1123 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1124 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1125 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1129 assert(!"Unrecognized sample count in "
1130 "brw_blorp_blit_program::compute_frag_coords()");
1135 /* Either the destination surface is single-sampled, or the WM will be
1136 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1137 * per pixel). In either case, it's not meaningful to compute a sample
1138 * value. Just set it to 0.
1145 * Emit code to compensate for the difference between Y and W tiling.
1147 * This code modifies the X and Y coordinates according to the formula:
1149 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1151 * (See brw_blorp_blit_program).
1153 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1154 * are booleans where true represents W tiling and false represents Y tiling.
1157 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1159 if (old_tiled_w
== new_tiled_w
)
1162 /* In the code that follows, we can safely assume that S = 0, because W
1163 * tiling formats always use IMS layout.
1168 /* Given X and Y coordinates that describe an address using Y tiling,
1169 * translate to the X and Y coordinates that describe the same address
1172 * If we break down the low order bits of X and Y, using a
1173 * single letter to represent each low-order bit:
1175 * X = A << 7 | 0bBCDEFGH
1176 * Y = J << 5 | 0bKLMNP (1)
1178 * Then we can apply the Y tiling formula to see the memory offset being
1181 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1183 * If we apply the W detiling formula to this memory location, that the
1184 * corresponding X' and Y' coordinates are:
1186 * X' = A << 6 | 0bBCDPFH (3)
1187 * Y' = J << 6 | 0bKLMNEG
1189 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1190 * we need to make the following computation:
1192 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1193 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1195 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1196 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1197 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1198 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1199 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1200 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1201 brw_OR(&func
, Xp
, t1
, t2
);
1202 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1203 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1204 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1205 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1206 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1207 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1208 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1209 brw_OR(&func
, Yp
, t1
, t2
);
1212 /* Applying the same logic as above, but in reverse, we obtain the
1215 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1216 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1218 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1219 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1220 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1221 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1222 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1223 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1224 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1225 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1227 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1228 brw_OR(&func
, Xp
, t1
, t2
);
1229 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1230 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1231 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1232 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1233 brw_OR(&func
, Yp
, t1
, t2
);
1239 * Emit code to compensate for the difference between MSAA and non-MSAA
1242 * This code modifies the X and Y coordinates according to the formula:
1244 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1246 * (See brw_blorp_blit_program).
1249 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1250 intel_msaa_layout layout
)
1253 case INTEL_MSAA_LAYOUT_NONE
:
1254 /* No translation necessary, and S should already be zero. */
1257 case INTEL_MSAA_LAYOUT_CMS
:
1258 /* We can't compensate for compressed layout since at this point in the
1259 * program we haven't read from the MCS buffer.
1261 assert(!"Bad layout in encode_msaa");
1263 case INTEL_MSAA_LAYOUT_UMS
:
1264 /* No translation necessary. */
1266 case INTEL_MSAA_LAYOUT_IMS
:
1267 switch (num_samples
) {
1269 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1270 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1271 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1273 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1275 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1276 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1278 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1280 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1281 brw_OR(&func
, Xp
, t1
, t2
);
1282 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1283 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1285 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1286 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1288 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1289 brw_OR(&func
, Yp
, t1
, t2
);
1292 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1293 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1295 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1297 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1298 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1300 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1301 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1302 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1303 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1304 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1307 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1308 brw_OR(&func
, Xp
, t1
, t2
);
1309 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1310 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1312 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1313 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1315 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1316 brw_OR(&func
, Yp
, t1
, t2
);
1326 * Emit code to compensate for the difference between MSAA and non-MSAA
1329 * This code modifies the X and Y coordinates according to the formula:
1331 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1333 * (See brw_blorp_blit_program).
1336 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1337 intel_msaa_layout layout
)
1340 case INTEL_MSAA_LAYOUT_NONE
:
1341 /* No translation necessary, and S should already be zero. */
1344 case INTEL_MSAA_LAYOUT_CMS
:
1345 /* We can't compensate for compressed layout since at this point in the
1346 * program we don't have access to the MCS buffer.
1348 assert(!"Bad layout in encode_msaa");
1350 case INTEL_MSAA_LAYOUT_UMS
:
1351 /* No translation necessary. */
1353 case INTEL_MSAA_LAYOUT_IMS
:
1355 switch (num_samples
) {
1357 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1358 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1359 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1360 * S = (Y & 0b10) | (X & 0b10) >> 1
1362 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1363 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1364 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1365 brw_OR(&func
, Xp
, t1
, t2
);
1366 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1367 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1368 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1369 brw_OR(&func
, Yp
, t1
, t2
);
1370 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1371 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1372 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1373 brw_OR(&func
, S
, t1
, t2
);
1376 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1377 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1378 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1379 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1381 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1382 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1383 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1384 brw_OR(&func
, Xp
, t1
, t2
);
1385 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1386 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1387 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1388 brw_OR(&func
, Yp
, t1
, t2
);
1389 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1390 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1391 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1392 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1393 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1394 brw_OR(&func
, S
, t1
, t2
);
1404 * Emit code that kills pixels whose X and Y coordinates are outside the
1405 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1409 brw_blorp_blit_program::kill_if_outside_dst_rect()
1411 struct brw_reg f0
= brw_flag_reg(0, 0);
1412 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1413 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1415 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1416 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1417 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1418 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1420 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1422 struct brw_instruction
*inst
= brw_AND(&func
, g1
, f0
, g1
);
1423 inst
->header
.mask_control
= BRW_MASK_DISABLE
;
1427 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1431 brw_blorp_blit_program::translate_dst_to_src()
1433 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1434 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1435 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1436 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1438 /* Move the UD coordinates to float registers. */
1439 brw_MOV(&func
, Xp_f
, X
);
1440 brw_MOV(&func
, Yp_f
, Y
);
1441 /* Scale and offset */
1442 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1443 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1444 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1445 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1446 if (key
->blit_scaled
&& key
->blend
) {
1447 /* Translate coordinates to lay out the samples in a rectangular grid
1448 * roughly corresponding to sample locations.
1450 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1451 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1452 /* Adjust coordinates so that integers represent pixel centers rather
1455 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1456 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1458 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1459 * texels on texture edges.
1461 clamp_tex_coords(X_f
, Y_f
,
1462 brw_imm_f(0.0), brw_imm_f(0.0),
1463 rect_grid_x1
, rect_grid_y1
);
1465 /* Store the fractional parts to be used as bilinear interpolation
1468 brw_FRC(&func
, x_frac
, X_f
);
1469 brw_FRC(&func
, y_frac
, Y_f
);
1471 /* Round the float coordinates down to nearest integer */
1472 brw_RNDD(&func
, Xp_f
, X_f
);
1473 brw_RNDD(&func
, Yp_f
, Y_f
);
1474 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1475 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1477 } else if (!key
->bilinear_filter
) {
1478 /* Round the float coordinates down to nearest integer by moving to
1481 brw_MOV(&func
, Xp
, X_f
);
1482 brw_MOV(&func
, Yp
, Y_f
);
1488 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1489 struct brw_reg regY
,
1490 struct brw_reg clampX0
,
1491 struct brw_reg clampY0
,
1492 struct brw_reg clampX1
,
1493 struct brw_reg clampY1
)
1495 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regX
, clampX0
);
1496 brw_MOV(&func
, regX
, clampX0
);
1497 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1499 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regX
, clampX1
);
1500 brw_MOV(&func
, regX
, clampX1
);
1501 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1503 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regY
, clampY0
);
1504 brw_MOV(&func
, regY
, clampY0
);
1505 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1507 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regY
, clampY1
);
1508 brw_MOV(&func
, regY
, clampY1
);
1509 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1513 * Emit code to transform the X and Y coordinates as needed for blending
1514 * together the different samples in an MSAA texture.
1517 brw_blorp_blit_program::single_to_blend()
1519 /* When looking up samples in an MSAA texture using the SAMPLE message,
1520 * Gen6 requires the texture coordinates to be odd integers (so that they
1521 * correspond to the center of a 2x2 block representing the four samples
1522 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1523 * each by 2 and then add 1.
1525 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1526 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1527 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1528 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1534 * Count the number of trailing 1 bits in the given value. For example:
1536 * count_trailing_one_bits(0) == 0
1537 * count_trailing_one_bits(7) == 3
1538 * count_trailing_one_bits(11) == 2
1540 inline int count_trailing_one_bits(unsigned value
)
1542 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1543 return __builtin_ctz(~value
);
1545 return _mesa_bitcount(value
& ~(value
+ 1));
1551 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1553 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1556 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1558 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1560 * This ensures that when all samples have the same value, no numerical
1561 * precision is lost, since each addition operation always adds two equal
1562 * values, and summing two equal floating point values does not lose
1565 * We perform this computation by treating the texture_data array as a
1566 * stack and performing the following operations:
1568 * - push sample 0 onto stack
1569 * - push sample 1 onto stack
1570 * - add top two stack entries
1571 * - push sample 2 onto stack
1572 * - push sample 3 onto stack
1573 * - add top two stack entries
1574 * - add top two stack entries
1575 * - divide top stack entry by 4
1577 * Note that after pushing sample i onto the stack, the number of add
1578 * operations we do is equal to the number of trailing 1 bits in i. This
1579 * works provided the total number of samples is a power of two, which it
1580 * always is for i965.
1582 * For integer formats, we replace the add operations with average
1583 * operations and skip the final division.
1585 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1589 brw_op2_ptr combine_op
=
1590 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1591 unsigned stack_depth
= 0;
1592 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1593 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1595 /* Push sample i onto the stack */
1596 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1601 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1603 texel_fetch(texture_data
[stack_depth
++]);
1605 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1606 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1607 * suggests an optimization:
1609 * "A simple optimization with probable large return in
1610 * performance is to compare the MCS value to zero (indicating
1611 * all samples are on sample slice 0), and sample only from
1612 * sample slice 0 using ld2dss if MCS is zero."
1614 * Note that in the case where the MCS value is zero, sampling from
1615 * sample slice 0 using ld2dss and sampling from sample 0 using
1616 * ld2dms are equivalent (since all samples are on sample slice 0).
1617 * Since we have already sampled from sample 0, all we need to do is
1618 * skip the remaining fetches and averaging if MCS is zero.
1620 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1621 mcs_data
, brw_imm_ud(0));
1622 brw_IF(&func
, BRW_EXECUTE_16
);
1625 /* Do count_trailing_one_bits(i) times */
1626 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1627 assert(stack_depth
>= 2);
1630 /* TODO: should use a smaller loop bound for non_RGBA formats */
1631 for (int k
= 0; k
< 4; ++k
) {
1632 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1633 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1634 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1639 /* We should have just 1 sample on the stack now. */
1640 assert(stack_depth
== 1);
1642 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1643 /* Scale the result down by a factor of num_samples */
1644 /* TODO: should use a smaller loop bound for non-RGBA formats */
1645 for (int j
= 0; j
< 4; ++j
) {
1646 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1647 offset(vec8(texture_data
[0]), 2*j
),
1648 brw_imm_f(1.0/num_samples
));
1652 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1657 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1659 /* We do this computation by performing the following operations:
1661 * In case of 4x, 8x MSAA:
1662 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1663 * which are later used for interpolation
1664 * - linearly interpolate samples a and b in X
1665 * - linearly interpolate samples c and d in X
1666 * - linearly interpolate the results of last two operations in Y
1668 * result = lrp(lrp(a + b) + lrp(c + d))
1670 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1671 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1672 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1673 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1675 for (unsigned i
= 0; i
< 4; ++i
) {
1676 assert(i
< ARRAY_SIZE(texture_data
));
1679 /* Compute pixel coordinates */
1680 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1681 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1682 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1683 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1684 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1685 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1687 /* The MCS value we fetch has to match up with the pixel that we're
1688 * sampling from. Since we sample from different pixels in each
1689 * iteration of this "for" loop, the call to mcs_fetch() should be
1690 * here inside the loop after computing the pixel coordinates.
1692 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1695 /* Compute sample index and map the sample index to a sample number.
1696 * Sample index layout shows the numbering of slots in a rectangular
1697 * grid of samples with in a pixel. Sample number layout shows the
1698 * rectangular grid of samples roughly corresponding to the real sample
1699 * locations with in a pixel.
1700 * In case of 4x MSAA, layout of sample indices matches the layout of
1708 * In case of 8x MSAA the two layouts don't match.
1709 * sample index layout : --------- sample number layout : ---------
1710 * | 0 | 1 | | 5 | 2 |
1711 * --------- ---------
1712 * | 2 | 3 | | 4 | 6 |
1713 * --------- ---------
1714 * | 4 | 5 | | 0 | 3 |
1715 * --------- ---------
1716 * | 6 | 7 | | 7 | 1 |
1717 * --------- ---------
1719 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1720 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1721 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1722 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1723 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1724 brw_MOV(&func
, vec16(S
), t1_f
);
1726 if (num_samples
== 8) {
1727 /* Map the sample index to a sample number */
1728 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1730 brw_IF(&func
, BRW_EXECUTE_16
);
1732 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1733 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1735 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1736 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1737 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1739 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1740 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1741 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1743 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1744 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1748 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1749 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1751 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1752 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1753 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1755 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1756 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1757 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1759 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1760 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1763 brw_MOV(&func
, vec16(S
), t2
);
1765 texel_fetch(texture_data
[i
]);
1768 #define SAMPLE(x, y) offset(texture_data[x], y)
1769 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1770 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1771 for (int index
= 3; index
> 0; ) {
1772 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1773 * Counter value of 8 in 'for' loop below is used to interpolate all
1774 * the color components.
1776 for (int k
= 0; k
< 8; ++k
)
1778 vec8(SAMPLE(index
- 1, k
)),
1779 offset(x_frac
, k
& 1),
1781 SAMPLE(index
- 1, k
));
1784 for (int k
= 0; k
< 8; ++k
)
1787 offset(y_frac
, k
& 1),
1789 vec8(SAMPLE(0, k
)));
1790 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1791 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1796 * Emit code to look up a value in the texture using the SAMPLE message (which
1797 * does blending of MSAA surfaces).
1800 brw_blorp_blit_program::sample(struct brw_reg dst
)
1802 static const sampler_message_arg args
[2] = {
1803 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1804 SAMPLER_MESSAGE_ARG_V_FLOAT
1807 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
,
1812 * Emit code to look up a value in the texture using the SAMPLE_LD message
1813 * (which does a simple texel fetch).
1816 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1818 static const sampler_message_arg gen6_args
[5] = {
1819 SAMPLER_MESSAGE_ARG_U_INT
,
1820 SAMPLER_MESSAGE_ARG_V_INT
,
1821 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1822 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1823 SAMPLER_MESSAGE_ARG_SI_INT
1825 static const sampler_message_arg gen7_ld_args
[3] = {
1826 SAMPLER_MESSAGE_ARG_U_INT
,
1827 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1828 SAMPLER_MESSAGE_ARG_V_INT
1830 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1831 SAMPLER_MESSAGE_ARG_SI_INT
,
1832 SAMPLER_MESSAGE_ARG_U_INT
,
1833 SAMPLER_MESSAGE_ARG_V_INT
1835 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1836 SAMPLER_MESSAGE_ARG_SI_INT
,
1837 SAMPLER_MESSAGE_ARG_MCS_INT
,
1838 SAMPLER_MESSAGE_ARG_U_INT
,
1839 SAMPLER_MESSAGE_ARG_V_INT
1844 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1848 switch (key
->tex_layout
) {
1849 case INTEL_MSAA_LAYOUT_IMS
:
1850 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1853 * If this field is MSFMT_DEPTH_STENCIL
1854 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1855 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1857 * So fall through to emit the same message as we use for
1858 * INTEL_MSAA_LAYOUT_CMS.
1860 case INTEL_MSAA_LAYOUT_CMS
:
1861 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1862 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1864 case INTEL_MSAA_LAYOUT_UMS
:
1865 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1866 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1868 case INTEL_MSAA_LAYOUT_NONE
:
1870 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1871 ARRAY_SIZE(gen7_ld_args
));
1876 assert(!"Should not get here.");
1882 brw_blorp_blit_program::mcs_fetch()
1884 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1885 SAMPLER_MESSAGE_ARG_U_INT
,
1886 SAMPLER_MESSAGE_ARG_V_INT
1888 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1889 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1893 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1895 const sampler_message_arg
*args
,
1898 struct brw_reg mrf
=
1899 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1900 for (int arg
= 0; arg
< num_args
; ++arg
) {
1901 switch (args
[arg
]) {
1902 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1903 if (key
->bilinear_filter
)
1904 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1905 retype(X
, BRW_REGISTER_TYPE_F
));
1907 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1909 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1910 if (key
->bilinear_filter
)
1911 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1912 retype(Y
, BRW_REGISTER_TYPE_F
));
1914 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1916 case SAMPLER_MESSAGE_ARG_U_INT
:
1917 brw_MOV(&func
, mrf
, X
);
1919 case SAMPLER_MESSAGE_ARG_V_INT
:
1920 brw_MOV(&func
, mrf
, Y
);
1922 case SAMPLER_MESSAGE_ARG_SI_INT
:
1923 /* Note: on Gen7, this code may be reached with s_is_zero==true
1924 * because in Gen7's ld2dss message, the sample index is the first
1925 * argument. When this happens, we need to move a 0 into the
1926 * appropriate message register.
1929 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1931 brw_MOV(&func
, mrf
, S
);
1933 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1934 switch (key
->tex_layout
) {
1935 case INTEL_MSAA_LAYOUT_CMS
:
1936 brw_MOV(&func
, mrf
, mcs_data
);
1938 case INTEL_MSAA_LAYOUT_IMS
:
1939 /* When sampling from an IMS surface, MCS data is not relevant,
1940 * and the hardware ignores it. So don't bother populating it.
1944 /* We shouldn't be trying to send MCS data with any other
1947 assert (!"Unsupported layout for MCS data");
1951 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1952 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1959 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1960 base_mrf
/* msg_reg_nr */,
1961 brw_message_reg(base_mrf
) /* src0 */,
1962 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1965 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1966 mrf
.nr
- base_mrf
/* msg_length */,
1967 0 /* header_present */,
1968 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1969 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1977 #undef SWAP_XY_AND_XPYP
1980 brw_blorp_blit_program::render_target_write()
1982 struct brw_reg mrf_rt_write
=
1983 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1986 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1987 * so that the render target knows which pixels we killed.
1989 bool use_header
= key
->use_kill
;
1991 /* Copy R0/1 to MRF */
1992 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1993 retype(R0
, BRW_REGISTER_TYPE_UD
));
1997 /* Copy texture data to MRFs */
1998 for (int i
= 0; i
< 4; ++i
) {
1999 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
2000 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
2001 offset(vec8(texture_data
[0]), 2*i
));
2005 /* Now write to the render target and terminate the thread */
2007 16 /* dispatch_width */,
2008 base_mrf
/* msg_reg_nr */,
2009 mrf_rt_write
/* src0 */,
2010 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
2011 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
2012 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
2013 0 /* response_length */,
2020 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
2021 GLfloat dst0
, GLfloat dst1
,
2024 float scale
= (src1
- src0
) / (dst1
- dst0
);
2026 /* When not mirroring a coordinate (say, X), we need:
2027 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
2029 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
2031 * blorp program uses "round toward zero" to convert the
2032 * transformed floating point coordinates to integer coordinates,
2033 * whereas the behaviour we actually want is "round to nearest",
2034 * so 0.5 provides the necessary correction.
2037 offset
= src0
+ (-dst0
+ 0.5) * scale
;
2039 /* When mirroring X we need:
2040 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2042 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2044 multiplier
= -scale
;
2045 offset
= src0
+ (dst1
- 0.5) * scale
;
2051 * Determine which MSAA layout the GPU pipeline should be configured for,
2052 * based on the chip generation, the number of samples, and the true layout of
2053 * the image in memory.
2055 inline intel_msaa_layout
2056 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2057 intel_msaa_layout true_layout
)
2059 if (num_samples
<= 1) {
2060 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2061 * format buffers, by transforming coordinates appropriately.
2063 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2064 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2065 return INTEL_MSAA_LAYOUT_NONE
;
2067 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2070 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2071 if (brw
->gen
== 6) {
2072 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2079 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2080 struct intel_mipmap_tree
*src_mt
,
2081 unsigned src_level
, unsigned src_layer
,
2082 struct intel_mipmap_tree
*dst_mt
,
2083 unsigned dst_level
, unsigned dst_layer
,
2084 GLfloat src_x0
, GLfloat src_y0
,
2085 GLfloat src_x1
, GLfloat src_y1
,
2086 GLfloat dst_x0
, GLfloat dst_y0
,
2087 GLfloat dst_x1
, GLfloat dst_y1
,
2089 bool mirror_x
, bool mirror_y
)
2091 struct gl_context
*ctx
= &brw
->ctx
;
2092 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2094 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
2095 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
2097 /* Even though we do multisample resolves at the time of the blit, OpenGL
2098 * specification defines them as if they happen at the time of rendering,
2099 * which means that the type of averaging we do during the resolve should
2100 * only depend on the source format; the destination format should be
2101 * ignored. But, specification doesn't seem to be strict about it.
2103 * It has been observed that mulitisample resolves produce slightly better
2104 * looking images when averaging is done using destination format. NVIDIA's
2105 * proprietary OpenGL driver also follow this approach. So, we choose to
2106 * follow it in our driver.
2108 * When multisampling, if the source and destination formats are equal
2109 * (aside from the color space), we choose to blit in sRGB space to get
2110 * this higher quality image.
2112 if (src
.num_samples
> 1 &&
2113 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
2114 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2115 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2116 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2117 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2120 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
2121 * texture, the above code configures the source format for L32_FLOAT or
2122 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
2123 * the SAMPLE message appears to handle multisampled L32_FLOAT and
2124 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
2125 * around the problem by using a source format of R32_FLOAT. This
2126 * shouldn't affect rendering correctness, since the destination format is
2127 * R32_FLOAT, so only the contents of the red channel matters.
2129 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
2130 src_mt
->format
== dst_mt
->format
&&
2131 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
2132 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2136 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2138 /* texture_data_type indicates the register type that should be used to
2139 * manipulate texture data.
2141 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2142 case GL_UNSIGNED_NORMALIZED
:
2143 case GL_SIGNED_NORMALIZED
:
2145 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2147 case GL_UNSIGNED_INT
:
2148 if (src_mt
->format
== MESA_FORMAT_S8
) {
2149 /* We process stencil as though it's an unsigned normalized color */
2150 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2152 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2156 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2159 assert(!"Unrecognized blorp format");
2164 /* Gen7's rendering hardware only supports the IMS layout for depth and
2165 * stencil render targets. Blorp always maps its destination surface as
2166 * a color render target (even if it's actually a depth or stencil
2167 * buffer). So if the destination is IMS, we'll have to map it as a
2168 * single-sampled texture and interleave the samples ourselves.
2170 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2171 dst
.num_samples
= 0;
2174 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2175 /* If the destination surface is a W-tiled multisampled stencil buffer
2176 * that we're mapping as Y tiled, then we need to arrange for the WM
2177 * program to run once per sample rather than once per pixel, because
2178 * the memory layout of related samples doesn't match between W and Y
2181 wm_prog_key
.persample_msaa_dispatch
= true;
2184 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2185 /* We are blitting from a multisample buffer to a multisample buffer, so
2186 * we must preserve samples within a pixel. This means we have to
2187 * arrange for the WM program to run once per sample rather than once
2190 wm_prog_key
.persample_msaa_dispatch
= true;
2193 /* Scaled blitting or not. */
2194 wm_prog_key
.blit_scaled
=
2195 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2196 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2198 /* Scaling factors used for bilinear filtering in multisample scaled
2201 wm_prog_key
.x_scale
= 2.0;
2202 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2204 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2205 wm_prog_key
.bilinear_filter
= true;
2207 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2208 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2209 base_format
!= GL_STENCIL_INDEX
&&
2210 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2211 /* We are downsampling a color buffer, so blend. */
2212 wm_prog_key
.blend
= true;
2215 /* src_samples and dst_samples are the true sample counts */
2216 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2217 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2219 /* tex_samples and rt_samples are the sample counts that are set up in
2222 wm_prog_key
.tex_samples
= src
.num_samples
;
2223 wm_prog_key
.rt_samples
= dst
.num_samples
;
2225 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2226 * use to access the source and destination surfaces.
2228 wm_prog_key
.tex_layout
=
2229 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2230 wm_prog_key
.rt_layout
=
2231 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2233 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2236 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2237 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2239 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2240 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2241 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2242 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2243 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2244 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2245 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2246 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2248 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2249 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2251 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2252 /* We must expand the rectangle we send through the rendering pipeline,
2253 * to account for the fact that we are mapping the destination region as
2254 * single-sampled when it is in fact multisampled. We must also align
2255 * it to a multiple of the multisampling pattern, because the
2256 * differences between multisampled and single-sampled surface formats
2257 * will mean that pixels are scrambled within the multisampling pattern.
2258 * TODO: what if this makes the coordinates too large?
2260 * Note: this only works if the destination surface uses the IMS layout.
2261 * If it's UMS, then we have no choice but to set up the rendering
2262 * pipeline as multisampled.
2264 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2265 switch (dst_mt
->num_samples
) {
2267 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2268 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2269 x1
= ALIGN(x1
* 2, 4);
2270 y1
= ALIGN(y1
* 2, 4);
2273 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2274 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2275 x1
= ALIGN(x1
* 4, 8);
2276 y1
= ALIGN(y1
* 2, 4);
2279 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2282 wm_prog_key
.use_kill
= true;
2285 if (dst
.map_stencil_as_y_tiled
) {
2286 /* We must modify the rectangle we send through the rendering pipeline
2287 * (and the size and x/y offset of the destination surface), to account
2288 * for the fact that we are mapping it as Y-tiled when it is in fact
2291 * Both Y tiling and W tiling can be understood as organizations of
2292 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2293 * is different, but the layout of the 32-byte sub-tiles within the 4k
2294 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2295 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2296 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2298 * Therefore, to account for the layout differences within the 32-byte
2299 * sub-tiles, we must expand the rectangle so the X coordinates of its
2300 * edges are multiples of 8 (the W sub-tile width), and its Y
2301 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2302 * Then we need to scale the X and Y coordinates of the rectangle to
2303 * account for the differences in aspect ratio between the Y and W
2304 * sub-tiles. We need to modify the layer width and height similarly.
2306 * A correction needs to be applied when MSAA is in use: since
2307 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2308 * we need to align the Y coordinates to multiples of 8, so that when
2309 * they are divided by two they are still multiples of 4.
2311 * Note: Since the x/y offset of the surface will be applied using the
2312 * SURFACE_STATE command packet, it will be invisible to the swizzling
2313 * code in the shader; therefore it needs to be in a multiple of the
2314 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2315 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2316 * buffer), and the miplevel alignment used for stencil buffers is 8
2317 * pixels horizontally and either 4 or 8 pixels vertically (see
2318 * intel_horizontal_texture_alignment_unit() and
2319 * intel_vertical_texture_alignment_unit()).
2321 * Note: Also, since the SURFACE_STATE command packet can only apply
2322 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2323 * vertically, it is important that the offsets will be multiples of
2324 * these sizes after they are converted into Y-tiled coordinates.
2325 * Fortunately they will be, since we know from above that the offsets
2326 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2327 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2329 * TODO: what if this makes the coordinates (or the texture size) too
2332 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2333 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2334 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2335 x1
= ALIGN(x1
, x_align
) * 2;
2336 y1
= ALIGN(y1
, y_align
) / 2;
2337 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2338 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2341 wm_prog_key
.use_kill
= true;
2344 if (src
.map_stencil_as_y_tiled
) {
2345 /* We must modify the size and x/y offset of the source surface to
2346 * account for the fact that we are mapping it as Y-tiled when it is in
2349 * See the comments above concerning x/y offset alignment for the
2350 * destination surface.
2352 * TODO: what if this makes the texture size too large?
2354 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2355 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2356 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2363 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2364 brw_blorp_prog_data
**prog_data
) const
2366 uint32_t prog_offset
= 0;
2367 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2368 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2369 &prog_offset
, prog_data
)) {
2370 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2371 GLuint program_size
;
2372 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2373 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2374 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2375 program
, program_size
,
2376 &prog
.prog_data
, sizeof(prog
.prog_data
),
2377 &prog_offset
, prog_data
);
2383 brw_blorp_blit_test_compile(struct brw_context
*brw
,
2384 const brw_blorp_blit_prog_key
*key
,
2387 GLuint program_size
;
2388 brw_blorp_blit_program
prog(brw
, key
);
2389 INTEL_DEBUG
|= DEBUG_BLORP
;
2390 prog
.compile(brw
, &program_size
, out
);