2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
39 * Helper function for handling mirror image blits.
41 * If coord0 > coord1, swap them and invert the "mirror" boolean.
44 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
46 if (coord0
> coord1
) {
56 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
57 * destination coordinates.
59 * Return true if there is still blitting to do, false if all pixels got
60 * rejected by the clip and/or scissor.
62 * For clarity, the nomenclature of this function assumes we are clipping and
63 * scissoring the X coordinate; the exact same logic applies for Y
66 * Note: this function may also be used to account for clipping of source
67 * coordinates, by swapping the roles of src and dst.
70 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
71 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
73 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
74 /* If we are going to scissor everything away, stop. */
75 if (!(fb_xmin
< fb_xmax
&&
82 /* Clip the destination rectangle, and keep track of how many pixels we
83 * clipped off of the left and right sides of it.
85 GLint pixels_clipped_left
= 0;
86 GLint pixels_clipped_right
= 0;
87 if (dst_x0
< fb_xmin
) {
88 pixels_clipped_left
= fb_xmin
- dst_x0
;
91 if (fb_xmax
< dst_x1
) {
92 pixels_clipped_right
= dst_x1
- fb_xmax
;
96 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
97 * the source coordinates, we need to flip them to account for the
101 GLint tmp
= pixels_clipped_left
;
102 pixels_clipped_left
= pixels_clipped_right
;
103 pixels_clipped_right
= tmp
;
106 /* Adjust the source rectangle to remove the pixels corresponding to those
107 * that were clipped/scissored out of the destination rectangle.
109 src_x0
+= pixels_clipped_left
* scale
;
110 src_x1
-= pixels_clipped_right
* scale
;
116 static struct intel_mipmap_tree
*
117 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
119 struct intel_mipmap_tree
*mt
= irb
->mt
;
120 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
126 brw_blorp_blit_miptrees(struct intel_context
*intel
,
127 struct intel_mipmap_tree
*src_mt
,
128 unsigned src_level
, unsigned src_layer
,
129 struct intel_mipmap_tree
*dst_mt
,
130 unsigned dst_level
, unsigned dst_layer
,
131 float src_x0
, float src_y0
,
132 float src_x1
, float src_y1
,
133 float dst_x0
, float dst_y0
,
134 float dst_x1
, float dst_y1
,
135 bool mirror_x
, bool mirror_y
)
137 intel_miptree_slice_resolve_depth(intel
, src_mt
, src_level
, src_layer
);
138 intel_miptree_slice_resolve_depth(intel
, dst_mt
, dst_level
, dst_layer
);
140 brw_blorp_blit_params
params(brw_context(&intel
->ctx
),
141 src_mt
, src_level
, src_layer
,
142 dst_mt
, dst_level
, dst_layer
,
148 brw_blorp_exec(intel
, ¶ms
);
150 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
154 do_blorp_blit(struct intel_context
*intel
, GLbitfield buffer_bit
,
155 struct intel_renderbuffer
*src_irb
,
156 struct intel_renderbuffer
*dst_irb
,
157 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
158 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
159 bool mirror_x
, bool mirror_y
)
161 /* Find source/dst miptrees */
162 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
163 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
166 brw_blorp_blit_miptrees(intel
,
167 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
168 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
169 srcX0
, srcY0
, srcX1
, srcY1
,
170 dstX0
, dstY0
, dstX1
, dstY1
,
173 intel_renderbuffer_set_needs_downsample(dst_irb
);
177 color_formats_match(gl_format src_format
, gl_format dst_format
)
179 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
180 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
182 /* Normally, we require the formats to be equal. However, we also support
183 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
184 * (overriding alpha to 1.0 via blending).
186 return linear_src_format
== linear_dst_format
||
187 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
188 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
189 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
190 linear_dst_format
== MESA_FORMAT_XRGB8888
);
194 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
195 struct intel_renderbuffer
*dst_irb
)
197 /* Note: don't just check gl_renderbuffer::Format, because in some cases
198 * multiple gl_formats resolve to the same native type in the miptree (for
199 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
200 * between those formats.
202 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
203 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
205 return color_formats_match(src_format
, dst_format
);
209 try_blorp_blit(struct intel_context
*intel
,
210 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
211 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
212 GLenum filter
, GLbitfield buffer_bit
)
214 struct gl_context
*ctx
= &intel
->ctx
;
216 /* Sync up the state of window system buffers. We need to do this before
217 * we go looking for the buffers.
219 intel_prepare_render(intel
);
221 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
222 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
224 /* Detect if the blit needs to be mirrored */
225 bool mirror_x
= false, mirror_y
= false;
226 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
227 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
228 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
229 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
231 /* Linear filtering is not yet implemented in blorp engine. So, fallback
232 * to other blit paths.
234 if ((srcX1
- srcX0
!= dstX1
- dstX0
||
235 srcY1
- srcY0
!= dstY1
- dstY0
) &&
239 /* If the destination rectangle needs to be clipped or scissored, do so.
241 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
242 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
243 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
244 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
245 /* Everything got clipped/scissored away, so the blit was successful. */
249 /* If the source rectangle needs to be clipped or scissored, do so. */
250 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
251 0, read_fb
->Width
) &&
252 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
253 0, read_fb
->Height
))) {
254 /* Everything got clipped/scissored away, so the blit was successful. */
258 /* Account for the fact that in the system framebuffer, the origin is at
261 if (_mesa_is_winsys_fbo(read_fb
)) {
262 GLint tmp
= read_fb
->Height
- srcY0
;
263 srcY0
= read_fb
->Height
- srcY1
;
265 mirror_y
= !mirror_y
;
267 if (_mesa_is_winsys_fbo(draw_fb
)) {
268 GLint tmp
= draw_fb
->Height
- dstY0
;
269 dstY0
= draw_fb
->Height
- dstY1
;
271 mirror_y
= !mirror_y
;
275 struct intel_renderbuffer
*src_irb
;
276 struct intel_renderbuffer
*dst_irb
;
277 switch (buffer_bit
) {
278 case GL_COLOR_BUFFER_BIT
:
279 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
280 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
281 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
282 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
285 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
286 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
288 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
289 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
293 case GL_DEPTH_BUFFER_BIT
:
295 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
297 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
298 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
300 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
301 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
304 case GL_STENCIL_BUFFER_BIT
:
306 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
308 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
309 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
311 do_blorp_blit(intel
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
312 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
323 brw_blorp_copytexsubimage(struct intel_context
*intel
,
324 struct gl_renderbuffer
*src_rb
,
325 struct gl_texture_image
*dst_image
,
326 int srcX0
, int srcY0
,
327 int dstX0
, int dstY0
,
328 int width
, int height
)
330 struct gl_context
*ctx
= &intel
->ctx
;
331 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
332 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
334 /* Sync up the state of window system buffers. We need to do this before
335 * we go looking at the src renderbuffer's miptree.
337 intel_prepare_render(intel
);
339 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
340 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
342 /* BLORP is not supported before Gen6. */
346 if (!color_formats_match(src_mt
->format
, dst_mt
->format
)) {
350 /* Source clipping shouldn't be necessary, since copytexsubimage (in
351 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
354 * Destination clipping shouldn't be necessary since the restrictions on
355 * glCopyTexSubImage prevent the user from specifying a destination rectangle
356 * that falls outside the bounds of the destination texture.
357 * See error_check_subtexture_dimensions().
360 int srcY1
= srcY0
+ height
;
361 int srcX1
= srcX0
+ width
;
362 int dstX1
= dstX0
+ width
;
363 int dstY1
= dstY0
+ height
;
365 /* Account for the fact that in the system framebuffer, the origin is at
368 bool mirror_y
= false;
369 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
370 GLint tmp
= src_rb
->Height
- srcY0
;
371 srcY0
= src_rb
->Height
- srcY1
;
376 brw_blorp_blit_miptrees(intel
,
377 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
378 dst_mt
, dst_image
->Level
, dst_image
->Face
,
379 srcX0
, srcY0
, srcX1
, srcY1
,
380 dstX0
, dstY0
, dstX1
, dstY1
,
383 /* If we're copying to a packed depth stencil texture and the source
384 * framebuffer has separate stencil, we need to also copy the stencil data
387 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
388 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
390 src_irb
= intel_renderbuffer(src_rb
);
391 if (src_irb
->mt
!= src_mt
)
393 brw_blorp_blit_miptrees(intel
,
394 src_irb
->mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
395 dst_mt
, dst_image
->Level
, dst_image
->Face
,
396 srcX0
, srcY0
, srcX1
, srcY1
,
397 dstX0
, dstY0
, dstX1
, dstY1
,
406 brw_blorp_framebuffer(struct intel_context
*intel
,
407 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
408 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
409 GLbitfield mask
, GLenum filter
)
411 /* BLORP is not supported before Gen6. */
415 static GLbitfield buffer_bits
[] = {
418 GL_STENCIL_BUFFER_BIT
,
421 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
422 if ((mask
& buffer_bits
[i
]) &&
423 try_blorp_blit(intel
,
424 srcX0
, srcY0
, srcX1
, srcY1
,
425 dstX0
, dstY0
, dstX1
, dstY1
,
426 filter
, buffer_bits
[i
])) {
427 mask
&= ~buffer_bits
[i
];
436 * Enum to specify the order of arguments in a sampler message
438 enum sampler_message_arg
440 SAMPLER_MESSAGE_ARG_U_FLOAT
,
441 SAMPLER_MESSAGE_ARG_V_FLOAT
,
442 SAMPLER_MESSAGE_ARG_U_INT
,
443 SAMPLER_MESSAGE_ARG_V_INT
,
444 SAMPLER_MESSAGE_ARG_SI_INT
,
445 SAMPLER_MESSAGE_ARG_MCS_INT
,
446 SAMPLER_MESSAGE_ARG_ZERO_INT
,
450 * Generator for WM programs used in BLORP blits.
452 * The bulk of the work done by the WM program is to wrap and unwrap the
453 * coordinate transformations used by the hardware to store surfaces in
454 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
455 * sample index for a multisampled surface) to a memory offset by the
456 * following formulas:
458 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
459 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
461 * For a single-sampled surface, or for a multisampled surface using
462 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
465 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
466 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
467 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
468 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
470 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
471 * embeds the sample number into bit 1 of the X and Y coordinates:
473 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
474 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
475 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
476 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
477 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
478 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
479 * S = (Y & 0b10) | (X & 0b10) >> 1
481 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
482 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
485 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
486 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
487 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
488 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
489 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
490 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
491 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
493 * For X tiling, tile() combines together the low-order bits of the X and Y
494 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
495 * bytes wide and 8 rows high:
497 * tile(x_tiled, X, Y, S) = A
498 * where A = tile_num << 12 | offset
499 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
500 * offset = (Y' & 0b111) << 9
501 * | (X & 0b111111111)
503 * Y' = Y + S * qpitch
504 * detile(x_tiled, A) = (X, Y, S)
508 * Y' = (tile_num / tile_pitch) << 3
509 * | (A & 0b111000000000) >> 9
510 * X' = (tile_num % tile_pitch) << 9
511 * | (A & 0b111111111)
513 * (In all tiling formulas, cpp is the number of bytes occupied by a single
514 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
515 * to fill the width of the surface, and qpitch is the spacing (in rows)
516 * between array slices).
518 * For Y tiling, tile() combines together the low-order bits of the X and Y
519 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
520 * bytes wide and 32 rows high:
522 * tile(y_tiled, X, Y, S) = A
523 * where A = tile_num << 12 | offset
524 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
525 * offset = (X' & 0b1110000) << 5
526 * | (Y' & 0b11111) << 4
529 * Y' = Y + S * qpitch
530 * detile(y_tiled, A) = (X, Y, S)
534 * Y' = (tile_num / tile_pitch) << 5
535 * | (A & 0b111110000) >> 4
536 * X' = (tile_num % tile_pitch) << 7
537 * | (A & 0b111000000000) >> 5
540 * For W tiling, tile() combines together the low-order bits of the X and Y
541 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
542 * bytes wide and 64 rows high (note that W tiling is only used for stencil
543 * buffers, which always have cpp = 1 and S=0):
545 * tile(w_tiled, X, Y, S) = A
546 * where A = tile_num << 12 | offset
547 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
548 * offset = (X' & 0b111000) << 6
549 * | (Y' & 0b111100) << 3
550 * | (X' & 0b100) << 2
556 * Y' = Y + S * qpitch
557 * detile(w_tiled, A) = (X, Y, S)
558 * where X = X' / cpp = X'
559 * Y = Y' % qpitch = Y'
561 * Y' = (tile_num / tile_pitch) << 6
562 * | (A & 0b111100000) >> 3
563 * | (A & 0b1000) >> 2
565 * X' = (tile_num % tile_pitch) << 6
566 * | (A & 0b111000000000) >> 6
567 * | (A & 0b10000) >> 2
571 * Finally, for a non-tiled surface, tile() simply combines together the X and
572 * Y coordinates in the natural way:
574 * tile(untiled, X, Y, S) = A
575 * where A = Y * pitch + X'
577 * Y' = Y + S * qpitch
578 * detile(untiled, A) = (X, Y, S)
585 * (In these formulas, pitch is the number of bytes occupied by a single row
588 class brw_blorp_blit_program
591 brw_blorp_blit_program(struct brw_context
*brw
,
592 const brw_blorp_blit_prog_key
*key
);
593 ~brw_blorp_blit_program();
595 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
597 brw_blorp_prog_data prog_data
;
601 void alloc_push_const_regs(int base_reg
);
602 void compute_frag_coords();
603 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
604 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
605 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
606 void kill_if_outside_dst_rect();
607 void translate_dst_to_src();
608 void single_to_blend();
609 void manual_blend(unsigned num_samples
);
610 void sample(struct brw_reg dst
);
611 void texel_fetch(struct brw_reg dst
);
613 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
614 const sampler_message_arg
*args
, int num_args
);
615 void render_target_write();
618 * Base-2 logarithm of the maximum number of samples that can be blended.
620 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
623 struct brw_context
*brw
;
624 const brw_blorp_blit_prog_key
*key
;
625 struct brw_compile func
;
627 /* Thread dispatch header */
630 /* Pixel X/Y coordinates (always in R1). */
634 struct brw_reg dst_x0
;
635 struct brw_reg dst_x1
;
636 struct brw_reg dst_y0
;
637 struct brw_reg dst_y1
;
639 struct brw_reg multiplier
;
640 struct brw_reg offset
;
641 } x_transform
, y_transform
;
643 /* Data read from texture (4 vec16's per array element) */
644 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
646 /* Auxiliary storage for the contents of the MCS surface.
648 * Since the sampler always returns 8 registers worth of data, this is 8
649 * registers wide, even though we only use the first 2 registers of it.
651 struct brw_reg mcs_data
;
653 /* X coordinates. We have two of them so that we can perform coordinate
654 * transformations easily.
656 struct brw_reg x_coords
[2];
658 /* Y coordinates. We have two of them so that we can perform coordinate
659 * transformations easily.
661 struct brw_reg y_coords
[2];
663 /* Which element of x_coords and y_coords is currently in use.
667 /* True if, at the point in the program currently being compiled, the
668 * sample index is known to be zero.
672 /* Register storing the sample index when s_is_zero is false. */
673 struct brw_reg sample_index
;
679 /* MRF used for sampling and render target writes */
683 brw_blorp_blit_program::brw_blorp_blit_program(
684 struct brw_context
*brw
,
685 const brw_blorp_blit_prog_key
*key
)
686 : mem_ctx(ralloc_context(NULL
)),
690 brw_init_compile(brw
, &func
, mem_ctx
);
693 brw_blorp_blit_program::~brw_blorp_blit_program()
695 ralloc_free(mem_ctx
);
699 brw_blorp_blit_program::compile(struct brw_context
*brw
,
700 GLuint
*program_size
)
703 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
704 /* If the destination image is W tiled and multisampled, then the thread
705 * must be dispatched once per sample, not once per pixel. This is
706 * necessary because after conversion between W and Y tiling, there's no
707 * guarantee that all samples corresponding to a single pixel will still
710 assert(key
->persample_msaa_dispatch
);
714 /* We are blending, which means we won't have an opportunity to
715 * translate the tiling and sample count for the texture surface. So
716 * the surface state for the texture must be configured with the correct
717 * tiling and sample count.
719 assert(!key
->src_tiled_w
);
720 assert(key
->tex_samples
== key
->src_samples
);
721 assert(key
->tex_layout
== key
->src_layout
);
722 assert(key
->tex_samples
> 0);
725 if (key
->persample_msaa_dispatch
) {
726 /* It only makes sense to do persample dispatch if the render target is
727 * configured as multisampled.
729 assert(key
->rt_samples
> 0);
732 /* Make sure layout is consistent with sample count */
733 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
734 (key
->tex_samples
== 0));
735 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
736 (key
->rt_samples
== 0));
737 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
738 (key
->src_samples
== 0));
739 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
740 (key
->dst_samples
== 0));
742 /* Set up prog_data */
743 memset(&prog_data
, 0, sizeof(prog_data
));
744 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
746 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
749 compute_frag_coords();
751 /* Render target and texture hardware don't support W tiling. */
752 const bool rt_tiled_w
= false;
753 const bool tex_tiled_w
= false;
755 /* The address that data will be written to is determined by the
756 * coordinates supplied to the WM thread and the tiling and sample count of
757 * the render target, according to the formula:
759 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
761 * If the actual tiling and sample count of the destination surface are not
762 * the same as the configuration of the render target, then these
763 * coordinates are wrong and we have to adjust them to compensate for the
766 if (rt_tiled_w
!= key
->dst_tiled_w
||
767 key
->rt_samples
!= key
->dst_samples
||
768 key
->rt_layout
!= key
->dst_layout
) {
769 encode_msaa(key
->rt_samples
, key
->rt_layout
);
770 /* Now (X, Y, S) = detile(rt_tiling, offset) */
771 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
772 /* Now (X, Y, S) = detile(dst_tiling, offset) */
773 decode_msaa(key
->dst_samples
, key
->dst_layout
);
776 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
778 * That is: X, Y and S now contain the true coordinates and sample index of
779 * the data that the WM thread should output.
781 * If we need to kill pixels that are outside the destination rectangle,
782 * now is the time to do it.
786 kill_if_outside_dst_rect();
788 /* Next, apply a translation to obtain coordinates in the source image. */
789 translate_dst_to_src();
791 /* If the source image is not multisampled, then we want to fetch sample
792 * number 0, because that's the only sample there is.
794 if (key
->src_samples
== 0)
797 /* X, Y, and S are now the coordinates of the pixel in the source image
798 * that we want to texture from. Exception: if we are blending, then S is
799 * irrelevant, because we are going to fetch all samples.
802 if (brw
->intel
.gen
== 6) {
803 /* Gen6 hardware an automatically blend using the SAMPLE message */
805 sample(texture_data
[0]);
807 /* Gen7+ hardware doesn't automaticaly blend. */
808 manual_blend(key
->src_samples
);
811 /* We aren't blending, which means we just want to fetch a single sample
812 * from the source surface. The address that we want to fetch from is
813 * related to the X, Y and S values according to the formula:
815 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
817 * If the actual tiling and sample count of the source surface are not
818 * the same as the configuration of the texture, then we need to adjust
819 * the coordinates to compensate for the difference.
821 if (tex_tiled_w
!= key
->src_tiled_w
||
822 key
->tex_samples
!= key
->src_samples
||
823 key
->tex_layout
!= key
->src_layout
) {
824 encode_msaa(key
->src_samples
, key
->src_layout
);
825 /* Now (X, Y, S) = detile(src_tiling, offset) */
826 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
827 /* Now (X, Y, S) = detile(tex_tiling, offset) */
828 decode_msaa(key
->tex_samples
, key
->tex_layout
);
831 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
833 * In other words: X, Y, and S now contain values which, when passed to
834 * the texturing unit, will cause data to be read from the correct
835 * memory location. So we can fetch the texel now.
837 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
839 texel_fetch(texture_data
[0]);
842 /* Finally, write the fetched (or blended) value to the render target and
843 * terminate the thread.
845 render_target_write();
847 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
848 printf("Native code for BLORP blit:\n");
849 brw_dump_compile(&func
, stdout
, 0, func
.next_insn_offset
);
852 return brw_get_program(&func
, program_size
);
856 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
858 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
859 #define ALLOC_REG(name) \
861 brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 4)
867 ALLOC_REG(x_transform
.multiplier
);
868 ALLOC_REG(x_transform
.offset
);
869 ALLOC_REG(y_transform
.multiplier
);
870 ALLOC_REG(y_transform
.offset
);
876 brw_blorp_blit_program::alloc_regs()
879 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
880 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
881 prog_data
.first_curbe_grf
= reg
;
882 alloc_push_const_regs(reg
);
883 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
884 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
885 this->texture_data
[i
] =
886 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
890 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
892 for (int i
= 0; i
< 2; ++i
) {
894 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
897 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
900 this->xy_coord_index
= 0;
902 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
904 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
906 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
909 /* Make sure we didn't run out of registers */
910 assert(reg
<= GEN7_MRF_HACK_START
);
913 this->base_mrf
= mrf
;
916 /* In the code that follows, X and Y can be used to quickly refer to the
917 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
918 * prime") to the inactive elements.
920 * S can be used to quickly refer to sample_index.
922 #define X x_coords[xy_coord_index]
923 #define Y y_coords[xy_coord_index]
924 #define Xp x_coords[!xy_coord_index]
925 #define Yp y_coords[!xy_coord_index]
926 #define S sample_index
928 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
929 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
931 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
934 * Emit code to compute the X and Y coordinates of the pixels being rendered
935 * by this WM invocation.
937 * Assuming the render target is set up for Y tiling, these (X, Y) values are
938 * related to the address offset where outputs will be written by the formula:
940 * (X, Y, S) = decode_msaa(detile(offset)).
942 * (See brw_blorp_blit_program).
945 brw_blorp_blit_program::compute_frag_coords()
947 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
948 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
949 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
950 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
952 * Pixels within a subspan are laid out in this arrangement:
956 * So, to compute the coordinates of each pixel, we need to read every 2nd
957 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
958 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
959 * In other words, the data we want to access is R1.4<2;4,0>UW.
961 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
962 * result, since pixels n+1 and n+3 are in the right half of the subspan.
964 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
965 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
967 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
968 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
969 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
972 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
973 * pixels n+2 and n+3 are in the bottom half of the subspan.
975 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
976 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
978 /* Move the coordinates to UD registers. */
979 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
980 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
983 if (key
->persample_msaa_dispatch
) {
984 switch (key
->rt_samples
) {
986 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
987 * Therefore, subspan 0 will represent sample 0, subspan 1 will
988 * represent sample 1, and so on.
990 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
991 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
992 * populate a temporary variable with the sequence (0, 1, 2, 3), and
993 * then copy from it using vstride=1, width=4, hstride=0.
995 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
996 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
997 /* Move to UD sample_index register. */
998 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
999 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1003 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1004 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1005 * subspan 1 will represent sample 1, and so on. We can find the
1006 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1007 * Index") and multiplying by two (since samples are always delivered
1008 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1011 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1012 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1013 * variable with the sequence (0, 1, 2, 3), and then reading from it
1014 * using vstride=1, width=4, hstride=0.
1016 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1017 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1018 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1019 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1020 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1021 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1022 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1023 stride(t2_uw1
, 1, 4, 0));
1024 brw_ADD(&func
, offset(S
, 1),
1025 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1026 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1030 assert(!"Unrecognized sample count in "
1031 "brw_blorp_blit_program::compute_frag_coords()");
1036 /* Either the destination surface is single-sampled, or the WM will be
1037 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1038 * per pixel). In either case, it's not meaningful to compute a sample
1039 * value. Just set it to 0.
1046 * Emit code to compensate for the difference between Y and W tiling.
1048 * This code modifies the X and Y coordinates according to the formula:
1050 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1052 * (See brw_blorp_blit_program).
1054 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1055 * are booleans where true represents W tiling and false represents Y tiling.
1058 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1060 if (old_tiled_w
== new_tiled_w
)
1063 /* In the code that follows, we can safely assume that S = 0, because W
1064 * tiling formats always use IMS layout.
1068 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1070 /* Given X and Y coordinates that describe an address using Y tiling,
1071 * translate to the X and Y coordinates that describe the same address
1074 * If we break down the low order bits of X and Y, using a
1075 * single letter to represent each low-order bit:
1077 * X = A << 7 | 0bBCDEFGH
1078 * Y = J << 5 | 0bKLMNP (1)
1080 * Then we can apply the Y tiling formula to see the memory offset being
1083 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1085 * If we apply the W detiling formula to this memory location, that the
1086 * corresponding X' and Y' coordinates are:
1088 * X' = A << 6 | 0bBCDPFH (3)
1089 * Y' = J << 6 | 0bKLMNEG
1091 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1092 * we need to make the following computation:
1094 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1095 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1097 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1098 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1099 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1100 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1101 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1102 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1103 brw_OR(&func
, Xp
, t1
, t2
);
1104 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1105 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1106 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1107 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1108 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1109 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1110 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1111 brw_OR(&func
, Yp
, t1
, t2
);
1114 /* Applying the same logic as above, but in reverse, we obtain the
1117 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1118 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1120 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1121 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1122 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1123 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1124 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1125 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1126 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1127 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1129 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1130 brw_OR(&func
, Xp
, t1
, t2
);
1131 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1132 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1133 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1134 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1135 brw_OR(&func
, Yp
, t1
, t2
);
1138 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1142 * Emit code to compensate for the difference between MSAA and non-MSAA
1145 * This code modifies the X and Y coordinates according to the formula:
1147 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1149 * (See brw_blorp_blit_program).
1152 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1153 intel_msaa_layout layout
)
1155 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1157 case INTEL_MSAA_LAYOUT_NONE
:
1158 /* No translation necessary, and S should already be zero. */
1161 case INTEL_MSAA_LAYOUT_CMS
:
1162 /* We can't compensate for compressed layout since at this point in the
1163 * program we haven't read from the MCS buffer.
1165 assert(!"Bad layout in encode_msaa");
1167 case INTEL_MSAA_LAYOUT_UMS
:
1168 /* No translation necessary. */
1170 case INTEL_MSAA_LAYOUT_IMS
:
1171 switch (num_samples
) {
1173 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1174 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1175 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1177 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1179 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1180 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1182 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1184 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1185 brw_OR(&func
, Xp
, t1
, t2
);
1186 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1187 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1189 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1190 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1192 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1193 brw_OR(&func
, Yp
, t1
, t2
);
1196 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1197 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1199 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1201 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1202 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1204 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1205 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1206 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1207 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1208 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1211 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1212 brw_OR(&func
, Xp
, t1
, t2
);
1213 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1214 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1216 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1217 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1219 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1220 brw_OR(&func
, Yp
, t1
, t2
);
1227 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1231 * Emit code to compensate for the difference between MSAA and non-MSAA
1234 * This code modifies the X and Y coordinates according to the formula:
1236 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1238 * (See brw_blorp_blit_program).
1241 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1242 intel_msaa_layout layout
)
1244 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1246 case INTEL_MSAA_LAYOUT_NONE
:
1247 /* No translation necessary, and S should already be zero. */
1250 case INTEL_MSAA_LAYOUT_CMS
:
1251 /* We can't compensate for compressed layout since at this point in the
1252 * program we don't have access to the MCS buffer.
1254 assert(!"Bad layout in encode_msaa");
1256 case INTEL_MSAA_LAYOUT_UMS
:
1257 /* No translation necessary. */
1259 case INTEL_MSAA_LAYOUT_IMS
:
1261 switch (num_samples
) {
1263 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1264 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1265 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1266 * S = (Y & 0b10) | (X & 0b10) >> 1
1268 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1269 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1270 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1271 brw_OR(&func
, Xp
, t1
, t2
);
1272 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1273 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1274 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1275 brw_OR(&func
, Yp
, t1
, t2
);
1276 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1277 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1278 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1279 brw_OR(&func
, S
, t1
, t2
);
1282 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1283 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1284 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1285 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1287 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1288 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1289 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1290 brw_OR(&func
, Xp
, t1
, t2
);
1291 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1292 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1293 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1294 brw_OR(&func
, Yp
, t1
, t2
);
1295 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1296 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1297 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1298 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1299 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1300 brw_OR(&func
, S
, t1
, t2
);
1307 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1311 * Emit code that kills pixels whose X and Y coordinates are outside the
1312 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1316 brw_blorp_blit_program::kill_if_outside_dst_rect()
1318 struct brw_reg f0
= brw_flag_reg(0, 0);
1319 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1320 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1322 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1323 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1324 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1325 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1327 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1328 brw_push_insn_state(&func
);
1329 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1330 brw_AND(&func
, g1
, f0
, g1
);
1331 brw_pop_insn_state(&func
);
1335 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1339 brw_blorp_blit_program::translate_dst_to_src()
1341 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1342 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1343 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1344 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1346 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1347 /* Move the UD coordinates to float registers. */
1348 brw_MOV(&func
, Xp_f
, X
);
1349 brw_MOV(&func
, Yp_f
, Y
);
1350 /* Scale and offset */
1351 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1352 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1353 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1354 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1355 /* Round the float coordinates down to nearest integer by moving to
1358 brw_MOV(&func
, Xp
, X_f
);
1359 brw_MOV(&func
, Yp
, Y_f
);
1361 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1365 * Emit code to transform the X and Y coordinates as needed for blending
1366 * together the different samples in an MSAA texture.
1369 brw_blorp_blit_program::single_to_blend()
1371 /* When looking up samples in an MSAA texture using the SAMPLE message,
1372 * Gen6 requires the texture coordinates to be odd integers (so that they
1373 * correspond to the center of a 2x2 block representing the four samples
1374 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1375 * each by 2 and then add 1.
1377 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1378 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1379 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1380 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1381 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1382 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1388 * Count the number of trailing 1 bits in the given value. For example:
1390 * count_trailing_one_bits(0) == 0
1391 * count_trailing_one_bits(7) == 3
1392 * count_trailing_one_bits(11) == 2
1394 inline int count_trailing_one_bits(unsigned value
)
1396 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1397 return __builtin_ctz(~value
);
1399 return _mesa_bitcount(value
& ~(value
+ 1));
1405 brw_blorp_blit_program::manual_blend(unsigned num_samples
)
1407 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1410 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1412 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1414 * This ensures that when all samples have the same value, no numerical
1415 * precision is lost, since each addition operation always adds two equal
1416 * values, and summing two equal floating point values does not lose
1419 * We perform this computation by treating the texture_data array as a
1420 * stack and performing the following operations:
1422 * - push sample 0 onto stack
1423 * - push sample 1 onto stack
1424 * - add top two stack entries
1425 * - push sample 2 onto stack
1426 * - push sample 3 onto stack
1427 * - add top two stack entries
1428 * - add top two stack entries
1429 * - divide top stack entry by 4
1431 * Note that after pushing sample i onto the stack, the number of add
1432 * operations we do is equal to the number of trailing 1 bits in i. This
1433 * works provided the total number of samples is a power of two, which it
1434 * always is for i965.
1436 * For integer formats, we replace the add operations with average
1437 * operations and skip the final division.
1439 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1443 brw_op2_ptr combine_op
=
1444 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1445 unsigned stack_depth
= 0;
1446 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1447 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1449 /* Push sample i onto the stack */
1450 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1455 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1457 texel_fetch(texture_data
[stack_depth
++]);
1459 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1460 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1461 * suggests an optimization:
1463 * "A simple optimization with probable large return in
1464 * performance is to compare the MCS value to zero (indicating
1465 * all samples are on sample slice 0), and sample only from
1466 * sample slice 0 using ld2dss if MCS is zero."
1468 * Note that in the case where the MCS value is zero, sampling from
1469 * sample slice 0 using ld2dss and sampling from sample 0 using
1470 * ld2dms are equivalent (since all samples are on sample slice 0).
1471 * Since we have already sampled from sample 0, all we need to do is
1472 * skip the remaining fetches and averaging if MCS is zero.
1474 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1475 mcs_data
, brw_imm_ud(0));
1476 brw_IF(&func
, BRW_EXECUTE_16
);
1479 /* Do count_trailing_one_bits(i) times */
1480 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1481 assert(stack_depth
>= 2);
1484 /* TODO: should use a smaller loop bound for non_RGBA formats */
1485 for (int k
= 0; k
< 4; ++k
) {
1486 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1487 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1488 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1493 /* We should have just 1 sample on the stack now. */
1494 assert(stack_depth
== 1);
1496 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1497 /* Scale the result down by a factor of num_samples */
1498 /* TODO: should use a smaller loop bound for non-RGBA formats */
1499 for (int j
= 0; j
< 4; ++j
) {
1500 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1501 offset(vec8(texture_data
[0]), 2*j
),
1502 brw_imm_f(1.0/num_samples
));
1506 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1511 * Emit code to look up a value in the texture using the SAMPLE message (which
1512 * does blending of MSAA surfaces).
1515 brw_blorp_blit_program::sample(struct brw_reg dst
)
1517 static const sampler_message_arg args
[2] = {
1518 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1519 SAMPLER_MESSAGE_ARG_V_FLOAT
1522 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
, ARRAY_SIZE(args
));
1526 * Emit code to look up a value in the texture using the SAMPLE_LD message
1527 * (which does a simple texel fetch).
1530 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1532 static const sampler_message_arg gen6_args
[5] = {
1533 SAMPLER_MESSAGE_ARG_U_INT
,
1534 SAMPLER_MESSAGE_ARG_V_INT
,
1535 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1536 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1537 SAMPLER_MESSAGE_ARG_SI_INT
1539 static const sampler_message_arg gen7_ld_args
[3] = {
1540 SAMPLER_MESSAGE_ARG_U_INT
,
1541 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1542 SAMPLER_MESSAGE_ARG_V_INT
1544 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1545 SAMPLER_MESSAGE_ARG_SI_INT
,
1546 SAMPLER_MESSAGE_ARG_U_INT
,
1547 SAMPLER_MESSAGE_ARG_V_INT
1549 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1550 SAMPLER_MESSAGE_ARG_SI_INT
,
1551 SAMPLER_MESSAGE_ARG_MCS_INT
,
1552 SAMPLER_MESSAGE_ARG_U_INT
,
1553 SAMPLER_MESSAGE_ARG_V_INT
1556 switch (brw
->intel
.gen
) {
1558 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1562 switch (key
->tex_layout
) {
1563 case INTEL_MSAA_LAYOUT_IMS
:
1564 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1567 * If this field is MSFMT_DEPTH_STENCIL
1568 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1569 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1571 * So fall through to emit the same message as we use for
1572 * INTEL_MSAA_LAYOUT_CMS.
1574 case INTEL_MSAA_LAYOUT_CMS
:
1575 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1576 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1578 case INTEL_MSAA_LAYOUT_UMS
:
1579 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1580 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1582 case INTEL_MSAA_LAYOUT_NONE
:
1584 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1585 ARRAY_SIZE(gen7_ld_args
));
1590 assert(!"Should not get here.");
1596 brw_blorp_blit_program::mcs_fetch()
1598 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1599 SAMPLER_MESSAGE_ARG_U_INT
,
1600 SAMPLER_MESSAGE_ARG_V_INT
1602 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1603 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1607 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1609 const sampler_message_arg
*args
,
1612 struct brw_reg mrf
=
1613 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1614 for (int arg
= 0; arg
< num_args
; ++arg
) {
1615 switch (args
[arg
]) {
1616 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1617 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1619 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1620 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1622 case SAMPLER_MESSAGE_ARG_U_INT
:
1623 brw_MOV(&func
, mrf
, X
);
1625 case SAMPLER_MESSAGE_ARG_V_INT
:
1626 brw_MOV(&func
, mrf
, Y
);
1628 case SAMPLER_MESSAGE_ARG_SI_INT
:
1629 /* Note: on Gen7, this code may be reached with s_is_zero==true
1630 * because in Gen7's ld2dss message, the sample index is the first
1631 * argument. When this happens, we need to move a 0 into the
1632 * appropriate message register.
1635 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1637 brw_MOV(&func
, mrf
, S
);
1639 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1640 switch (key
->tex_layout
) {
1641 case INTEL_MSAA_LAYOUT_CMS
:
1642 brw_MOV(&func
, mrf
, mcs_data
);
1644 case INTEL_MSAA_LAYOUT_IMS
:
1645 /* When sampling from an IMS surface, MCS data is not relevant,
1646 * and the hardware ignores it. So don't bother populating it.
1650 /* We shouldn't be trying to send MCS data with any other
1653 assert (!"Unsupported layout for MCS data");
1657 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1658 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1665 retype(dst
, BRW_REGISTER_TYPE_F
) /* dest */,
1666 base_mrf
/* msg_reg_nr */,
1667 brw_message_reg(base_mrf
) /* src0 */,
1668 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1671 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1672 mrf
.nr
- base_mrf
/* msg_length */,
1673 0 /* header_present */,
1674 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1675 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1683 #undef SWAP_XY_AND_XPYP
1686 brw_blorp_blit_program::render_target_write()
1688 struct brw_reg mrf_rt_write
=
1689 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1692 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1693 * so that the render target knows which pixels we killed.
1695 bool use_header
= key
->use_kill
;
1697 /* Copy R0/1 to MRF */
1698 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1699 retype(R0
, BRW_REGISTER_TYPE_UD
));
1703 /* Copy texture data to MRFs */
1704 for (int i
= 0; i
< 4; ++i
) {
1705 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1706 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1707 offset(vec8(texture_data
[0]), 2*i
));
1711 /* Now write to the render target and terminate the thread */
1713 16 /* dispatch_width */,
1714 base_mrf
/* msg_reg_nr */,
1715 mrf_rt_write
/* src0 */,
1716 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1717 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1718 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1719 0 /* response_length */,
1726 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1727 GLfloat dst0
, GLfloat dst1
,
1730 float scale
= (src1
- src0
) / (dst1
- dst0
);
1732 /* When not mirroring a coordinate (say, X), we need:
1733 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1735 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1737 * blorp program uses "round toward zero" to convert the
1738 * transformed floating point coordinates to integer coordinates,
1739 * whereas the behaviour we actually want is "round to nearest",
1740 * so 0.5 provides the necessary correction.
1743 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1745 /* When mirroring X we need:
1746 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1748 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1750 multiplier
= -scale
;
1751 offset
= src0
+ (dst1
- 0.5) * scale
;
1757 * Determine which MSAA layout the GPU pipeline should be configured for,
1758 * based on the chip generation, the number of samples, and the true layout of
1759 * the image in memory.
1761 inline intel_msaa_layout
1762 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1763 intel_msaa_layout true_layout
)
1765 if (num_samples
<= 1) {
1766 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1767 * format buffers, by transforming coordinates appropriately.
1769 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1770 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1771 return INTEL_MSAA_LAYOUT_NONE
;
1773 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1776 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1777 if (brw
->intel
.gen
== 6) {
1778 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1785 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1786 struct intel_mipmap_tree
*src_mt
,
1787 unsigned src_level
, unsigned src_layer
,
1788 struct intel_mipmap_tree
*dst_mt
,
1789 unsigned dst_level
, unsigned dst_layer
,
1790 GLfloat src_x0
, GLfloat src_y0
,
1791 GLfloat src_x1
, GLfloat src_y1
,
1792 GLfloat dst_x0
, GLfloat dst_y0
,
1793 GLfloat dst_x1
, GLfloat dst_y1
,
1794 bool mirror_x
, bool mirror_y
)
1796 src
.set(brw
, src_mt
, src_level
, src_layer
);
1797 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
);
1799 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1802 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1804 /* texture_data_type indicates the register type that should be used to
1805 * manipulate texture data.
1807 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1808 case GL_UNSIGNED_NORMALIZED
:
1809 case GL_SIGNED_NORMALIZED
:
1811 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1813 case GL_UNSIGNED_INT
:
1814 if (src_mt
->format
== MESA_FORMAT_S8
) {
1815 /* We process stencil as though it's an unsigned normalized color */
1816 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1818 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1822 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1825 assert(!"Unrecognized blorp format");
1829 if (brw
->intel
.gen
> 6) {
1830 /* Gen7's rendering hardware only supports the IMS layout for depth and
1831 * stencil render targets. Blorp always maps its destination surface as
1832 * a color render target (even if it's actually a depth or stencil
1833 * buffer). So if the destination is IMS, we'll have to map it as a
1834 * single-sampled texture and interleave the samples ourselves.
1836 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1837 dst
.num_samples
= 0;
1840 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1841 /* If the destination surface is a W-tiled multisampled stencil buffer
1842 * that we're mapping as Y tiled, then we need to arrange for the WM
1843 * program to run once per sample rather than once per pixel, because
1844 * the memory layout of related samples doesn't match between W and Y
1847 wm_prog_key
.persample_msaa_dispatch
= true;
1850 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1851 /* We are blitting from a multisample buffer to a multisample buffer, so
1852 * we must preserve samples within a pixel. This means we have to
1853 * arrange for the WM program to run once per sample rather than once
1856 wm_prog_key
.persample_msaa_dispatch
= true;
1859 /* The render path must be configured to use the same number of samples as
1860 * the destination buffer.
1862 num_samples
= dst
.num_samples
;
1864 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1865 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1866 base_format
!= GL_STENCIL_INDEX
&&
1867 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1868 /* We are downsampling a color buffer, so blend. */
1869 wm_prog_key
.blend
= true;
1872 /* src_samples and dst_samples are the true sample counts */
1873 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1874 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1876 /* tex_samples and rt_samples are the sample counts that are set up in
1879 wm_prog_key
.tex_samples
= src
.num_samples
;
1880 wm_prog_key
.rt_samples
= dst
.num_samples
;
1882 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1883 * use to access the source and destination surfaces.
1885 wm_prog_key
.tex_layout
=
1886 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1887 wm_prog_key
.rt_layout
=
1888 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1890 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1893 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1894 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1896 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1897 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1898 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1899 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1900 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1901 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1902 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
1903 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
1905 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
1906 /* We must expand the rectangle we send through the rendering pipeline,
1907 * to account for the fact that we are mapping the destination region as
1908 * single-sampled when it is in fact multisampled. We must also align
1909 * it to a multiple of the multisampling pattern, because the
1910 * differences between multisampled and single-sampled surface formats
1911 * will mean that pixels are scrambled within the multisampling pattern.
1912 * TODO: what if this makes the coordinates too large?
1914 * Note: this only works if the destination surface uses the IMS layout.
1915 * If it's UMS, then we have no choice but to set up the rendering
1916 * pipeline as multisampled.
1918 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
1919 switch (dst_mt
->num_samples
) {
1921 x0
= ROUND_DOWN_TO(x0
* 2, 4);
1922 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1923 x1
= ALIGN(x1
* 2, 4);
1924 y1
= ALIGN(y1
* 2, 4);
1927 x0
= ROUND_DOWN_TO(x0
* 4, 8);
1928 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1929 x1
= ALIGN(x1
* 4, 8);
1930 y1
= ALIGN(y1
* 2, 4);
1933 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
1936 wm_prog_key
.use_kill
= true;
1939 if (dst
.map_stencil_as_y_tiled
) {
1940 /* We must modify the rectangle we send through the rendering pipeline
1941 * (and the size and x/y offset of the destination surface), to account
1942 * for the fact that we are mapping it as Y-tiled when it is in fact
1945 * Both Y tiling and W tiling can be understood as organizations of
1946 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
1947 * is different, but the layout of the 32-byte sub-tiles within the 4k
1948 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
1949 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
1950 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
1952 * Therefore, to account for the layout differences within the 32-byte
1953 * sub-tiles, we must expand the rectangle so the X coordinates of its
1954 * edges are multiples of 8 (the W sub-tile width), and its Y
1955 * coordinates of its edges are multiples of 4 (the W sub-tile height).
1956 * Then we need to scale the X and Y coordinates of the rectangle to
1957 * account for the differences in aspect ratio between the Y and W
1958 * sub-tiles. We need to modify the layer width and height similarly.
1960 * A correction needs to be applied when MSAA is in use: since
1961 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
1962 * we need to align the Y coordinates to multiples of 8, so that when
1963 * they are divided by two they are still multiples of 4.
1965 * Note: Since the x/y offset of the surface will be applied using the
1966 * SURFACE_STATE command packet, it will be invisible to the swizzling
1967 * code in the shader; therefore it needs to be in a multiple of the
1968 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
1969 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
1970 * buffer), and the miplevel alignment used for stencil buffers is 8
1971 * pixels horizontally and either 4 or 8 pixels vertically (see
1972 * intel_horizontal_texture_alignment_unit() and
1973 * intel_vertical_texture_alignment_unit()).
1975 * Note: Also, since the SURFACE_STATE command packet can only apply
1976 * offsets that are multiples of 4 pixels horizontally and 2 pixels
1977 * vertically, it is important that the offsets will be multiples of
1978 * these sizes after they are converted into Y-tiled coordinates.
1979 * Fortunately they will be, since we know from above that the offsets
1980 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
1981 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
1983 * TODO: what if this makes the coordinates (or the texture size) too
1986 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
1987 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
1988 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
1989 x1
= ALIGN(x1
, x_align
) * 2;
1990 y1
= ALIGN(y1
, y_align
) / 2;
1991 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
1992 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
1995 wm_prog_key
.use_kill
= true;
1998 if (src
.map_stencil_as_y_tiled
) {
1999 /* We must modify the size and x/y offset of the source surface to
2000 * account for the fact that we are mapping it as Y-tiled when it is in
2003 * See the comments above concerning x/y offset alignment for the
2004 * destination surface.
2006 * TODO: what if this makes the texture size too large?
2008 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2009 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2010 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2017 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2018 brw_blorp_prog_data
**prog_data
) const
2020 uint32_t prog_offset
;
2021 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2022 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2023 &prog_offset
, prog_data
)) {
2024 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2025 GLuint program_size
;
2026 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2027 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2028 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2029 program
, program_size
,
2030 &prog
.prog_data
, sizeof(prog
.prog_data
),
2031 &prog_offset
, prog_data
);