2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
26 #include "glsl/ralloc.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
33 #include "brw_state.h"
37 * Helper function for handling mirror image blits.
39 * If coord0 > coord1, swap them and invert the "mirror" boolean.
42 fixup_mirroring(bool &mirror
, GLint
&coord0
, GLint
&coord1
)
44 if (coord0
> coord1
) {
54 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
55 * destination coordinates.
57 * Return true if there is still blitting to do, false if all pixels got
58 * rejected by the clip and/or scissor.
60 * For clarity, the nomenclature of this function assumes we are clipping and
61 * scissoring the X coordinate; the exact same logic applies for Y
64 * Note: this function may also be used to account for clipping of source
65 * coordinates, by swapping the roles of src and dst.
68 clip_or_scissor(bool mirror
, GLint
&src_x0
, GLint
&src_x1
, GLint
&dst_x0
,
69 GLint
&dst_x1
, GLint fb_xmin
, GLint fb_xmax
)
71 /* If we are going to scissor everything away, stop. */
72 if (!(fb_xmin
< fb_xmax
&&
79 /* Clip the destination rectangle, and keep track of how many pixels we
80 * clipped off of the left and right sides of it.
82 GLint pixels_clipped_left
= 0;
83 GLint pixels_clipped_right
= 0;
84 if (dst_x0
< fb_xmin
) {
85 pixels_clipped_left
= fb_xmin
- dst_x0
;
88 if (fb_xmax
< dst_x1
) {
89 pixels_clipped_right
= dst_x1
- fb_xmax
;
93 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
94 * the source coordinates, we need to flip them to account for the
98 GLint tmp
= pixels_clipped_left
;
99 pixels_clipped_left
= pixels_clipped_right
;
100 pixels_clipped_right
= tmp
;
103 /* Adjust the source rectangle to remove the pixels corresponding to those
104 * that were clipped/scissored out of the destination rectangle.
106 src_x0
+= pixels_clipped_left
;
107 src_x1
-= pixels_clipped_right
;
114 try_blorp_blit(struct intel_context
*intel
,
115 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
116 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
117 GLenum filter
, GLbitfield buffer_bit
)
119 struct gl_context
*ctx
= &intel
->ctx
;
121 /* Sync up the state of window system buffers. We need to do this before
122 * we go looking for the buffers.
124 intel_prepare_render(intel
);
127 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
128 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
129 struct gl_renderbuffer
*src_rb
;
130 struct gl_renderbuffer
*dst_rb
;
131 switch (buffer_bit
) {
132 case GL_COLOR_BUFFER_BIT
:
133 src_rb
= read_fb
->_ColorReadBuffer
;
136 draw_fb
->_ColorDrawBufferIndexes
[0]].Renderbuffer
;
138 case GL_DEPTH_BUFFER_BIT
:
139 src_rb
= read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
140 dst_rb
= draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
142 case GL_STENCIL_BUFFER_BIT
:
143 src_rb
= read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
144 dst_rb
= draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
150 /* Validate source */
151 if (!src_rb
) return false;
152 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
153 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
154 if (!src_mt
) return false;
155 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& src_mt
->stencil_mt
)
156 src_mt
= src_mt
->stencil_mt
;
158 /* Validate destination */
159 if (!dst_rb
) return false;
160 struct intel_renderbuffer
*dst_irb
= intel_renderbuffer(dst_rb
);
161 struct intel_mipmap_tree
*dst_mt
= dst_irb
->mt
;
162 if (!dst_mt
) return false;
163 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& dst_mt
->stencil_mt
)
164 dst_mt
= dst_mt
->stencil_mt
;
166 /* Blorp blits can't translate from one format to another. For that we'll
167 * have to fall back to the meta-op blit. Note: the meta-op blit doesn't
168 * support multisampled blits, but fortunately this is ok because
169 * multisampled blits require identical source and destination formats.
171 if (src_mt
->format
!= dst_mt
->format
)
174 /* Account for the fact that in the system framebuffer, the origin is at
177 if (read_fb
->Name
== 0) {
178 srcY0
= read_fb
->Height
- srcY0
;
179 srcY1
= read_fb
->Height
- srcY1
;
181 if (draw_fb
->Name
== 0) {
182 dstY0
= draw_fb
->Height
- dstY0
;
183 dstY1
= draw_fb
->Height
- dstY1
;
186 /* Detect if the blit needs to be mirrored */
187 bool mirror_x
= false, mirror_y
= false;
188 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
189 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
190 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
191 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
193 /* Make sure width and height match */
194 GLsizei width
= srcX1
- srcX0
;
195 GLsizei height
= srcY1
- srcY0
;
196 if (width
!= dstX1
- dstX0
) return false;
197 if (height
!= dstY1
- dstY0
) return false;
199 /* If the destination rectangle needs to be clipped or scissored, do so.
201 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
202 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
203 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
204 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
205 /* Everything got clipped/scissored away, so the blit was successful. */
209 /* If the source rectangle needs to be clipped or scissored, do so. */
210 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
211 0, read_fb
->Width
) &&
212 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
213 0, read_fb
->Height
))) {
214 /* Everything got clipped/scissored away, so the blit was successful. */
218 /* Get ready to blit. This includes depth resolving the src and dst
219 * buffers if necessary.
221 intel_renderbuffer_resolve_depth(intel
, src_irb
);
222 intel_renderbuffer_resolve_depth(intel
, dst_irb
);
225 brw_blorp_blit_params
params(brw_context(ctx
), src_mt
, dst_mt
,
226 srcX0
, srcY0
, dstX0
, dstY0
, dstX1
, dstY1
,
228 brw_blorp_exec(intel
, ¶ms
);
230 /* Mark the dst buffer as needing a HiZ resolve if necessary. */
231 intel_renderbuffer_set_needs_hiz_resolve(dst_irb
);
237 brw_blorp_framebuffer(struct intel_context
*intel
,
238 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
239 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
240 GLbitfield mask
, GLenum filter
)
242 /* BLORP is not supported before Gen6. */
246 static GLbitfield buffer_bits
[] = {
249 GL_STENCIL_BUFFER_BIT
,
252 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
253 if ((mask
& buffer_bits
[i
]) &&
254 try_blorp_blit(intel
,
255 srcX0
, srcY0
, srcX1
, srcY1
,
256 dstX0
, dstY0
, dstX1
, dstY1
,
257 filter
, buffer_bits
[i
])) {
258 mask
&= ~buffer_bits
[i
];
267 * Enum to specify the order of arguments in a sampler message
269 enum sampler_message_arg
271 SAMPLER_MESSAGE_ARG_U_FLOAT
,
272 SAMPLER_MESSAGE_ARG_V_FLOAT
,
273 SAMPLER_MESSAGE_ARG_U_INT
,
274 SAMPLER_MESSAGE_ARG_V_INT
,
275 SAMPLER_MESSAGE_ARG_SI_INT
,
276 SAMPLER_MESSAGE_ARG_ZERO_INT
,
280 * Generator for WM programs used in BLORP blits.
282 * The bulk of the work done by the WM program is to wrap and unwrap the
283 * coordinate transformations used by the hardware to store surfaces in
284 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
285 * sample index for a multisampled surface) to a memory offset by the
286 * following formulas:
288 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
289 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
291 * For a single-sampled surface, or for a multisampled surface using
292 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
295 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
296 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
297 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
298 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
300 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
301 * embeds the sample number into bit 1 of the X and Y coordinates:
303 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
304 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
305 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
306 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
307 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
308 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
309 * S = (Y & 0b10) | (X & 0b10) >> 1
311 * For X tiling, tile() combines together the low-order bits of the X and Y
312 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
313 * bytes wide and 8 rows high:
315 * tile(x_tiled, X, Y, S) = A
316 * where A = tile_num << 12 | offset
317 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
318 * offset = (Y' & 0b111) << 9
319 * | (X & 0b111111111)
321 * Y' = Y + S * qpitch
322 * detile(x_tiled, A) = (X, Y, S)
326 * Y' = (tile_num / tile_pitch) << 3
327 * | (A & 0b111000000000) >> 9
328 * X' = (tile_num % tile_pitch) << 9
329 * | (A & 0b111111111)
331 * (In all tiling formulas, cpp is the number of bytes occupied by a single
332 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
333 * to fill the width of the surface, and qpitch is the spacing (in rows)
334 * between array slices).
336 * For Y tiling, tile() combines together the low-order bits of the X and Y
337 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
338 * bytes wide and 32 rows high:
340 * tile(y_tiled, X, Y, S) = A
341 * where A = tile_num << 12 | offset
342 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
343 * offset = (X' & 0b1110000) << 5
344 * | (Y' & 0b11111) << 4
347 * Y' = Y + S * qpitch
348 * detile(y_tiled, A) = (X, Y, S)
352 * Y' = (tile_num / tile_pitch) << 5
353 * | (A & 0b111110000) >> 4
354 * X' = (tile_num % tile_pitch) << 7
355 * | (A & 0b111000000000) >> 5
358 * For W tiling, tile() combines together the low-order bits of the X and Y
359 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
360 * bytes wide and 64 rows high (note that W tiling is only used for stencil
361 * buffers, which always have cpp = 1 and S=0):
363 * tile(w_tiled, X, Y, S) = A
364 * where A = tile_num << 12 | offset
365 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
366 * offset = (X' & 0b111000) << 6
367 * | (Y' & 0b111100) << 3
368 * | (X' & 0b100) << 2
374 * Y' = Y + S * qpitch
375 * detile(w_tiled, A) = (X, Y, S)
376 * where X = X' / cpp = X'
377 * Y = Y' % qpitch = Y'
379 * Y' = (tile_num / tile_pitch) << 6
380 * | (A & 0b111100000) >> 3
381 * | (A & 0b1000) >> 2
383 * X' = (tile_num % tile_pitch) << 6
384 * | (A & 0b111000000000) >> 6
385 * | (A & 0b10000) >> 2
389 * Finally, for a non-tiled surface, tile() simply combines together the X and
390 * Y coordinates in the natural way:
392 * tile(untiled, X, Y, S) = A
393 * where A = Y * pitch + X'
395 * Y' = Y + S * qpitch
396 * detile(untiled, A) = (X, Y, S)
403 * (In these formulas, pitch is the number of bytes occupied by a single row
406 class brw_blorp_blit_program
409 brw_blorp_blit_program(struct brw_context
*brw
,
410 const brw_blorp_blit_prog_key
*key
);
411 ~brw_blorp_blit_program();
413 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
415 brw_blorp_prog_data prog_data
;
419 void alloc_push_const_regs(int base_reg
);
420 void compute_frag_coords();
421 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
422 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
423 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
424 void kill_if_outside_dst_rect();
425 void translate_dst_to_src();
426 void single_to_blend();
428 void sample(struct brw_reg dst
);
429 void texel_fetch(struct brw_reg dst
);
430 void expand_to_32_bits(struct brw_reg src
, struct brw_reg dst
);
431 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
432 const sampler_message_arg
*args
, int num_args
);
433 void render_target_write();
436 struct brw_context
*brw
;
437 const brw_blorp_blit_prog_key
*key
;
438 struct brw_compile func
;
440 /* Thread dispatch header */
443 /* Pixel X/Y coordinates (always in R1). */
447 struct brw_reg dst_x0
;
448 struct brw_reg dst_x1
;
449 struct brw_reg dst_y0
;
450 struct brw_reg dst_y1
;
452 struct brw_reg multiplier
;
453 struct brw_reg offset
;
454 } x_transform
, y_transform
;
456 /* Data to be written to render target (4 vec16's) */
457 struct brw_reg result
;
459 /* Auxiliary storage for data returned by a sampling operation when
460 * blending (4 vec16's)
462 struct brw_reg texture_data
;
464 /* X coordinates. We have two of them so that we can perform coordinate
465 * transformations easily.
467 struct brw_reg x_coords
[2];
469 /* Y coordinates. We have two of them so that we can perform coordinate
470 * transformations easily.
472 struct brw_reg y_coords
[2];
474 /* Which element of x_coords and y_coords is currently in use.
478 /* True if, at the point in the program currently being compiled, the
479 * sample index is known to be zero.
483 /* Register storing the sample index when s_is_zero is false. */
484 struct brw_reg sample_index
;
490 /* MRF used for sampling and render target writes */
494 brw_blorp_blit_program::brw_blorp_blit_program(
495 struct brw_context
*brw
,
496 const brw_blorp_blit_prog_key
*key
)
497 : mem_ctx(ralloc_context(NULL
)),
501 brw_init_compile(brw
, &func
, mem_ctx
);
504 brw_blorp_blit_program::~brw_blorp_blit_program()
506 ralloc_free(mem_ctx
);
510 brw_blorp_blit_program::compile(struct brw_context
*brw
,
511 GLuint
*program_size
)
514 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
515 /* If the destination image is W tiled and multisampled, then the thread
516 * must be dispatched once per sample, not once per pixel. This is
517 * necessary because after conversion between W and Y tiling, there's no
518 * guarantee that all samples corresponding to a single pixel will still
521 assert(key
->persample_msaa_dispatch
);
525 /* We are blending, which means we won't have an opportunity to
526 * translate the tiling and sample count for the texture surface. So
527 * the surface state for the texture must be configured with the correct
528 * tiling and sample count.
530 assert(!key
->src_tiled_w
);
531 assert(key
->tex_samples
== key
->src_samples
);
532 assert(key
->tex_layout
== key
->src_layout
);
533 assert(key
->tex_samples
> 0);
536 if (key
->persample_msaa_dispatch
) {
537 /* It only makes sense to do persample dispatch if the render target is
538 * configured as multisampled.
540 assert(key
->rt_samples
> 0);
543 /* Make sure layout is consistent with sample count */
544 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
545 (key
->tex_samples
== 0));
546 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
547 (key
->rt_samples
== 0));
548 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
549 (key
->src_samples
== 0));
550 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
551 (key
->dst_samples
== 0));
553 /* Set up prog_data */
554 memset(&prog_data
, 0, sizeof(prog_data
));
555 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
557 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
560 compute_frag_coords();
562 /* Render target and texture hardware don't support W tiling. */
563 const bool rt_tiled_w
= false;
564 const bool tex_tiled_w
= false;
566 /* The address that data will be written to is determined by the
567 * coordinates supplied to the WM thread and the tiling and sample count of
568 * the render target, according to the formula:
570 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
572 * If the actual tiling and sample count of the destination surface are not
573 * the same as the configuration of the render target, then these
574 * coordinates are wrong and we have to adjust them to compensate for the
577 if (rt_tiled_w
!= key
->dst_tiled_w
||
578 key
->rt_samples
!= key
->dst_samples
||
579 key
->rt_layout
!= key
->dst_layout
) {
580 encode_msaa(key
->rt_samples
, key
->rt_layout
);
581 /* Now (X, Y, S) = detile(rt_tiling, offset) */
582 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
583 /* Now (X, Y, S) = detile(dst_tiling, offset) */
584 decode_msaa(key
->dst_samples
, key
->dst_layout
);
587 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
589 * That is: X, Y and S now contain the true coordinates and sample index of
590 * the data that the WM thread should output.
592 * If we need to kill pixels that are outside the destination rectangle,
593 * now is the time to do it.
597 kill_if_outside_dst_rect();
599 /* Next, apply a translation to obtain coordinates in the source image. */
600 translate_dst_to_src();
602 /* If the source image is not multisampled, then we want to fetch sample
603 * number 0, because that's the only sample there is.
605 if (key
->src_samples
== 0)
608 /* X, Y, and S are now the coordinates of the pixel in the source image
609 * that we want to texture from. Exception: if we are blending, then S is
610 * irrelevant, because we are going to fetch all samples.
613 if (brw
->intel
.gen
== 6) {
614 /* Gen6 hardware an automatically blend using the SAMPLE message */
618 /* Gen7+ hardware doesn't automaticaly blend. */
622 /* We aren't blending, which means we just want to fetch a single sample
623 * from the source surface. The address that we want to fetch from is
624 * related to the X, Y and S values according to the formula:
626 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
628 * If the actual tiling and sample count of the source surface are not
629 * the same as the configuration of the texture, then we need to adjust
630 * the coordinates to compensate for the difference.
632 if (tex_tiled_w
!= key
->src_tiled_w
||
633 key
->tex_samples
!= key
->src_samples
||
634 key
->tex_layout
!= key
->src_layout
) {
635 encode_msaa(key
->src_samples
, key
->src_layout
);
636 /* Now (X, Y, S) = detile(src_tiling, offset) */
637 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
638 /* Now (X, Y, S) = detile(tex_tiling, offset) */
639 decode_msaa(key
->tex_samples
, key
->tex_layout
);
642 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
644 * In other words: X, Y, and S now contain values which, when passed to
645 * the texturing unit, will cause data to be read from the correct
646 * memory location. So we can fetch the texel now.
651 /* Finally, write the fetched (or blended) value to the render target and
652 * terminate the thread.
654 render_target_write();
655 return brw_get_program(&func
, program_size
);
659 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
661 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
662 #define ALLOC_REG(name) \
664 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
670 ALLOC_REG(x_transform
.multiplier
);
671 ALLOC_REG(x_transform
.offset
);
672 ALLOC_REG(y_transform
.multiplier
);
673 ALLOC_REG(y_transform
.offset
);
679 brw_blorp_blit_program::alloc_regs()
682 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
683 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
684 prog_data
.first_curbe_grf
= reg
;
685 alloc_push_const_regs(reg
);
686 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
687 this->result
= vec16(brw_vec8_grf(reg
, 0)); reg
+= 8;
688 this->texture_data
= vec16(brw_vec8_grf(reg
, 0)); reg
+= 8;
689 for (int i
= 0; i
< 2; ++i
) {
691 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
693 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
695 this->xy_coord_index
= 0;
697 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
698 this->t1
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
699 this->t2
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
702 this->base_mrf
= mrf
;
705 /* In the code that follows, X and Y can be used to quickly refer to the
706 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
707 * prime") to the inactive elements.
709 * S can be used to quickly refer to sample_index.
711 #define X x_coords[xy_coord_index]
712 #define Y y_coords[xy_coord_index]
713 #define Xp x_coords[!xy_coord_index]
714 #define Yp y_coords[!xy_coord_index]
715 #define S sample_index
717 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
718 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
720 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
723 * Emit code to compute the X and Y coordinates of the pixels being rendered
724 * by this WM invocation.
726 * Assuming the render target is set up for Y tiling, these (X, Y) values are
727 * related to the address offset where outputs will be written by the formula:
729 * (X, Y, S) = decode_msaa(detile(offset)).
731 * (See brw_blorp_blit_program).
734 brw_blorp_blit_program::compute_frag_coords()
736 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
737 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
738 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
739 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
741 * Pixels within a subspan are laid out in this arrangement:
745 * So, to compute the coordinates of each pixel, we need to read every 2nd
746 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
747 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
748 * In other words, the data we want to access is R1.4<2;4,0>UW.
750 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
751 * result, since pixels n+1 and n+3 are in the right half of the subspan.
753 brw_ADD(&func
, X
, stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
755 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
756 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
757 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
760 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
761 * pixels n+2 and n+3 are in the bottom half of the subspan.
763 brw_ADD(&func
, Y
, stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
765 if (key
->persample_msaa_dispatch
) {
766 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples > 0.
767 * Therefore, subspan 0 will represent sample 0, subspan 1 will
768 * represent sample 1, and so on.
770 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1, 1,
771 * 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to populate a
772 * temporary variable with the sequence (0, 1, 2, 3), and then copy from
773 * it using vstride=1, width=4, hstride=0.
775 * TODO: implement the necessary calculation for 8x multisampling.
777 brw_MOV(&func
, t1
, brw_imm_v(0x3210));
778 brw_MOV(&func
, S
, stride(t1
, 1, 4, 0));
781 /* Either the destination surface is single-sampled, or the WM will be
782 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
783 * per pixel). In either case, it's not meaningful to compute a sample
784 * value. Just set it to 0.
791 * Emit code to compensate for the difference between Y and W tiling.
793 * This code modifies the X and Y coordinates according to the formula:
795 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
797 * (See brw_blorp_blit_program).
799 * It can only translate between W and Y tiling, so new_tiling and old_tiling
800 * are booleans where true represents W tiling and false represents Y tiling.
803 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
805 if (old_tiled_w
== new_tiled_w
)
808 /* In the code that follows, we can safely assume that S = 0, because W
809 * tiling formats always use IMS layout.
814 /* Given X and Y coordinates that describe an address using Y tiling,
815 * translate to the X and Y coordinates that describe the same address
818 * If we break down the low order bits of X and Y, using a
819 * single letter to represent each low-order bit:
821 * X = A << 7 | 0bBCDEFGH
822 * Y = J << 5 | 0bKLMNP (1)
824 * Then we can apply the Y tiling formula to see the memory offset being
827 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
829 * If we apply the W detiling formula to this memory location, that the
830 * corresponding X' and Y' coordinates are:
832 * X' = A << 6 | 0bBCDPFH (3)
833 * Y' = J << 6 | 0bKLMNEG
835 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
836 * we need to make the following computation:
838 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
839 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
841 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
842 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
843 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
844 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
845 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
846 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
847 brw_OR(&func
, Xp
, t1
, t2
);
848 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
849 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
850 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
851 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
852 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
853 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
854 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
855 brw_OR(&func
, Yp
, t1
, t2
);
858 /* Applying the same logic as above, but in reverse, we obtain the
861 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
862 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
864 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
865 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
866 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
867 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
868 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
869 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
870 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
871 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
873 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
874 brw_OR(&func
, Xp
, t1
, t2
);
875 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
876 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
877 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
878 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
879 brw_OR(&func
, Yp
, t1
, t2
);
885 * Emit code to compensate for the difference between MSAA and non-MSAA
888 * This code modifies the X and Y coordinates according to the formula:
890 * (X', Y', S') = encode_msaa_4x(X, Y, S)
892 * (See brw_blorp_blit_program).
895 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
896 intel_msaa_layout layout
)
899 case INTEL_MSAA_LAYOUT_NONE
:
900 /* No translation necessary, and S should already be zero. */
903 case INTEL_MSAA_LAYOUT_CMS
:
904 /* We can't compensate for compressed layout since at this point in the
905 * program we haven't read from the MCS buffer.
907 assert(!"Bad layout in encode_msaa");
909 case INTEL_MSAA_LAYOUT_UMS
:
910 /* No translation necessary. */
912 case INTEL_MSAA_LAYOUT_IMS
:
913 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
914 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
915 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
917 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
919 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
920 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
922 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
924 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
925 brw_OR(&func
, Xp
, t1
, t2
);
926 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
927 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
929 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
930 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
932 brw_AND(&func
, t2
, Y
, brw_imm_uw(1));
933 brw_OR(&func
, Yp
, t1
, t2
);
941 * Emit code to compensate for the difference between MSAA and non-MSAA
944 * This code modifies the X and Y coordinates according to the formula:
946 * (X', Y', S) = decode_msaa(num_samples, X, Y, S)
948 * (See brw_blorp_blit_program).
951 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
952 intel_msaa_layout layout
)
955 case INTEL_MSAA_LAYOUT_NONE
:
956 /* No translation necessary, and S should already be zero. */
959 case INTEL_MSAA_LAYOUT_CMS
:
960 /* We can't compensate for compressed layout since at this point in the
961 * program we don't have access to the MCS buffer.
963 assert(!"Bad layout in encode_msaa");
965 case INTEL_MSAA_LAYOUT_UMS
:
966 /* No translation necessary. */
968 case INTEL_MSAA_LAYOUT_IMS
:
969 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
970 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
971 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
972 * S = (Y & 0b10) | (X & 0b10) >> 1
975 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
976 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
977 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
978 brw_OR(&func
, Xp
, t1
, t2
);
979 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
980 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
981 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
982 brw_OR(&func
, Yp
, t1
, t2
);
983 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
984 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
985 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
986 brw_OR(&func
, S
, t1
, t2
);
994 * Emit code that kills pixels whose X and Y coordinates are outside the
995 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
999 brw_blorp_blit_program::kill_if_outside_dst_rect()
1001 struct brw_reg f0
= brw_flag_reg();
1002 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1003 struct brw_reg null16
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
1005 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1006 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1007 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1008 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1010 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1011 brw_push_insn_state(&func
);
1012 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1013 brw_AND(&func
, g1
, f0
, g1
);
1014 brw_pop_insn_state(&func
);
1018 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1022 brw_blorp_blit_program::translate_dst_to_src()
1024 brw_MUL(&func
, Xp
, X
, x_transform
.multiplier
);
1025 brw_MUL(&func
, Yp
, Y
, y_transform
.multiplier
);
1026 brw_ADD(&func
, Xp
, Xp
, x_transform
.offset
);
1027 brw_ADD(&func
, Yp
, Yp
, y_transform
.offset
);
1032 * Emit code to transform the X and Y coordinates as needed for blending
1033 * together the different samples in an MSAA texture.
1036 brw_blorp_blit_program::single_to_blend()
1038 /* When looking up samples in an MSAA texture using the SAMPLE message,
1039 * Gen6 requires the texture coordinates to be odd integers (so that they
1040 * correspond to the center of a 2x2 block representing the four samples
1041 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1042 * each by 2 and then add 1.
1044 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1045 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1046 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1047 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1052 brw_blorp_blit_program::manual_blend()
1054 /* TODO: support num_samples != 4 */
1055 const int num_samples
= 4;
1057 /* Gather sample 0 data first */
1059 texel_fetch(result
);
1061 /* Gather data for remaining samples and accumulate it into result. */
1063 for (int i
= 1; i
< num_samples
; ++i
) {
1064 brw_MOV(&func
, S
, brw_imm_uw(i
));
1065 texel_fetch(texture_data
);
1067 /* TODO: should use a smaller loop bound for non-RGBA formats */
1068 for (int j
= 0; j
< 4; ++j
) {
1069 brw_ADD(&func
, offset(result
, 2*j
), offset(vec8(result
), 2*j
),
1070 offset(vec8(texture_data
), 2*j
));
1074 /* Scale the result down by a factor of num_samples */
1075 /* TODO: should use a smaller loop bound for non-RGBA formats */
1076 for (int j
= 0; j
< 4; ++j
) {
1077 brw_MUL(&func
, offset(result
, 2*j
), offset(vec8(result
), 2*j
),
1078 brw_imm_f(1.0/num_samples
));
1083 * Emit code to look up a value in the texture using the SAMPLE message (which
1084 * does blending of MSAA surfaces).
1087 brw_blorp_blit_program::sample(struct brw_reg dst
)
1089 static const sampler_message_arg args
[2] = {
1090 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1091 SAMPLER_MESSAGE_ARG_V_FLOAT
1094 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
, ARRAY_SIZE(args
));
1098 * Emit code to look up a value in the texture using the SAMPLE_LD message
1099 * (which does a simple texel fetch).
1102 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1104 static const sampler_message_arg gen6_args
[5] = {
1105 SAMPLER_MESSAGE_ARG_U_INT
,
1106 SAMPLER_MESSAGE_ARG_V_INT
,
1107 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1108 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1109 SAMPLER_MESSAGE_ARG_SI_INT
1111 static const sampler_message_arg gen7_ld_args
[3] = {
1112 SAMPLER_MESSAGE_ARG_U_INT
,
1113 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1114 SAMPLER_MESSAGE_ARG_V_INT
1116 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1117 SAMPLER_MESSAGE_ARG_SI_INT
,
1118 SAMPLER_MESSAGE_ARG_U_INT
,
1119 SAMPLER_MESSAGE_ARG_V_INT
1122 switch (brw
->intel
.gen
) {
1124 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1128 if (key
->tex_samples
> 0) {
1129 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1130 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1133 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1134 ARRAY_SIZE(gen7_ld_args
));
1138 assert(!"Should not get here.");
1144 brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src
,
1147 brw_MOV(&func
, vec8(dst
), vec8(src
));
1148 brw_set_compression_control(&func
, BRW_COMPRESSION_2NDHALF
);
1149 brw_MOV(&func
, offset(vec8(dst
), 1), suboffset(vec8(src
), 8));
1150 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1154 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1156 const sampler_message_arg
*args
,
1159 struct brw_reg mrf
=
1160 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1161 for (int arg
= 0; arg
< num_args
; ++arg
) {
1162 switch (args
[arg
]) {
1163 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1164 expand_to_32_bits(X
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1166 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1167 expand_to_32_bits(Y
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1169 case SAMPLER_MESSAGE_ARG_U_INT
:
1170 expand_to_32_bits(X
, mrf
);
1172 case SAMPLER_MESSAGE_ARG_V_INT
:
1173 expand_to_32_bits(Y
, mrf
);
1175 case SAMPLER_MESSAGE_ARG_SI_INT
:
1176 /* Note: on Gen7, this code may be reached with s_is_zero==true
1177 * because in Gen7's ld2dss message, the sample index is the first
1178 * argument. When this happens, we need to move a 0 into the
1179 * appropriate message register.
1182 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1184 expand_to_32_bits(S
, mrf
);
1186 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1187 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1194 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1195 base_mrf
/* msg_reg_nr */,
1196 brw_message_reg(base_mrf
) /* src0 */,
1197 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1201 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1202 mrf
.nr
- base_mrf
/* msg_length */,
1203 0 /* header_present */,
1204 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1205 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1213 #undef SWAP_XY_AND_XPYP
1216 brw_blorp_blit_program::render_target_write()
1218 struct brw_reg mrf_rt_write
= vec16(brw_message_reg(base_mrf
));
1221 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1222 * so that the render target knows which pixels we killed.
1224 bool use_header
= key
->use_kill
;
1226 /* Copy R0/1 to MRF */
1227 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1228 retype(R0
, BRW_REGISTER_TYPE_UD
));
1232 /* Copy texture data to MRFs */
1233 for (int i
= 0; i
< 4; ++i
) {
1234 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1235 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1236 offset(vec8(result
), 2*i
));
1240 /* Now write to the render target and terminate the thread */
1242 16 /* dispatch_width */,
1243 base_mrf
/* msg_reg_nr */,
1244 mrf_rt_write
/* src0 */,
1245 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1246 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1247 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1248 0 /* response_length */,
1255 brw_blorp_coord_transform_params::setup(GLuint src0
, GLuint dst0
, GLuint dst1
,
1259 /* When not mirroring a coordinate (say, X), we need:
1260 * x' - src_x0 = x - dst_x0
1262 * x' = 1*x + (src_x0 - dst_x0)
1265 offset
= src0
- dst0
;
1267 /* When mirroring X we need:
1268 * x' - src_x0 = dst_x1 - x - 1
1270 * x' = -1*x + (src_x0 + dst_x1 - 1)
1273 offset
= src0
+ dst1
- 1;
1279 * Determine which MSAA layout the GPU pipeline should be configured for,
1280 * based on the chip generation, the number of samples, and the true layout of
1281 * the image in memory.
1283 inline intel_msaa_layout
1284 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1285 intel_msaa_layout true_layout
)
1287 if (num_samples
== 0) {
1288 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1289 * format buffers, by transforming coordinates appropriately.
1291 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1292 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1293 return INTEL_MSAA_LAYOUT_NONE
;
1296 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1297 if (brw
->intel
.gen
== 6) {
1298 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1299 return INTEL_MSAA_LAYOUT_IMS
;
1302 /* Since blorp uses color textures and render targets to do all its work
1303 * (even when blitting stencil and depth data), we always have to configure
1304 * the Gen7 GPU to use UMS or CMS layout on Gen7.
1306 assert(true_layout
== INTEL_MSAA_LAYOUT_UMS
||
1307 true_layout
== INTEL_MSAA_LAYOUT_CMS
);
1312 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1313 struct intel_mipmap_tree
*src_mt
,
1314 struct intel_mipmap_tree
*dst_mt
,
1315 GLuint src_x0
, GLuint src_y0
,
1316 GLuint dst_x0
, GLuint dst_y0
,
1317 GLuint dst_x1
, GLuint dst_y1
,
1318 bool mirror_x
, bool mirror_y
)
1320 src
.set(brw
, src_mt
, 0, 0);
1321 dst
.set(brw
, dst_mt
, 0, 0);
1324 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1326 if (brw
->intel
.gen
> 6) {
1327 /* Gen7's texturing hardware only supports the IMS layout with the
1328 * ld2dms instruction (which blorp doesn't use). So if the source is
1329 * IMS, we'll have to map it as a single-sampled texture and
1330 * de-interleave the samples ourselves.
1332 if (src_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1333 src
.num_samples
= 0;
1335 /* Similarly, Gen7's rendering hardware only supports the IMS layout for
1336 * depth and stencil render targets. Blorp always maps its destination
1337 * surface as a color render target (even if it's actually a depth or
1338 * stencil buffer). So if the destination is IMS, we'll have to map it
1339 * as a single-sampled texture and interleave the samples ourselves.
1341 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1342 dst
.num_samples
= 0;
1345 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 0) {
1346 /* If the destination surface is a W-tiled multisampled stencil buffer
1347 * that we're mapping as Y tiled, then we need to arrange for the WM
1348 * program to run once per sample rather than once per pixel, because
1349 * the memory layout of related samples doesn't match between W and Y
1352 wm_prog_key
.persample_msaa_dispatch
= true;
1355 if (src
.num_samples
> 0 && dst
.num_samples
> 0) {
1356 /* We are blitting from a multisample buffer to a multisample buffer, so
1357 * we must preserve samples within a pixel. This means we have to
1358 * arrange for the WM program to run once per sample rather than once
1361 wm_prog_key
.persample_msaa_dispatch
= true;
1364 /* The render path must be configured to use the same number of samples as
1365 * the destination buffer.
1367 num_samples
= dst
.num_samples
;
1369 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1370 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1371 base_format
!= GL_STENCIL_INDEX
&&
1372 src_mt
->num_samples
> 0 && dst_mt
->num_samples
== 0) {
1373 /* We are downsampling a color buffer, so blend. */
1374 wm_prog_key
.blend
= true;
1377 /* src_samples and dst_samples are the true sample counts */
1378 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1379 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1381 /* tex_samples and rt_samples are the sample counts that are set up in
1384 wm_prog_key
.tex_samples
= src
.num_samples
;
1385 wm_prog_key
.rt_samples
= dst
.num_samples
;
1387 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1388 * use to access the source and destination surfaces.
1390 wm_prog_key
.tex_layout
=
1391 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1392 wm_prog_key
.rt_layout
=
1393 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1395 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1398 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1399 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1401 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1402 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1403 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1404 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1405 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1406 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1407 wm_push_consts
.x_transform
.setup(src_x0
, dst_x0
, dst_x1
, mirror_x
);
1408 wm_push_consts
.y_transform
.setup(src_y0
, dst_y0
, dst_y1
, mirror_y
);
1410 if (dst
.num_samples
== 0 && dst_mt
->num_samples
> 0) {
1411 /* We must expand the rectangle we send through the rendering pipeline,
1412 * to account for the fact that we are mapping the destination region as
1413 * single-sampled when it is in fact multisampled. We must also align
1414 * it to a multiple of the multisampling pattern, because the
1415 * differences between multisampled and single-sampled surface formats
1416 * will mean that pixels are scrambled within the multisampling pattern.
1417 * TODO: what if this makes the coordinates too large?
1419 * Note: this only works if the destination surface uses the IMS layout.
1420 * If it's UMS, then we have no choice but to set up the rendering
1421 * pipeline as multisampled.
1423 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
1426 x1
= ALIGN(x1
* 2, 4);
1427 y1
= ALIGN(y1
* 2, 4);
1428 wm_prog_key
.use_kill
= true;
1431 if (dst
.map_stencil_as_y_tiled
) {
1432 /* We must modify the rectangle we send through the rendering pipeline,
1433 * to account for the fact that we are mapping it as Y-tiled when it is
1434 * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have
1435 * dimensions 64x64. We must also align it to a multiple of the tile
1436 * size, because the differences between W and Y tiling formats will
1437 * mean that pixels are scrambled within the tile.
1439 * Note: if the destination surface configured to use IMS layout, then
1440 * the effective tile size we need to align it to is smaller, because
1441 * each pixel covers a 2x2 or a 4x2 block of samples.
1443 * TODO: what if this makes the coordinates too large?
1445 unsigned x_align
= 64, y_align
= 64;
1446 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
1447 x_align
/= (dst_mt
->num_samples
== 4 ? 2 : 4);
1450 x0
= (x0
& ~(x_align
- 1)) * 2;
1451 y0
= (y0
& ~(y_align
- 1)) / 2;
1452 x1
= ALIGN(x1
, x_align
) * 2;
1453 y1
= ALIGN(y1
, y_align
) / 2;
1454 wm_prog_key
.use_kill
= true;
1459 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
1460 brw_blorp_prog_data
**prog_data
) const
1462 uint32_t prog_offset
;
1463 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1464 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1465 &prog_offset
, prog_data
)) {
1466 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
1467 GLuint program_size
;
1468 const GLuint
*program
= prog
.compile(brw
, &program_size
);
1469 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1470 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1471 program
, program_size
,
1472 &prog
.prog_data
, sizeof(prog
.prog_data
),
1473 &prog_offset
, prog_data
);