2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
27 #include "intel_fbo.h"
29 #include "brw_blorp.h"
30 #include "brw_context.h"
31 #include "brw_blorp_blit_eu.h"
32 #include "brw_state.h"
33 #include "brw_meta_util.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
37 static struct intel_mipmap_tree
*
38 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
40 struct intel_mipmap_tree
*mt
= irb
->mt
;
41 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
48 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
49 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
50 * the physical layer holding sample 0. So, for example, if
51 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
55 brw_blorp_blit_miptrees(struct brw_context
*brw
,
56 struct intel_mipmap_tree
*src_mt
,
57 unsigned src_level
, unsigned src_layer
,
58 mesa_format src_format
,
59 struct intel_mipmap_tree
*dst_mt
,
60 unsigned dst_level
, unsigned dst_layer
,
61 mesa_format dst_format
,
62 float src_x0
, float src_y0
,
63 float src_x1
, float src_y1
,
64 float dst_x0
, float dst_y0
,
65 float dst_x1
, float dst_y1
,
66 GLenum filter
, bool mirror_x
, bool mirror_y
)
68 /* Get ready to blit. This includes depth resolving the src and dst
69 * buffers if necessary. Note: it's not necessary to do a color resolve on
70 * the destination buffer because we use the standard render path to render
71 * to destination color buffers, and the standard render path is
74 intel_miptree_resolve_color(brw
, src_mt
);
75 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
76 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
78 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
79 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
81 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
82 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
83 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
84 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
87 brw_blorp_blit_params
params(brw
,
88 src_mt
, src_level
, src_layer
, src_format
,
89 dst_mt
, dst_level
, dst_layer
, dst_format
,
94 filter
, mirror_x
, mirror_y
);
95 brw_blorp_exec(brw
, ¶ms
);
97 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
101 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
102 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
103 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
104 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
105 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
106 GLenum filter
, bool mirror_x
, bool mirror_y
)
108 /* Find source/dst miptrees */
109 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
110 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
113 brw_blorp_blit_miptrees(brw
,
114 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
116 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
118 srcX0
, srcY0
, srcX1
, srcY1
,
119 dstX0
, dstY0
, dstX1
, dstY1
,
120 filter
, mirror_x
, mirror_y
);
122 dst_irb
->need_downsample
= true;
126 try_blorp_blit(struct brw_context
*brw
,
127 const struct gl_framebuffer
*read_fb
,
128 const struct gl_framebuffer
*draw_fb
,
129 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
130 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
131 GLenum filter
, GLbitfield buffer_bit
)
133 struct gl_context
*ctx
= &brw
->ctx
;
135 /* Sync up the state of window system buffers. We need to do this before
136 * we go looking for the buffers.
138 intel_prepare_render(brw
);
140 bool mirror_x
, mirror_y
;
141 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
142 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
143 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
144 &mirror_x
, &mirror_y
))
148 struct intel_renderbuffer
*src_irb
;
149 struct intel_renderbuffer
*dst_irb
;
150 struct intel_mipmap_tree
*src_mt
;
151 struct intel_mipmap_tree
*dst_mt
;
152 switch (buffer_bit
) {
153 case GL_COLOR_BUFFER_BIT
:
154 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
155 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
156 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
158 do_blorp_blit(brw
, buffer_bit
,
159 src_irb
, src_irb
->Base
.Base
.Format
,
160 dst_irb
, dst_irb
->Base
.Base
.Format
,
161 srcX0
, srcY0
, srcX1
, srcY1
,
162 dstX0
, dstY0
, dstX1
, dstY1
,
163 filter
, mirror_x
, mirror_y
);
166 case GL_DEPTH_BUFFER_BIT
:
168 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
170 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
171 src_mt
= find_miptree(buffer_bit
, src_irb
);
172 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
174 /* We can't handle format conversions between Z24 and other formats
175 * since we have to lie about the surface format. See the comments in
176 * brw_blorp_surface_info::set().
178 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
179 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
182 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
183 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
184 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
185 filter
, mirror_x
, mirror_y
);
187 case GL_STENCIL_BUFFER_BIT
:
189 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
191 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
192 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
193 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
194 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
195 filter
, mirror_x
, mirror_y
);
198 unreachable("not reached");
205 brw_blorp_copytexsubimage(struct brw_context
*brw
,
206 struct gl_renderbuffer
*src_rb
,
207 struct gl_texture_image
*dst_image
,
209 int srcX0
, int srcY0
,
210 int dstX0
, int dstY0
,
211 int width
, int height
)
213 struct gl_context
*ctx
= &brw
->ctx
;
214 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
215 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
217 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
218 if (brw
->ctx
._ImageTransferState
)
221 /* Sync up the state of window system buffers. We need to do this before
222 * we go looking at the src renderbuffer's miptree.
224 intel_prepare_render(brw
);
226 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
227 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
229 /* BLORP is only supported for Gen6-7. */
230 if (brw
->gen
< 6 || brw
->gen
> 7)
233 if (_mesa_get_format_base_format(src_rb
->Format
) !=
234 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
238 /* We can't handle format conversions between Z24 and other formats since
239 * we have to lie about the surface format. See the comments in
240 * brw_blorp_surface_info::set().
242 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
243 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
247 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
250 /* Source clipping shouldn't be necessary, since copytexsubimage (in
251 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
254 * Destination clipping shouldn't be necessary since the restrictions on
255 * glCopyTexSubImage prevent the user from specifying a destination rectangle
256 * that falls outside the bounds of the destination texture.
257 * See error_check_subtexture_dimensions().
260 int srcY1
= srcY0
+ height
;
261 int srcX1
= srcX0
+ width
;
262 int dstX1
= dstX0
+ width
;
263 int dstY1
= dstY0
+ height
;
265 /* Account for the fact that in the system framebuffer, the origin is at
268 bool mirror_y
= false;
269 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
270 GLint tmp
= src_rb
->Height
- srcY0
;
271 srcY0
= src_rb
->Height
- srcY1
;
276 /* Account for face selection and texture view MinLayer */
277 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
278 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
280 brw_blorp_blit_miptrees(brw
,
281 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
283 dst_mt
, dst_level
, dst_slice
,
284 dst_image
->TexFormat
,
285 srcX0
, srcY0
, srcX1
, srcY1
,
286 dstX0
, dstY0
, dstX1
, dstY1
,
287 GL_NEAREST
, false, mirror_y
);
289 /* If we're copying to a packed depth stencil texture and the source
290 * framebuffer has separate stencil, we need to also copy the stencil data
293 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
294 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
296 src_irb
= intel_renderbuffer(src_rb
);
297 src_mt
= src_irb
->mt
;
299 if (src_mt
->stencil_mt
)
300 src_mt
= src_mt
->stencil_mt
;
301 if (dst_mt
->stencil_mt
)
302 dst_mt
= dst_mt
->stencil_mt
;
304 if (src_mt
!= dst_mt
) {
305 brw_blorp_blit_miptrees(brw
,
306 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
308 dst_mt
, dst_level
, dst_slice
,
310 srcX0
, srcY0
, srcX1
, srcY1
,
311 dstX0
, dstY0
, dstX1
, dstY1
,
312 GL_NEAREST
, false, mirror_y
);
321 brw_blorp_framebuffer(struct brw_context
*brw
,
322 struct gl_framebuffer
*readFb
,
323 struct gl_framebuffer
*drawFb
,
324 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
325 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
326 GLbitfield mask
, GLenum filter
)
328 /* BLORP is not supported before Gen6. */
329 if (brw
->gen
< 6 || brw
->gen
>= 8)
332 static GLbitfield buffer_bits
[] = {
335 GL_STENCIL_BUFFER_BIT
,
338 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
339 if ((mask
& buffer_bits
[i
]) &&
340 try_blorp_blit(brw
, readFb
, drawFb
,
341 srcX0
, srcY0
, srcX1
, srcY1
,
342 dstX0
, dstY0
, dstX1
, dstY1
,
343 filter
, buffer_bits
[i
])) {
344 mask
&= ~buffer_bits
[i
];
353 * Enum to specify the order of arguments in a sampler message
355 enum sampler_message_arg
357 SAMPLER_MESSAGE_ARG_U_FLOAT
,
358 SAMPLER_MESSAGE_ARG_V_FLOAT
,
359 SAMPLER_MESSAGE_ARG_U_INT
,
360 SAMPLER_MESSAGE_ARG_V_INT
,
361 SAMPLER_MESSAGE_ARG_SI_INT
,
362 SAMPLER_MESSAGE_ARG_MCS_INT
,
363 SAMPLER_MESSAGE_ARG_ZERO_INT
,
367 * Generator for WM programs used in BLORP blits.
369 * The bulk of the work done by the WM program is to wrap and unwrap the
370 * coordinate transformations used by the hardware to store surfaces in
371 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
372 * sample index for a multisampled surface) to a memory offset by the
373 * following formulas:
375 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
376 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
378 * For a single-sampled surface, or for a multisampled surface using
379 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
382 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
383 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
384 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
385 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
387 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
388 * embeds the sample number into bit 1 of the X and Y coordinates:
390 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
391 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
392 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
393 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
394 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
395 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
396 * S = (Y & 0b10) | (X & 0b10) >> 1
398 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
399 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
402 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
403 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
404 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
405 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
406 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
407 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
408 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
410 * For X tiling, tile() combines together the low-order bits of the X and Y
411 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
412 * bytes wide and 8 rows high:
414 * tile(x_tiled, X, Y, S) = A
415 * where A = tile_num << 12 | offset
416 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
417 * offset = (Y' & 0b111) << 9
418 * | (X & 0b111111111)
420 * Y' = Y + S * qpitch
421 * detile(x_tiled, A) = (X, Y, S)
425 * Y' = (tile_num / tile_pitch) << 3
426 * | (A & 0b111000000000) >> 9
427 * X' = (tile_num % tile_pitch) << 9
428 * | (A & 0b111111111)
430 * (In all tiling formulas, cpp is the number of bytes occupied by a single
431 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
432 * to fill the width of the surface, and qpitch is the spacing (in rows)
433 * between array slices).
435 * For Y tiling, tile() combines together the low-order bits of the X and Y
436 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
437 * bytes wide and 32 rows high:
439 * tile(y_tiled, X, Y, S) = A
440 * where A = tile_num << 12 | offset
441 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
442 * offset = (X' & 0b1110000) << 5
443 * | (Y' & 0b11111) << 4
446 * Y' = Y + S * qpitch
447 * detile(y_tiled, A) = (X, Y, S)
451 * Y' = (tile_num / tile_pitch) << 5
452 * | (A & 0b111110000) >> 4
453 * X' = (tile_num % tile_pitch) << 7
454 * | (A & 0b111000000000) >> 5
457 * For W tiling, tile() combines together the low-order bits of the X and Y
458 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
459 * bytes wide and 64 rows high (note that W tiling is only used for stencil
460 * buffers, which always have cpp = 1 and S=0):
462 * tile(w_tiled, X, Y, S) = A
463 * where A = tile_num << 12 | offset
464 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
465 * offset = (X' & 0b111000) << 6
466 * | (Y' & 0b111100) << 3
467 * | (X' & 0b100) << 2
473 * Y' = Y + S * qpitch
474 * detile(w_tiled, A) = (X, Y, S)
475 * where X = X' / cpp = X'
476 * Y = Y' % qpitch = Y'
478 * Y' = (tile_num / tile_pitch) << 6
479 * | (A & 0b111100000) >> 3
480 * | (A & 0b1000) >> 2
482 * X' = (tile_num % tile_pitch) << 6
483 * | (A & 0b111000000000) >> 6
484 * | (A & 0b10000) >> 2
488 * Finally, for a non-tiled surface, tile() simply combines together the X and
489 * Y coordinates in the natural way:
491 * tile(untiled, X, Y, S) = A
492 * where A = Y * pitch + X'
494 * Y' = Y + S * qpitch
495 * detile(untiled, A) = (X, Y, S)
502 * (In these formulas, pitch is the number of bytes occupied by a single row
505 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
508 brw_blorp_blit_program(struct brw_context
*brw
,
509 const brw_blorp_blit_prog_key
*key
, bool debug_flag
);
511 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
513 brw_blorp_prog_data prog_data
;
517 void alloc_push_const_regs(int base_reg
);
518 void compute_frag_coords();
519 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
520 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
521 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
522 void translate_dst_to_src();
523 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
524 struct brw_reg clampX0
, struct brw_reg clampY0
,
525 struct brw_reg clampX1
, struct brw_reg clampY1
);
526 void single_to_blend();
527 void manual_blend_average(unsigned num_samples
);
528 void manual_blend_bilinear(unsigned num_samples
);
529 void sample(struct brw_reg dst
);
530 void texel_fetch(struct brw_reg dst
);
532 void texture_lookup(struct brw_reg dst
, enum opcode op
,
533 const sampler_message_arg
*args
, int num_args
);
534 void render_target_write();
537 * Base-2 logarithm of the maximum number of samples that can be blended.
539 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
541 struct brw_context
*brw
;
542 const brw_blorp_blit_prog_key
*key
;
544 /* Thread dispatch header */
547 /* Pixel X/Y coordinates (always in R1). */
551 struct brw_reg dst_x0
;
552 struct brw_reg dst_x1
;
553 struct brw_reg dst_y0
;
554 struct brw_reg dst_y1
;
555 /* Top right coordinates of the rectangular grid used for scaled blitting */
556 struct brw_reg rect_grid_x1
;
557 struct brw_reg rect_grid_y1
;
559 struct brw_reg multiplier
;
560 struct brw_reg offset
;
561 } x_transform
, y_transform
;
563 /* Data read from texture (4 vec16's per array element) */
564 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
566 /* Auxiliary storage for the contents of the MCS surface.
568 * Since the sampler always returns 8 registers worth of data, this is 8
569 * registers wide, even though we only use the first 2 registers of it.
571 struct brw_reg mcs_data
;
573 /* X coordinates. We have two of them so that we can perform coordinate
574 * transformations easily.
576 struct brw_reg x_coords
[2];
578 /* Y coordinates. We have two of them so that we can perform coordinate
579 * transformations easily.
581 struct brw_reg y_coords
[2];
583 /* X, Y coordinates of the pixel from which we need to fetch the specific
584 * sample. These are used for multisample scaled blitting.
586 struct brw_reg x_sample_coords
;
587 struct brw_reg y_sample_coords
;
589 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
590 struct brw_reg x_frac
;
591 struct brw_reg y_frac
;
593 /* Which element of x_coords and y_coords is currently in use.
597 /* True if, at the point in the program currently being compiled, the
598 * sample index is known to be zero.
602 /* Register storing the sample index when s_is_zero is false. */
603 struct brw_reg sample_index
;
609 /* MRF used for sampling and render target writes */
613 brw_blorp_blit_program::brw_blorp_blit_program(
614 struct brw_context
*brw
,
615 const brw_blorp_blit_prog_key
*key
,
617 : brw_blorp_eu_emitter(brw
, debug_flag
),
624 brw_blorp_blit_program::compile(struct brw_context
*brw
,
625 GLuint
*program_size
)
628 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
629 /* If the destination image is W tiled and multisampled, then the thread
630 * must be dispatched once per sample, not once per pixel. This is
631 * necessary because after conversion between W and Y tiling, there's no
632 * guarantee that all samples corresponding to a single pixel will still
635 assert(key
->persample_msaa_dispatch
);
639 /* We are blending, which means we won't have an opportunity to
640 * translate the tiling and sample count for the texture surface. So
641 * the surface state for the texture must be configured with the correct
642 * tiling and sample count.
644 assert(!key
->src_tiled_w
);
645 assert(key
->tex_samples
== key
->src_samples
);
646 assert(key
->tex_layout
== key
->src_layout
);
647 assert(key
->tex_samples
> 0);
650 if (key
->persample_msaa_dispatch
) {
651 /* It only makes sense to do persample dispatch if the render target is
652 * configured as multisampled.
654 assert(key
->rt_samples
> 0);
657 /* Make sure layout is consistent with sample count */
658 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
659 (key
->tex_samples
== 0));
660 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
661 (key
->rt_samples
== 0));
662 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
663 (key
->src_samples
== 0));
664 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
665 (key
->dst_samples
== 0));
667 /* Set up prog_data */
668 memset(&prog_data
, 0, sizeof(prog_data
));
669 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
672 compute_frag_coords();
674 /* Render target and texture hardware don't support W tiling. */
675 const bool rt_tiled_w
= false;
676 const bool tex_tiled_w
= false;
678 /* The address that data will be written to is determined by the
679 * coordinates supplied to the WM thread and the tiling and sample count of
680 * the render target, according to the formula:
682 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
684 * If the actual tiling and sample count of the destination surface are not
685 * the same as the configuration of the render target, then these
686 * coordinates are wrong and we have to adjust them to compensate for the
689 if (rt_tiled_w
!= key
->dst_tiled_w
||
690 key
->rt_samples
!= key
->dst_samples
||
691 key
->rt_layout
!= key
->dst_layout
) {
692 encode_msaa(key
->rt_samples
, key
->rt_layout
);
693 /* Now (X, Y, S) = detile(rt_tiling, offset) */
694 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
695 /* Now (X, Y, S) = detile(dst_tiling, offset) */
696 decode_msaa(key
->dst_samples
, key
->dst_layout
);
699 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
701 * That is: X, Y and S now contain the true coordinates and sample index of
702 * the data that the WM thread should output.
704 * If we need to kill pixels that are outside the destination rectangle,
705 * now is the time to do it.
709 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
710 y_coords
[xy_coord_index
],
711 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
713 /* Next, apply a translation to obtain coordinates in the source image. */
714 translate_dst_to_src();
716 /* If the source image is not multisampled, then we want to fetch sample
717 * number 0, because that's the only sample there is.
719 if (key
->src_samples
== 0)
722 /* X, Y, and S are now the coordinates of the pixel in the source image
723 * that we want to texture from. Exception: if we are blending, then S is
724 * irrelevant, because we are going to fetch all samples.
726 if (key
->blend
&& !key
->blit_scaled
) {
728 /* Gen6 hardware an automatically blend using the SAMPLE message */
730 sample(texture_data
[0]);
732 /* Gen7+ hardware doesn't automaticaly blend. */
733 manual_blend_average(key
->src_samples
);
735 } else if(key
->blend
&& key
->blit_scaled
) {
736 manual_blend_bilinear(key
->src_samples
);
738 /* We aren't blending, which means we just want to fetch a single sample
739 * from the source surface. The address that we want to fetch from is
740 * related to the X, Y and S values according to the formula:
742 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
744 * If the actual tiling and sample count of the source surface are not
745 * the same as the configuration of the texture, then we need to adjust
746 * the coordinates to compensate for the difference.
748 if ((tex_tiled_w
!= key
->src_tiled_w
||
749 key
->tex_samples
!= key
->src_samples
||
750 key
->tex_layout
!= key
->src_layout
) &&
751 !key
->bilinear_filter
) {
752 encode_msaa(key
->src_samples
, key
->src_layout
);
753 /* Now (X, Y, S) = detile(src_tiling, offset) */
754 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
755 /* Now (X, Y, S) = detile(tex_tiling, offset) */
756 decode_msaa(key
->tex_samples
, key
->tex_layout
);
759 if (key
->bilinear_filter
) {
760 sample(texture_data
[0]);
763 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
765 * In other words: X, Y, and S now contain values which, when passed to
766 * the texturing unit, will cause data to be read from the correct
767 * memory location. So we can fetch the texel now.
769 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
771 texel_fetch(texture_data
[0]);
775 /* Finally, write the fetched (or blended) value to the render target and
776 * terminate the thread.
778 render_target_write();
780 return get_program(program_size
);
784 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
786 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
787 #define ALLOC_REG(name, type) \
789 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
790 base_reg + CONST_LOC(name) / 32, \
791 (CONST_LOC(name) % 32) / 4), type)
793 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
794 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
795 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
796 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
797 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
798 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
799 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
800 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
801 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
802 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
808 brw_blorp_blit_program::alloc_regs()
811 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
812 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
813 prog_data
.first_curbe_grf
= reg
;
814 alloc_push_const_regs(reg
);
815 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
816 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
817 this->texture_data
[i
] =
818 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
822 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
824 for (int i
= 0; i
< 2; ++i
) {
826 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
829 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
833 if (key
->blit_scaled
&& key
->blend
) {
834 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
836 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
838 this->x_frac
= brw_vec8_grf(reg
, 0);
840 this->y_frac
= brw_vec8_grf(reg
, 0);
844 this->xy_coord_index
= 0;
846 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
848 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
850 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
853 /* Make sure we didn't run out of registers */
854 assert(reg
<= GEN7_MRF_HACK_START
);
857 this->base_mrf
= mrf
;
860 /* In the code that follows, X and Y can be used to quickly refer to the
861 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
862 * prime") to the inactive elements.
864 * S can be used to quickly refer to sample_index.
866 #define X x_coords[xy_coord_index]
867 #define Y y_coords[xy_coord_index]
868 #define Xp x_coords[!xy_coord_index]
869 #define Yp y_coords[!xy_coord_index]
870 #define S sample_index
872 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
873 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
875 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
878 * Emit code to compute the X and Y coordinates of the pixels being rendered
879 * by this WM invocation.
881 * Assuming the render target is set up for Y tiling, these (X, Y) values are
882 * related to the address offset where outputs will be written by the formula:
884 * (X, Y, S) = decode_msaa(detile(offset)).
886 * (See brw_blorp_blit_program).
889 brw_blorp_blit_program::compute_frag_coords()
891 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
892 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
893 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
894 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
896 * Pixels within a subspan are laid out in this arrangement:
900 * So, to compute the coordinates of each pixel, we need to read every 2nd
901 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
902 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
903 * In other words, the data we want to access is R1.4<2;4,0>UW.
905 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
906 * result, since pixels n+1 and n+3 are in the right half of the subspan.
908 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
909 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
911 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
912 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
913 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
916 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
917 * pixels n+2 and n+3 are in the bottom half of the subspan.
919 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
920 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
922 /* Move the coordinates to UD registers. */
923 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
924 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
927 if (key
->persample_msaa_dispatch
) {
928 switch (key
->rt_samples
) {
930 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
931 * Therefore, subspan 0 will represent sample 0, subspan 1 will
932 * represent sample 1, and so on.
934 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
935 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
936 * populate a temporary variable with the sequence (0, 1, 2, 3), and
937 * then copy from it using vstride=1, width=4, hstride=0.
939 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
940 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
941 /* Move to UD sample_index register. */
942 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
943 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
947 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
948 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
949 * subspan 1 will represent sample 1, and so on. We can find the
950 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
951 * Index") and multiplying by two (since samples are always delivered
952 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
955 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
956 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
957 * variable with the sequence (0, 1, 2, 3), and then reading from it
958 * using vstride=1, width=4, hstride=0.
960 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
961 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
962 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
963 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
964 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
965 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
966 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
967 stride(t2_uw1
, 1, 4, 0));
968 emit_add_8(offset(S
, 1),
969 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
970 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
974 unreachable("Unrecognized sample count in "
975 "brw_blorp_blit_program::compute_frag_coords()");
979 /* Either the destination surface is single-sampled, or the WM will be
980 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
981 * per pixel). In either case, it's not meaningful to compute a sample
982 * value. Just set it to 0.
989 * Emit code to compensate for the difference between Y and W tiling.
991 * This code modifies the X and Y coordinates according to the formula:
993 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
995 * (See brw_blorp_blit_program).
997 * It can only translate between W and Y tiling, so new_tiling and old_tiling
998 * are booleans where true represents W tiling and false represents Y tiling.
1001 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1003 if (old_tiled_w
== new_tiled_w
)
1006 /* In the code that follows, we can safely assume that S = 0, because W
1007 * tiling formats always use IMS layout.
1012 /* Given X and Y coordinates that describe an address using Y tiling,
1013 * translate to the X and Y coordinates that describe the same address
1016 * If we break down the low order bits of X and Y, using a
1017 * single letter to represent each low-order bit:
1019 * X = A << 7 | 0bBCDEFGH
1020 * Y = J << 5 | 0bKLMNP (1)
1022 * Then we can apply the Y tiling formula to see the memory offset being
1025 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1027 * If we apply the W detiling formula to this memory location, that the
1028 * corresponding X' and Y' coordinates are:
1030 * X' = A << 6 | 0bBCDPFH (3)
1031 * Y' = J << 6 | 0bKLMNEG
1033 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1034 * we need to make the following computation:
1036 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1037 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1039 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1040 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1041 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1042 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1043 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1044 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1045 emit_or(Xp
, t1
, t2
);
1046 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1047 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1048 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1049 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1050 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1051 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1052 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1053 emit_or(Yp
, t1
, t2
);
1056 /* Applying the same logic as above, but in reverse, we obtain the
1059 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1060 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1062 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1063 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1064 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1065 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1066 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1067 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1068 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1069 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1071 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1072 emit_or(Xp
, t1
, t2
);
1073 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1074 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1075 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1076 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1077 emit_or(Yp
, t1
, t2
);
1083 * Emit code to compensate for the difference between MSAA and non-MSAA
1086 * This code modifies the X and Y coordinates according to the formula:
1088 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1090 * (See brw_blorp_blit_program).
1093 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1094 intel_msaa_layout layout
)
1097 case INTEL_MSAA_LAYOUT_NONE
:
1098 /* No translation necessary, and S should already be zero. */
1101 case INTEL_MSAA_LAYOUT_CMS
:
1102 /* We can't compensate for compressed layout since at this point in the
1103 * program we haven't read from the MCS buffer.
1105 unreachable("Bad layout in encode_msaa");
1106 case INTEL_MSAA_LAYOUT_UMS
:
1107 /* No translation necessary. */
1109 case INTEL_MSAA_LAYOUT_IMS
:
1110 switch (num_samples
) {
1112 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1113 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1114 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1116 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1118 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1119 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1121 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1123 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1124 emit_or(Xp
, t1
, t2
);
1125 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1126 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1128 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1129 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1131 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1132 emit_or(Yp
, t1
, t2
);
1135 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1136 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1138 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1140 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1141 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1143 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1144 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1145 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1146 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1147 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1150 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1151 emit_or(Xp
, t1
, t2
);
1152 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1153 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1155 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1156 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1158 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1159 emit_or(Yp
, t1
, t2
);
1169 * Emit code to compensate for the difference between MSAA and non-MSAA
1172 * This code modifies the X and Y coordinates according to the formula:
1174 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1176 * (See brw_blorp_blit_program).
1179 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1180 intel_msaa_layout layout
)
1183 case INTEL_MSAA_LAYOUT_NONE
:
1184 /* No translation necessary, and S should already be zero. */
1187 case INTEL_MSAA_LAYOUT_CMS
:
1188 /* We can't compensate for compressed layout since at this point in the
1189 * program we don't have access to the MCS buffer.
1191 unreachable("Bad layout in encode_msaa");
1192 case INTEL_MSAA_LAYOUT_UMS
:
1193 /* No translation necessary. */
1195 case INTEL_MSAA_LAYOUT_IMS
:
1197 switch (num_samples
) {
1199 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1200 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1201 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1202 * S = (Y & 0b10) | (X & 0b10) >> 1
1204 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1205 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1206 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1207 emit_or(Xp
, t1
, t2
);
1208 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1209 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1210 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1211 emit_or(Yp
, t1
, t2
);
1212 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1213 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1214 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1218 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1219 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1220 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1221 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1223 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1224 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1225 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1226 emit_or(Xp
, t1
, t2
);
1227 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1228 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1229 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1230 emit_or(Yp
, t1
, t2
);
1231 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1232 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1233 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1234 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1235 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1246 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1250 brw_blorp_blit_program::translate_dst_to_src()
1252 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1253 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1254 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1255 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1257 /* Move the UD coordinates to float registers. */
1260 /* Scale and offset */
1261 emit_mad(X_f
, x_transform
.offset
, Xp_f
, x_transform
.multiplier
);
1262 emit_mad(Y_f
, y_transform
.offset
, Yp_f
, y_transform
.multiplier
);
1263 if (key
->blit_scaled
&& key
->blend
) {
1264 /* Translate coordinates to lay out the samples in a rectangular grid
1265 * roughly corresponding to sample locations.
1267 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1268 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1269 /* Adjust coordinates so that integers represent pixel centers rather
1272 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1273 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1275 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1276 * texels on texture edges.
1278 clamp_tex_coords(X_f
, Y_f
,
1279 brw_imm_f(0.0), brw_imm_f(0.0),
1280 rect_grid_x1
, rect_grid_y1
);
1282 /* Store the fractional parts to be used as bilinear interpolation
1285 emit_frc(x_frac
, X_f
);
1286 emit_frc(y_frac
, Y_f
);
1288 /* Round the float coordinates down to nearest integer */
1289 emit_rndd(Xp_f
, X_f
);
1290 emit_rndd(Yp_f
, Y_f
);
1291 emit_mul(X_f
, Xp_f
, brw_imm_f(1.0f
/ key
->x_scale
));
1292 emit_mul(Y_f
, Yp_f
, brw_imm_f(1.0f
/ key
->y_scale
));
1294 } else if (!key
->bilinear_filter
) {
1295 /* Round the float coordinates down to nearest integer by moving to
1305 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1306 struct brw_reg regY
,
1307 struct brw_reg clampX0
,
1308 struct brw_reg clampY0
,
1309 struct brw_reg clampX1
,
1310 struct brw_reg clampY1
)
1312 emit_max(regX
, regX
, clampX0
);
1313 emit_max(regY
, regY
, clampY0
);
1314 emit_min(regX
, regX
, clampX1
);
1315 emit_min(regY
, regY
, clampY1
);
1319 * Emit code to transform the X and Y coordinates as needed for blending
1320 * together the different samples in an MSAA texture.
1323 brw_blorp_blit_program::single_to_blend()
1325 /* When looking up samples in an MSAA texture using the SAMPLE message,
1326 * Gen6 requires the texture coordinates to be odd integers (so that they
1327 * correspond to the center of a 2x2 block representing the four samples
1328 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1329 * each by 2 and then add 1.
1331 emit_shl(t1
, X
, brw_imm_w(1));
1332 emit_shl(t2
, Y
, brw_imm_w(1));
1333 emit_add(Xp
, t1
, brw_imm_w(1));
1334 emit_add(Yp
, t2
, brw_imm_w(1));
1340 * Count the number of trailing 1 bits in the given value. For example:
1342 * count_trailing_one_bits(0) == 0
1343 * count_trailing_one_bits(7) == 3
1344 * count_trailing_one_bits(11) == 2
1346 static inline int count_trailing_one_bits(unsigned value
)
1348 #ifdef HAVE___BUILTIN_CTZ
1349 return __builtin_ctz(~value
);
1351 return _mesa_bitcount(value
& ~(value
+ 1));
1357 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1359 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1362 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1364 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1366 * This ensures that when all samples have the same value, no numerical
1367 * precision is lost, since each addition operation always adds two equal
1368 * values, and summing two equal floating point values does not lose
1371 * We perform this computation by treating the texture_data array as a
1372 * stack and performing the following operations:
1374 * - push sample 0 onto stack
1375 * - push sample 1 onto stack
1376 * - add top two stack entries
1377 * - push sample 2 onto stack
1378 * - push sample 3 onto stack
1379 * - add top two stack entries
1380 * - add top two stack entries
1381 * - divide top stack entry by 4
1383 * Note that after pushing sample i onto the stack, the number of add
1384 * operations we do is equal to the number of trailing 1 bits in i. This
1385 * works provided the total number of samples is a power of two, which it
1386 * always is for i965.
1388 * For integer formats, we replace the add operations with average
1389 * operations and skip the final division.
1391 unsigned stack_depth
= 0;
1392 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1393 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1395 /* Push sample i onto the stack */
1396 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1401 emit_mov(vec16(S
), brw_imm_ud(i
));
1403 texel_fetch(texture_data
[stack_depth
++]);
1405 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1406 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1407 * suggests an optimization:
1409 * "A simple optimization with probable large return in
1410 * performance is to compare the MCS value to zero (indicating
1411 * all samples are on sample slice 0), and sample only from
1412 * sample slice 0 using ld2dss if MCS is zero."
1414 * Note that in the case where the MCS value is zero, sampling from
1415 * sample slice 0 using ld2dss and sampling from sample 0 using
1416 * ld2dms are equivalent (since all samples are on sample slice 0).
1417 * Since we have already sampled from sample 0, all we need to do is
1418 * skip the remaining fetches and averaging if MCS is zero.
1420 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1423 /* Do count_trailing_one_bits(i) times */
1424 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1425 assert(stack_depth
>= 2);
1428 /* TODO: should use a smaller loop bound for non_RGBA formats */
1429 for (int k
= 0; k
< 4; ++k
) {
1430 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1431 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1432 offset(texture_data
[stack_depth
- 1], 2*k
),
1433 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1434 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1439 /* We should have just 1 sample on the stack now. */
1440 assert(stack_depth
== 1);
1442 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1443 /* Scale the result down by a factor of num_samples */
1444 /* TODO: should use a smaller loop bound for non-RGBA formats */
1445 for (int j
= 0; j
< 4; ++j
) {
1446 emit_mul(offset(texture_data
[0], 2*j
),
1447 offset(vec8(texture_data
[0]), 2*j
),
1448 brw_imm_f(1.0f
/ num_samples
));
1452 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1457 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1459 /* We do this computation by performing the following operations:
1461 * In case of 4x, 8x MSAA:
1462 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1463 * which are later used for interpolation
1464 * - linearly interpolate samples a and b in X
1465 * - linearly interpolate samples c and d in X
1466 * - linearly interpolate the results of last two operations in Y
1468 * result = lrp(lrp(a + b) + lrp(c + d))
1470 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1471 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1472 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1473 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1475 for (unsigned i
= 0; i
< 4; ++i
) {
1476 assert(i
< ARRAY_SIZE(texture_data
));
1479 /* Compute pixel coordinates */
1480 emit_add(vec16(x_sample_coords
), Xp_f
,
1481 brw_imm_f((float)(i
& 0x1) * (1.0f
/ key
->x_scale
)));
1482 emit_add(vec16(y_sample_coords
), Yp_f
,
1483 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0f
/ key
->y_scale
)));
1484 emit_mov(vec16(X
), x_sample_coords
);
1485 emit_mov(vec16(Y
), y_sample_coords
);
1487 /* The MCS value we fetch has to match up with the pixel that we're
1488 * sampling from. Since we sample from different pixels in each
1489 * iteration of this "for" loop, the call to mcs_fetch() should be
1490 * here inside the loop after computing the pixel coordinates.
1492 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1495 /* Compute sample index and map the sample index to a sample number.
1496 * Sample index layout shows the numbering of slots in a rectangular
1497 * grid of samples with in a pixel. Sample number layout shows the
1498 * rectangular grid of samples roughly corresponding to the real sample
1499 * locations with in a pixel.
1500 * In case of 4x MSAA, layout of sample indices matches the layout of
1508 * In case of 8x MSAA the two layouts don't match.
1509 * sample index layout : --------- sample number layout : ---------
1510 * | 0 | 1 | | 5 | 2 |
1511 * --------- ---------
1512 * | 2 | 3 | | 4 | 6 |
1513 * --------- ---------
1514 * | 4 | 5 | | 0 | 3 |
1515 * --------- ---------
1516 * | 6 | 7 | | 7 | 1 |
1517 * --------- ---------
1519 emit_frc(vec16(t1_f
), x_sample_coords
);
1520 emit_frc(vec16(t2_f
), y_sample_coords
);
1521 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1522 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1523 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1524 emit_mov(vec16(S
), t1_f
);
1526 if (num_samples
== 8) {
1527 /* Map the sample index to a sample number */
1528 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1530 emit_mov(vec16(t2
), brw_imm_d(5));
1531 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1532 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1533 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1537 emit_mov(vec16(t2
), brw_imm_d(0));
1538 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1539 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1540 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1543 emit_mov(vec16(S
), t2
);
1545 texel_fetch(texture_data
[i
]);
1548 #define SAMPLE(x, y) offset(texture_data[x], y)
1549 for (int index
= 3; index
> 0; ) {
1550 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1551 * Counter value of 8 in 'for' loop below is used to interpolate all
1552 * the color components.
1554 for (int k
= 0; k
< 8; k
+= 2)
1555 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1557 vec8(SAMPLE(index
, k
)),
1558 vec8(SAMPLE(index
- 1, k
)));
1561 for (int k
= 0; k
< 8; k
+= 2)
1562 emit_lrp(vec8(SAMPLE(0, k
)),
1565 vec8(SAMPLE(0, k
)));
1570 * Emit code to look up a value in the texture using the SAMPLE message (which
1571 * does blending of MSAA surfaces).
1574 brw_blorp_blit_program::sample(struct brw_reg dst
)
1576 static const sampler_message_arg args
[2] = {
1577 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1578 SAMPLER_MESSAGE_ARG_V_FLOAT
1581 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1585 * Emit code to look up a value in the texture using the SAMPLE_LD message
1586 * (which does a simple texel fetch).
1589 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1591 static const sampler_message_arg gen6_args
[5] = {
1592 SAMPLER_MESSAGE_ARG_U_INT
,
1593 SAMPLER_MESSAGE_ARG_V_INT
,
1594 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1595 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1596 SAMPLER_MESSAGE_ARG_SI_INT
1598 static const sampler_message_arg gen7_ld_args
[3] = {
1599 SAMPLER_MESSAGE_ARG_U_INT
,
1600 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1601 SAMPLER_MESSAGE_ARG_V_INT
1603 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1604 SAMPLER_MESSAGE_ARG_SI_INT
,
1605 SAMPLER_MESSAGE_ARG_U_INT
,
1606 SAMPLER_MESSAGE_ARG_V_INT
1608 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1609 SAMPLER_MESSAGE_ARG_SI_INT
,
1610 SAMPLER_MESSAGE_ARG_MCS_INT
,
1611 SAMPLER_MESSAGE_ARG_U_INT
,
1612 SAMPLER_MESSAGE_ARG_V_INT
1617 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1620 switch (key
->tex_layout
) {
1621 case INTEL_MSAA_LAYOUT_IMS
:
1622 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1625 * If this field is MSFMT_DEPTH_STENCIL
1626 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1627 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1629 * So fall through to emit the same message as we use for
1630 * INTEL_MSAA_LAYOUT_CMS.
1632 case INTEL_MSAA_LAYOUT_CMS
:
1633 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1634 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1636 case INTEL_MSAA_LAYOUT_UMS
:
1637 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1638 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1640 case INTEL_MSAA_LAYOUT_NONE
:
1642 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1643 ARRAY_SIZE(gen7_ld_args
));
1648 unreachable("Should not get here.");
1653 brw_blorp_blit_program::mcs_fetch()
1655 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1656 SAMPLER_MESSAGE_ARG_U_INT
,
1657 SAMPLER_MESSAGE_ARG_V_INT
1659 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1660 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1664 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1666 const sampler_message_arg
*args
,
1669 struct brw_reg mrf
=
1670 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1671 for (int arg
= 0; arg
< num_args
; ++arg
) {
1672 switch (args
[arg
]) {
1673 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1674 if (key
->bilinear_filter
)
1675 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1676 retype(X
, BRW_REGISTER_TYPE_F
));
1678 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1680 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1681 if (key
->bilinear_filter
)
1682 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1683 retype(Y
, BRW_REGISTER_TYPE_F
));
1685 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1687 case SAMPLER_MESSAGE_ARG_U_INT
:
1690 case SAMPLER_MESSAGE_ARG_V_INT
:
1693 case SAMPLER_MESSAGE_ARG_SI_INT
:
1694 /* Note: on Gen7, this code may be reached with s_is_zero==true
1695 * because in Gen7's ld2dss message, the sample index is the first
1696 * argument. When this happens, we need to move a 0 into the
1697 * appropriate message register.
1700 emit_mov(mrf
, brw_imm_ud(0));
1704 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1705 switch (key
->tex_layout
) {
1706 case INTEL_MSAA_LAYOUT_CMS
:
1707 emit_mov(mrf
, mcs_data
);
1709 case INTEL_MSAA_LAYOUT_IMS
:
1710 /* When sampling from an IMS surface, MCS data is not relevant,
1711 * and the hardware ignores it. So don't bother populating it.
1715 /* We shouldn't be trying to send MCS data with any other
1718 assert (!"Unsupported layout for MCS data");
1722 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1723 emit_mov(mrf
, brw_imm_ud(0));
1729 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1732 mrf
.nr
- base_mrf
/* msg_length */);
1740 #undef SWAP_XY_AND_XPYP
1743 brw_blorp_blit_program::render_target_write()
1745 struct brw_reg mrf_rt_write
=
1746 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1749 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1750 * so that the render target knows which pixels we killed.
1752 bool use_header
= key
->use_kill
;
1754 /* Copy R0/1 to MRF */
1755 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1756 retype(R0
, BRW_REGISTER_TYPE_UD
));
1760 /* Copy texture data to MRFs */
1761 for (int i
= 0; i
< 4; ++i
) {
1762 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1763 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1764 offset(vec8(texture_data
[0]), 2*i
));
1768 /* Now write to the render target and terminate the thread */
1769 emit_render_target_write(
1772 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1778 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1779 GLfloat dst0
, GLfloat dst1
,
1782 float scale
= (src1
- src0
) / (dst1
- dst0
);
1784 /* When not mirroring a coordinate (say, X), we need:
1785 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1787 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1789 * blorp program uses "round toward zero" to convert the
1790 * transformed floating point coordinates to integer coordinates,
1791 * whereas the behaviour we actually want is "round to nearest",
1792 * so 0.5 provides the necessary correction.
1795 offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
1797 /* When mirroring X we need:
1798 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1800 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1802 multiplier
= -scale
;
1803 offset
= src0
+ (dst1
- 0.5f
) * scale
;
1809 * Determine which MSAA layout the GPU pipeline should be configured for,
1810 * based on the chip generation, the number of samples, and the true layout of
1811 * the image in memory.
1813 inline intel_msaa_layout
1814 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1815 intel_msaa_layout true_layout
)
1817 if (num_samples
<= 1) {
1818 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1819 * format buffers, by transforming coordinates appropriately.
1821 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1822 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1823 return INTEL_MSAA_LAYOUT_NONE
;
1825 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1828 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1829 if (brw
->gen
== 6) {
1830 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1837 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1838 struct intel_mipmap_tree
*src_mt
,
1839 unsigned src_level
, unsigned src_layer
,
1840 mesa_format src_format
,
1841 struct intel_mipmap_tree
*dst_mt
,
1842 unsigned dst_level
, unsigned dst_layer
,
1843 mesa_format dst_format
,
1844 GLfloat src_x0
, GLfloat src_y0
,
1845 GLfloat src_x1
, GLfloat src_y1
,
1846 GLfloat dst_x0
, GLfloat dst_y0
,
1847 GLfloat dst_x1
, GLfloat dst_y1
,
1849 bool mirror_x
, bool mirror_y
)
1851 src
.set(brw
, src_mt
, src_level
, src_layer
, src_format
, false);
1852 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, dst_format
, true);
1854 /* Even though we do multisample resolves at the time of the blit, OpenGL
1855 * specification defines them as if they happen at the time of rendering,
1856 * which means that the type of averaging we do during the resolve should
1857 * only depend on the source format; the destination format should be
1858 * ignored. But, specification doesn't seem to be strict about it.
1860 * It has been observed that mulitisample resolves produce slightly better
1861 * looking images when averaging is done using destination format. NVIDIA's
1862 * proprietary OpenGL driver also follow this approach. So, we choose to
1863 * follow it in our driver.
1865 * When multisampling, if the source and destination formats are equal
1866 * (aside from the color space), we choose to blit in sRGB space to get
1867 * this higher quality image.
1869 if (src
.num_samples
> 1 &&
1870 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1871 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1872 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1873 assert(brw
->format_supported_as_render_target
[dst_mt
->format
]);
1874 dst
.brw_surfaceformat
= brw
->render_target_format
[dst_mt
->format
];
1875 src
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1878 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1879 * texture, the above code configures the source format for L32_FLOAT or
1880 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1881 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1882 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1883 * around the problem by using a source format of R32_FLOAT. This
1884 * shouldn't affect rendering correctness, since the destination format is
1885 * R32_FLOAT, so only the contents of the red channel matters.
1887 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1888 src_mt
->format
== dst_mt
->format
&&
1889 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1890 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1894 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1896 /* texture_data_type indicates the register type that should be used to
1897 * manipulate texture data.
1899 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1900 case GL_UNSIGNED_NORMALIZED
:
1901 case GL_SIGNED_NORMALIZED
:
1903 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1905 case GL_UNSIGNED_INT
:
1906 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1907 /* We process stencil as though it's an unsigned normalized color */
1908 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1910 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1914 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1917 unreachable("Unrecognized blorp format");
1921 /* Gen7's rendering hardware only supports the IMS layout for depth and
1922 * stencil render targets. Blorp always maps its destination surface as
1923 * a color render target (even if it's actually a depth or stencil
1924 * buffer). So if the destination is IMS, we'll have to map it as a
1925 * single-sampled texture and interleave the samples ourselves.
1927 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1928 dst
.num_samples
= 0;
1931 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1932 /* If the destination surface is a W-tiled multisampled stencil buffer
1933 * that we're mapping as Y tiled, then we need to arrange for the WM
1934 * program to run once per sample rather than once per pixel, because
1935 * the memory layout of related samples doesn't match between W and Y
1938 wm_prog_key
.persample_msaa_dispatch
= true;
1941 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1942 /* We are blitting from a multisample buffer to a multisample buffer, so
1943 * we must preserve samples within a pixel. This means we have to
1944 * arrange for the WM program to run once per sample rather than once
1947 wm_prog_key
.persample_msaa_dispatch
= true;
1950 /* Scaled blitting or not. */
1951 wm_prog_key
.blit_scaled
=
1952 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1953 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1955 /* Scaling factors used for bilinear filtering in multisample scaled
1958 wm_prog_key
.x_scale
= 2.0f
;
1959 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0f
;
1961 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
1962 wm_prog_key
.bilinear_filter
= true;
1964 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1965 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1966 base_format
!= GL_STENCIL_INDEX
&&
1967 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1968 /* We are downsampling a color buffer, so blend. */
1969 wm_prog_key
.blend
= true;
1972 /* src_samples and dst_samples are the true sample counts */
1973 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1974 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1976 /* tex_samples and rt_samples are the sample counts that are set up in
1979 wm_prog_key
.tex_samples
= src
.num_samples
;
1980 wm_prog_key
.rt_samples
= dst
.num_samples
;
1982 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1983 * use to access the source and destination surfaces.
1985 wm_prog_key
.tex_layout
=
1986 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1987 wm_prog_key
.rt_layout
=
1988 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1990 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1993 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1994 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1996 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1997 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1998 /* Round floating point values to nearest integer to avoid "off by one texel"
1999 * kind of errors when blitting.
2001 x0
= wm_push_consts
.dst_x0
= roundf(dst_x0
);
2002 y0
= wm_push_consts
.dst_y0
= roundf(dst_y0
);
2003 x1
= wm_push_consts
.dst_x1
= roundf(dst_x1
);
2004 y1
= wm_push_consts
.dst_y1
= roundf(dst_y1
);
2005 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
2006 wm_prog_key
.x_scale
- 1.0f
);
2007 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
2008 wm_prog_key
.y_scale
- 1.0f
);
2010 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2011 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2013 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2014 /* We must expand the rectangle we send through the rendering pipeline,
2015 * to account for the fact that we are mapping the destination region as
2016 * single-sampled when it is in fact multisampled. We must also align
2017 * it to a multiple of the multisampling pattern, because the
2018 * differences between multisampled and single-sampled surface formats
2019 * will mean that pixels are scrambled within the multisampling pattern.
2020 * TODO: what if this makes the coordinates too large?
2022 * Note: this only works if the destination surface uses the IMS layout.
2023 * If it's UMS, then we have no choice but to set up the rendering
2024 * pipeline as multisampled.
2026 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2027 switch (dst_mt
->num_samples
) {
2029 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2030 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2031 x1
= ALIGN(x1
* 2, 4);
2032 y1
= ALIGN(y1
* 2, 4);
2035 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2036 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2037 x1
= ALIGN(x1
* 4, 8);
2038 y1
= ALIGN(y1
* 2, 4);
2041 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2043 wm_prog_key
.use_kill
= true;
2046 if (dst
.map_stencil_as_y_tiled
) {
2047 /* We must modify the rectangle we send through the rendering pipeline
2048 * (and the size and x/y offset of the destination surface), to account
2049 * for the fact that we are mapping it as Y-tiled when it is in fact
2052 * Both Y tiling and W tiling can be understood as organizations of
2053 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2054 * is different, but the layout of the 32-byte sub-tiles within the 4k
2055 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2056 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2057 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2059 * Therefore, to account for the layout differences within the 32-byte
2060 * sub-tiles, we must expand the rectangle so the X coordinates of its
2061 * edges are multiples of 8 (the W sub-tile width), and its Y
2062 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2063 * Then we need to scale the X and Y coordinates of the rectangle to
2064 * account for the differences in aspect ratio between the Y and W
2065 * sub-tiles. We need to modify the layer width and height similarly.
2067 * A correction needs to be applied when MSAA is in use: since
2068 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2069 * we need to align the Y coordinates to multiples of 8, so that when
2070 * they are divided by two they are still multiples of 4.
2072 * Note: Since the x/y offset of the surface will be applied using the
2073 * SURFACE_STATE command packet, it will be invisible to the swizzling
2074 * code in the shader; therefore it needs to be in a multiple of the
2075 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2076 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2077 * buffer), and the miplevel alignment used for stencil buffers is 8
2078 * pixels horizontally and either 4 or 8 pixels vertically (see
2079 * intel_horizontal_texture_alignment_unit() and
2080 * intel_vertical_texture_alignment_unit()).
2082 * Note: Also, since the SURFACE_STATE command packet can only apply
2083 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2084 * vertically, it is important that the offsets will be multiples of
2085 * these sizes after they are converted into Y-tiled coordinates.
2086 * Fortunately they will be, since we know from above that the offsets
2087 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2088 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2090 * TODO: what if this makes the coordinates (or the texture size) too
2093 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2094 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2095 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2096 x1
= ALIGN(x1
, x_align
) * 2;
2097 y1
= ALIGN(y1
, y_align
) / 2;
2098 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2099 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2102 wm_prog_key
.use_kill
= true;
2105 if (src
.map_stencil_as_y_tiled
) {
2106 /* We must modify the size and x/y offset of the source surface to
2107 * account for the fact that we are mapping it as Y-tiled when it is in
2110 * See the comments above concerning x/y offset alignment for the
2111 * destination surface.
2113 * TODO: what if this makes the texture size too large?
2115 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2116 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2117 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2124 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2125 brw_blorp_prog_data
**prog_data
) const
2127 uint32_t prog_offset
= 0;
2128 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_BLIT_PROG
,
2129 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2130 &prog_offset
, prog_data
)) {
2131 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
,
2132 INTEL_DEBUG
& DEBUG_BLORP
);
2133 GLuint program_size
;
2134 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2135 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_BLIT_PROG
,
2136 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2137 program
, program_size
,
2138 &prog
.prog_data
, sizeof(prog
.prog_data
),
2139 &prog_offset
, prog_data
);