2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
49 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
50 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
51 * the physical layer holding sample 0. So, for example, if
52 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
56 brw_blorp_blit_miptrees(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*src_mt
,
58 unsigned src_level
, unsigned src_layer
,
59 struct intel_mipmap_tree
*dst_mt
,
60 unsigned dst_level
, unsigned dst_layer
,
61 float src_x0
, float src_y0
,
62 float src_x1
, float src_y1
,
63 float dst_x0
, float dst_y0
,
64 float dst_x1
, float dst_y1
,
65 GLenum filter
, bool mirror_x
, bool mirror_y
)
67 /* Get ready to blit. This includes depth resolving the src and dst
68 * buffers if necessary. Note: it's not necessary to do a color resolve on
69 * the destination buffer because we use the standard render path to render
70 * to destination color buffers, and the standard render path is
73 intel_miptree_resolve_color(brw
, src_mt
);
74 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
75 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
77 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
78 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
80 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
81 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
82 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
83 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
86 brw_blorp_blit_params
params(brw
,
87 src_mt
, src_level
, src_layer
,
88 dst_mt
, dst_level
, dst_layer
,
93 filter
, mirror_x
, mirror_y
);
94 brw_blorp_exec(brw
, ¶ms
);
96 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
100 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
101 struct intel_renderbuffer
*src_irb
,
102 struct intel_renderbuffer
*dst_irb
,
103 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
104 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
105 GLenum filter
, bool mirror_x
, bool mirror_y
)
107 /* Find source/dst miptrees */
108 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
109 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
112 brw_blorp_blit_miptrees(brw
,
113 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
114 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
115 srcX0
, srcY0
, srcX1
, srcY1
,
116 dstX0
, dstY0
, dstX1
, dstY1
,
117 filter
, mirror_x
, mirror_y
);
119 dst_irb
->need_downsample
= true;
123 try_blorp_blit(struct brw_context
*brw
,
124 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
125 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
126 GLenum filter
, GLbitfield buffer_bit
)
128 struct gl_context
*ctx
= &brw
->ctx
;
130 /* Sync up the state of window system buffers. We need to do this before
131 * we go looking for the buffers.
133 intel_prepare_render(brw
);
135 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
136 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
138 bool mirror_x
, mirror_y
;
139 if (brw_meta_mirror_clip_and_scissor(ctx
,
140 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
141 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
142 &mirror_x
, &mirror_y
))
146 struct intel_renderbuffer
*src_irb
;
147 struct intel_renderbuffer
*dst_irb
;
148 struct intel_mipmap_tree
*src_mt
;
149 struct intel_mipmap_tree
*dst_mt
;
150 switch (buffer_bit
) {
151 case GL_COLOR_BUFFER_BIT
:
152 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
153 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
154 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
156 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
157 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
158 filter
, mirror_x
, mirror_y
);
161 case GL_DEPTH_BUFFER_BIT
:
163 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
165 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
166 src_mt
= find_miptree(buffer_bit
, src_irb
);
167 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
169 /* We can't handle format conversions between Z24 and other formats
170 * since we have to lie about the surface format. See the comments in
171 * brw_blorp_surface_info::set().
173 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
174 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
177 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
178 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
179 filter
, mirror_x
, mirror_y
);
181 case GL_STENCIL_BUFFER_BIT
:
183 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
185 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
186 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
187 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
188 filter
, mirror_x
, mirror_y
);
191 unreachable("not reached");
198 brw_blorp_copytexsubimage(struct brw_context
*brw
,
199 struct gl_renderbuffer
*src_rb
,
200 struct gl_texture_image
*dst_image
,
202 int srcX0
, int srcY0
,
203 int dstX0
, int dstY0
,
204 int width
, int height
)
206 struct gl_context
*ctx
= &brw
->ctx
;
207 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
208 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
210 /* Sync up the state of window system buffers. We need to do this before
211 * we go looking at the src renderbuffer's miptree.
213 intel_prepare_render(brw
);
215 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
216 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
218 /* BLORP is not supported before Gen6. */
219 if (brw
->gen
< 6 || brw
->gen
>= 8)
222 if (_mesa_get_format_base_format(src_mt
->format
) !=
223 _mesa_get_format_base_format(dst_mt
->format
)) {
227 /* We can't handle format conversions between Z24 and other formats since
228 * we have to lie about the surface format. See the comments in
229 * brw_blorp_surface_info::set().
231 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
232 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
236 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
239 /* Source clipping shouldn't be necessary, since copytexsubimage (in
240 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
243 * Destination clipping shouldn't be necessary since the restrictions on
244 * glCopyTexSubImage prevent the user from specifying a destination rectangle
245 * that falls outside the bounds of the destination texture.
246 * See error_check_subtexture_dimensions().
249 int srcY1
= srcY0
+ height
;
250 int srcX1
= srcX0
+ width
;
251 int dstX1
= dstX0
+ width
;
252 int dstY1
= dstY0
+ height
;
254 /* Account for the fact that in the system framebuffer, the origin is at
257 bool mirror_y
= false;
258 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
259 GLint tmp
= src_rb
->Height
- srcY0
;
260 srcY0
= src_rb
->Height
- srcY1
;
265 /* Account for face selection and texture view MinLayer */
266 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
267 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
269 _mesa_unlock_texture(ctx
, dst_image
->TexObject
);
271 brw_blorp_blit_miptrees(brw
,
272 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
273 dst_mt
, dst_level
, dst_slice
,
274 srcX0
, srcY0
, srcX1
, srcY1
,
275 dstX0
, dstY0
, dstX1
, dstY1
,
276 GL_NEAREST
, false, mirror_y
);
278 _mesa_lock_texture(ctx
, dst_image
->TexObject
);
280 /* If we're copying to a packed depth stencil texture and the source
281 * framebuffer has separate stencil, we need to also copy the stencil data
284 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
285 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
287 src_irb
= intel_renderbuffer(src_rb
);
288 src_mt
= src_irb
->mt
;
290 if (src_mt
->stencil_mt
)
291 src_mt
= src_mt
->stencil_mt
;
292 if (dst_mt
->stencil_mt
)
293 dst_mt
= dst_mt
->stencil_mt
;
295 if (src_mt
!= dst_mt
) {
296 brw_blorp_blit_miptrees(brw
,
297 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
298 dst_mt
, dst_level
, dst_slice
,
299 srcX0
, srcY0
, srcX1
, srcY1
,
300 dstX0
, dstY0
, dstX1
, dstY1
,
301 GL_NEAREST
, false, mirror_y
);
310 brw_blorp_framebuffer(struct brw_context
*brw
,
311 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
312 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
313 GLbitfield mask
, GLenum filter
)
315 /* BLORP is not supported before Gen6. */
316 if (brw
->gen
< 6 || brw
->gen
>= 8)
319 static GLbitfield buffer_bits
[] = {
322 GL_STENCIL_BUFFER_BIT
,
325 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
326 if ((mask
& buffer_bits
[i
]) &&
328 srcX0
, srcY0
, srcX1
, srcY1
,
329 dstX0
, dstY0
, dstX1
, dstY1
,
330 filter
, buffer_bits
[i
])) {
331 mask
&= ~buffer_bits
[i
];
340 * Enum to specify the order of arguments in a sampler message
342 enum sampler_message_arg
344 SAMPLER_MESSAGE_ARG_U_FLOAT
,
345 SAMPLER_MESSAGE_ARG_V_FLOAT
,
346 SAMPLER_MESSAGE_ARG_U_INT
,
347 SAMPLER_MESSAGE_ARG_V_INT
,
348 SAMPLER_MESSAGE_ARG_SI_INT
,
349 SAMPLER_MESSAGE_ARG_MCS_INT
,
350 SAMPLER_MESSAGE_ARG_ZERO_INT
,
354 * Generator for WM programs used in BLORP blits.
356 * The bulk of the work done by the WM program is to wrap and unwrap the
357 * coordinate transformations used by the hardware to store surfaces in
358 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
359 * sample index for a multisampled surface) to a memory offset by the
360 * following formulas:
362 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
363 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
365 * For a single-sampled surface, or for a multisampled surface using
366 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
369 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
370 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
371 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
372 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
374 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
375 * embeds the sample number into bit 1 of the X and Y coordinates:
377 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
378 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
379 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
380 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
381 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
382 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
383 * S = (Y & 0b10) | (X & 0b10) >> 1
385 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
386 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
389 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
390 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
391 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
392 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
393 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
394 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
395 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
397 * For X tiling, tile() combines together the low-order bits of the X and Y
398 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
399 * bytes wide and 8 rows high:
401 * tile(x_tiled, X, Y, S) = A
402 * where A = tile_num << 12 | offset
403 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
404 * offset = (Y' & 0b111) << 9
405 * | (X & 0b111111111)
407 * Y' = Y + S * qpitch
408 * detile(x_tiled, A) = (X, Y, S)
412 * Y' = (tile_num / tile_pitch) << 3
413 * | (A & 0b111000000000) >> 9
414 * X' = (tile_num % tile_pitch) << 9
415 * | (A & 0b111111111)
417 * (In all tiling formulas, cpp is the number of bytes occupied by a single
418 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
419 * to fill the width of the surface, and qpitch is the spacing (in rows)
420 * between array slices).
422 * For Y tiling, tile() combines together the low-order bits of the X and Y
423 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
424 * bytes wide and 32 rows high:
426 * tile(y_tiled, X, Y, S) = A
427 * where A = tile_num << 12 | offset
428 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
429 * offset = (X' & 0b1110000) << 5
430 * | (Y' & 0b11111) << 4
433 * Y' = Y + S * qpitch
434 * detile(y_tiled, A) = (X, Y, S)
438 * Y' = (tile_num / tile_pitch) << 5
439 * | (A & 0b111110000) >> 4
440 * X' = (tile_num % tile_pitch) << 7
441 * | (A & 0b111000000000) >> 5
444 * For W tiling, tile() combines together the low-order bits of the X and Y
445 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
446 * bytes wide and 64 rows high (note that W tiling is only used for stencil
447 * buffers, which always have cpp = 1 and S=0):
449 * tile(w_tiled, X, Y, S) = A
450 * where A = tile_num << 12 | offset
451 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
452 * offset = (X' & 0b111000) << 6
453 * | (Y' & 0b111100) << 3
454 * | (X' & 0b100) << 2
460 * Y' = Y + S * qpitch
461 * detile(w_tiled, A) = (X, Y, S)
462 * where X = X' / cpp = X'
463 * Y = Y' % qpitch = Y'
465 * Y' = (tile_num / tile_pitch) << 6
466 * | (A & 0b111100000) >> 3
467 * | (A & 0b1000) >> 2
469 * X' = (tile_num % tile_pitch) << 6
470 * | (A & 0b111000000000) >> 6
471 * | (A & 0b10000) >> 2
475 * Finally, for a non-tiled surface, tile() simply combines together the X and
476 * Y coordinates in the natural way:
478 * tile(untiled, X, Y, S) = A
479 * where A = Y * pitch + X'
481 * Y' = Y + S * qpitch
482 * detile(untiled, A) = (X, Y, S)
489 * (In these formulas, pitch is the number of bytes occupied by a single row
492 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
495 brw_blorp_blit_program(struct brw_context
*brw
,
496 const brw_blorp_blit_prog_key
*key
, bool debug_flag
);
498 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
500 brw_blorp_prog_data prog_data
;
504 void alloc_push_const_regs(int base_reg
);
505 void compute_frag_coords();
506 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
507 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
508 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
509 void translate_dst_to_src();
510 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
511 struct brw_reg clampX0
, struct brw_reg clampY0
,
512 struct brw_reg clampX1
, struct brw_reg clampY1
);
513 void single_to_blend();
514 void manual_blend_average(unsigned num_samples
);
515 void manual_blend_bilinear(unsigned num_samples
);
516 void sample(struct brw_reg dst
);
517 void texel_fetch(struct brw_reg dst
);
519 void texture_lookup(struct brw_reg dst
, enum opcode op
,
520 const sampler_message_arg
*args
, int num_args
);
521 void render_target_write();
524 * Base-2 logarithm of the maximum number of samples that can be blended.
526 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
528 struct brw_context
*brw
;
529 const brw_blorp_blit_prog_key
*key
;
531 /* Thread dispatch header */
534 /* Pixel X/Y coordinates (always in R1). */
538 struct brw_reg dst_x0
;
539 struct brw_reg dst_x1
;
540 struct brw_reg dst_y0
;
541 struct brw_reg dst_y1
;
542 /* Top right coordinates of the rectangular grid used for scaled blitting */
543 struct brw_reg rect_grid_x1
;
544 struct brw_reg rect_grid_y1
;
546 struct brw_reg multiplier
;
547 struct brw_reg offset
;
548 } x_transform
, y_transform
;
550 /* Data read from texture (4 vec16's per array element) */
551 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
553 /* Auxiliary storage for the contents of the MCS surface.
555 * Since the sampler always returns 8 registers worth of data, this is 8
556 * registers wide, even though we only use the first 2 registers of it.
558 struct brw_reg mcs_data
;
560 /* X coordinates. We have two of them so that we can perform coordinate
561 * transformations easily.
563 struct brw_reg x_coords
[2];
565 /* Y coordinates. We have two of them so that we can perform coordinate
566 * transformations easily.
568 struct brw_reg y_coords
[2];
570 /* X, Y coordinates of the pixel from which we need to fetch the specific
571 * sample. These are used for multisample scaled blitting.
573 struct brw_reg x_sample_coords
;
574 struct brw_reg y_sample_coords
;
576 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
577 struct brw_reg x_frac
;
578 struct brw_reg y_frac
;
580 /* Which element of x_coords and y_coords is currently in use.
584 /* True if, at the point in the program currently being compiled, the
585 * sample index is known to be zero.
589 /* Register storing the sample index when s_is_zero is false. */
590 struct brw_reg sample_index
;
596 /* MRF used for sampling and render target writes */
600 brw_blorp_blit_program::brw_blorp_blit_program(
601 struct brw_context
*brw
,
602 const brw_blorp_blit_prog_key
*key
,
604 : brw_blorp_eu_emitter(brw
, debug_flag
),
611 brw_blorp_blit_program::compile(struct brw_context
*brw
,
612 GLuint
*program_size
)
615 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
616 /* If the destination image is W tiled and multisampled, then the thread
617 * must be dispatched once per sample, not once per pixel. This is
618 * necessary because after conversion between W and Y tiling, there's no
619 * guarantee that all samples corresponding to a single pixel will still
622 assert(key
->persample_msaa_dispatch
);
626 /* We are blending, which means we won't have an opportunity to
627 * translate the tiling and sample count for the texture surface. So
628 * the surface state for the texture must be configured with the correct
629 * tiling and sample count.
631 assert(!key
->src_tiled_w
);
632 assert(key
->tex_samples
== key
->src_samples
);
633 assert(key
->tex_layout
== key
->src_layout
);
634 assert(key
->tex_samples
> 0);
637 if (key
->persample_msaa_dispatch
) {
638 /* It only makes sense to do persample dispatch if the render target is
639 * configured as multisampled.
641 assert(key
->rt_samples
> 0);
644 /* Make sure layout is consistent with sample count */
645 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
646 (key
->tex_samples
== 0));
647 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
648 (key
->rt_samples
== 0));
649 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
650 (key
->src_samples
== 0));
651 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
652 (key
->dst_samples
== 0));
654 /* Set up prog_data */
655 memset(&prog_data
, 0, sizeof(prog_data
));
656 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
659 compute_frag_coords();
661 /* Render target and texture hardware don't support W tiling. */
662 const bool rt_tiled_w
= false;
663 const bool tex_tiled_w
= false;
665 /* The address that data will be written to is determined by the
666 * coordinates supplied to the WM thread and the tiling and sample count of
667 * the render target, according to the formula:
669 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
671 * If the actual tiling and sample count of the destination surface are not
672 * the same as the configuration of the render target, then these
673 * coordinates are wrong and we have to adjust them to compensate for the
676 if (rt_tiled_w
!= key
->dst_tiled_w
||
677 key
->rt_samples
!= key
->dst_samples
||
678 key
->rt_layout
!= key
->dst_layout
) {
679 encode_msaa(key
->rt_samples
, key
->rt_layout
);
680 /* Now (X, Y, S) = detile(rt_tiling, offset) */
681 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
682 /* Now (X, Y, S) = detile(dst_tiling, offset) */
683 decode_msaa(key
->dst_samples
, key
->dst_layout
);
686 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
688 * That is: X, Y and S now contain the true coordinates and sample index of
689 * the data that the WM thread should output.
691 * If we need to kill pixels that are outside the destination rectangle,
692 * now is the time to do it.
696 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
697 y_coords
[xy_coord_index
],
698 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
700 /* Next, apply a translation to obtain coordinates in the source image. */
701 translate_dst_to_src();
703 /* If the source image is not multisampled, then we want to fetch sample
704 * number 0, because that's the only sample there is.
706 if (key
->src_samples
== 0)
709 /* X, Y, and S are now the coordinates of the pixel in the source image
710 * that we want to texture from. Exception: if we are blending, then S is
711 * irrelevant, because we are going to fetch all samples.
713 if (key
->blend
&& !key
->blit_scaled
) {
715 /* Gen6 hardware an automatically blend using the SAMPLE message */
717 sample(texture_data
[0]);
719 /* Gen7+ hardware doesn't automaticaly blend. */
720 manual_blend_average(key
->src_samples
);
722 } else if(key
->blend
&& key
->blit_scaled
) {
723 manual_blend_bilinear(key
->src_samples
);
725 /* We aren't blending, which means we just want to fetch a single sample
726 * from the source surface. The address that we want to fetch from is
727 * related to the X, Y and S values according to the formula:
729 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
731 * If the actual tiling and sample count of the source surface are not
732 * the same as the configuration of the texture, then we need to adjust
733 * the coordinates to compensate for the difference.
735 if ((tex_tiled_w
!= key
->src_tiled_w
||
736 key
->tex_samples
!= key
->src_samples
||
737 key
->tex_layout
!= key
->src_layout
) &&
738 !key
->bilinear_filter
) {
739 encode_msaa(key
->src_samples
, key
->src_layout
);
740 /* Now (X, Y, S) = detile(src_tiling, offset) */
741 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
742 /* Now (X, Y, S) = detile(tex_tiling, offset) */
743 decode_msaa(key
->tex_samples
, key
->tex_layout
);
746 if (key
->bilinear_filter
) {
747 sample(texture_data
[0]);
750 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
752 * In other words: X, Y, and S now contain values which, when passed to
753 * the texturing unit, will cause data to be read from the correct
754 * memory location. So we can fetch the texel now.
756 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
758 texel_fetch(texture_data
[0]);
762 /* Finally, write the fetched (or blended) value to the render target and
763 * terminate the thread.
765 render_target_write();
767 return get_program(program_size
);
771 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
773 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
774 #define ALLOC_REG(name, type) \
776 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
777 base_reg + CONST_LOC(name) / 32, \
778 (CONST_LOC(name) % 32) / 4), type)
780 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
781 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
782 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
783 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
784 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
785 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
786 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
787 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
788 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
789 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
795 brw_blorp_blit_program::alloc_regs()
798 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
799 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
800 prog_data
.first_curbe_grf
= reg
;
801 alloc_push_const_regs(reg
);
802 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
803 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
804 this->texture_data
[i
] =
805 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
809 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
811 for (int i
= 0; i
< 2; ++i
) {
813 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
816 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
820 if (key
->blit_scaled
&& key
->blend
) {
821 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
823 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
825 this->x_frac
= brw_vec8_grf(reg
, 0);
827 this->y_frac
= brw_vec8_grf(reg
, 0);
831 this->xy_coord_index
= 0;
833 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
835 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
837 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
840 /* Make sure we didn't run out of registers */
841 assert(reg
<= GEN7_MRF_HACK_START
);
844 this->base_mrf
= mrf
;
847 /* In the code that follows, X and Y can be used to quickly refer to the
848 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
849 * prime") to the inactive elements.
851 * S can be used to quickly refer to sample_index.
853 #define X x_coords[xy_coord_index]
854 #define Y y_coords[xy_coord_index]
855 #define Xp x_coords[!xy_coord_index]
856 #define Yp y_coords[!xy_coord_index]
857 #define S sample_index
859 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
860 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
862 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
865 * Emit code to compute the X and Y coordinates of the pixels being rendered
866 * by this WM invocation.
868 * Assuming the render target is set up for Y tiling, these (X, Y) values are
869 * related to the address offset where outputs will be written by the formula:
871 * (X, Y, S) = decode_msaa(detile(offset)).
873 * (See brw_blorp_blit_program).
876 brw_blorp_blit_program::compute_frag_coords()
878 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
879 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
880 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
881 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
883 * Pixels within a subspan are laid out in this arrangement:
887 * So, to compute the coordinates of each pixel, we need to read every 2nd
888 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
889 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
890 * In other words, the data we want to access is R1.4<2;4,0>UW.
892 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
893 * result, since pixels n+1 and n+3 are in the right half of the subspan.
895 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
896 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
898 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
899 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
900 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
903 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
904 * pixels n+2 and n+3 are in the bottom half of the subspan.
906 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
907 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
909 /* Move the coordinates to UD registers. */
910 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
911 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
914 if (key
->persample_msaa_dispatch
) {
915 switch (key
->rt_samples
) {
917 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
918 * Therefore, subspan 0 will represent sample 0, subspan 1 will
919 * represent sample 1, and so on.
921 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
922 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
923 * populate a temporary variable with the sequence (0, 1, 2, 3), and
924 * then copy from it using vstride=1, width=4, hstride=0.
926 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
927 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
928 /* Move to UD sample_index register. */
929 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
930 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
934 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
935 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
936 * subspan 1 will represent sample 1, and so on. We can find the
937 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
938 * Index") and multiplying by two (since samples are always delivered
939 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
942 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
943 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
944 * variable with the sequence (0, 1, 2, 3), and then reading from it
945 * using vstride=1, width=4, hstride=0.
947 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
948 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
949 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
950 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
951 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
952 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
953 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
954 stride(t2_uw1
, 1, 4, 0));
955 emit_add_8(offset(S
, 1),
956 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
957 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
961 unreachable("Unrecognized sample count in "
962 "brw_blorp_blit_program::compute_frag_coords()");
966 /* Either the destination surface is single-sampled, or the WM will be
967 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
968 * per pixel). In either case, it's not meaningful to compute a sample
969 * value. Just set it to 0.
976 * Emit code to compensate for the difference between Y and W tiling.
978 * This code modifies the X and Y coordinates according to the formula:
980 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
982 * (See brw_blorp_blit_program).
984 * It can only translate between W and Y tiling, so new_tiling and old_tiling
985 * are booleans where true represents W tiling and false represents Y tiling.
988 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
990 if (old_tiled_w
== new_tiled_w
)
993 /* In the code that follows, we can safely assume that S = 0, because W
994 * tiling formats always use IMS layout.
999 /* Given X and Y coordinates that describe an address using Y tiling,
1000 * translate to the X and Y coordinates that describe the same address
1003 * If we break down the low order bits of X and Y, using a
1004 * single letter to represent each low-order bit:
1006 * X = A << 7 | 0bBCDEFGH
1007 * Y = J << 5 | 0bKLMNP (1)
1009 * Then we can apply the Y tiling formula to see the memory offset being
1012 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1014 * If we apply the W detiling formula to this memory location, that the
1015 * corresponding X' and Y' coordinates are:
1017 * X' = A << 6 | 0bBCDPFH (3)
1018 * Y' = J << 6 | 0bKLMNEG
1020 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1021 * we need to make the following computation:
1023 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1024 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1026 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1027 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1028 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1029 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1030 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1031 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1032 emit_or(Xp
, t1
, t2
);
1033 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1034 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1035 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1036 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1037 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1038 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1039 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1040 emit_or(Yp
, t1
, t2
);
1043 /* Applying the same logic as above, but in reverse, we obtain the
1046 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1047 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1049 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1050 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1051 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1052 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1053 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1054 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1055 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1056 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1058 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1059 emit_or(Xp
, t1
, t2
);
1060 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1061 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1062 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1063 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1064 emit_or(Yp
, t1
, t2
);
1070 * Emit code to compensate for the difference between MSAA and non-MSAA
1073 * This code modifies the X and Y coordinates according to the formula:
1075 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1077 * (See brw_blorp_blit_program).
1080 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1081 intel_msaa_layout layout
)
1084 case INTEL_MSAA_LAYOUT_NONE
:
1085 /* No translation necessary, and S should already be zero. */
1088 case INTEL_MSAA_LAYOUT_CMS
:
1089 /* We can't compensate for compressed layout since at this point in the
1090 * program we haven't read from the MCS buffer.
1092 unreachable("Bad layout in encode_msaa");
1093 case INTEL_MSAA_LAYOUT_UMS
:
1094 /* No translation necessary. */
1096 case INTEL_MSAA_LAYOUT_IMS
:
1097 switch (num_samples
) {
1099 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1100 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1101 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1103 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1105 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1106 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1108 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1110 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1111 emit_or(Xp
, t1
, t2
);
1112 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1113 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1115 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1116 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1118 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1119 emit_or(Yp
, t1
, t2
);
1122 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1123 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1125 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1127 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1128 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1130 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1131 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1132 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1133 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1134 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1137 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1138 emit_or(Xp
, t1
, t2
);
1139 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1140 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1142 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1143 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1145 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1146 emit_or(Yp
, t1
, t2
);
1156 * Emit code to compensate for the difference between MSAA and non-MSAA
1159 * This code modifies the X and Y coordinates according to the formula:
1161 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1163 * (See brw_blorp_blit_program).
1166 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1167 intel_msaa_layout layout
)
1170 case INTEL_MSAA_LAYOUT_NONE
:
1171 /* No translation necessary, and S should already be zero. */
1174 case INTEL_MSAA_LAYOUT_CMS
:
1175 /* We can't compensate for compressed layout since at this point in the
1176 * program we don't have access to the MCS buffer.
1178 unreachable("Bad layout in encode_msaa");
1179 case INTEL_MSAA_LAYOUT_UMS
:
1180 /* No translation necessary. */
1182 case INTEL_MSAA_LAYOUT_IMS
:
1184 switch (num_samples
) {
1186 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1187 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1188 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1189 * S = (Y & 0b10) | (X & 0b10) >> 1
1191 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1192 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1193 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1194 emit_or(Xp
, t1
, t2
);
1195 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1196 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1197 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1198 emit_or(Yp
, t1
, t2
);
1199 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1200 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1201 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1205 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1206 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1207 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1208 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1210 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1211 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1212 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1213 emit_or(Xp
, t1
, t2
);
1214 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1215 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1216 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1217 emit_or(Yp
, t1
, t2
);
1218 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1219 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1220 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1221 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1222 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1233 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1237 brw_blorp_blit_program::translate_dst_to_src()
1239 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1240 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1241 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1242 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1244 /* Move the UD coordinates to float registers. */
1247 /* Scale and offset */
1248 emit_mul(X_f
, Xp_f
, x_transform
.multiplier
);
1249 emit_mul(Y_f
, Yp_f
, y_transform
.multiplier
);
1250 emit_add(X_f
, X_f
, x_transform
.offset
);
1251 emit_add(Y_f
, Y_f
, y_transform
.offset
);
1252 if (key
->blit_scaled
&& key
->blend
) {
1253 /* Translate coordinates to lay out the samples in a rectangular grid
1254 * roughly corresponding to sample locations.
1256 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1257 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1258 /* Adjust coordinates so that integers represent pixel centers rather
1261 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1262 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1264 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1265 * texels on texture edges.
1267 clamp_tex_coords(X_f
, Y_f
,
1268 brw_imm_f(0.0), brw_imm_f(0.0),
1269 rect_grid_x1
, rect_grid_y1
);
1271 /* Store the fractional parts to be used as bilinear interpolation
1274 emit_frc(x_frac
, X_f
);
1275 emit_frc(y_frac
, Y_f
);
1277 /* Round the float coordinates down to nearest integer */
1278 emit_rndd(Xp_f
, X_f
);
1279 emit_rndd(Yp_f
, Y_f
);
1280 emit_mul(X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1281 emit_mul(Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1283 } else if (!key
->bilinear_filter
) {
1284 /* Round the float coordinates down to nearest integer by moving to
1294 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1295 struct brw_reg regY
,
1296 struct brw_reg clampX0
,
1297 struct brw_reg clampY0
,
1298 struct brw_reg clampX1
,
1299 struct brw_reg clampY1
)
1301 emit_cond_mov(regX
, clampX0
, BRW_CONDITIONAL_L
, regX
, clampX0
);
1302 emit_cond_mov(regX
, clampX1
, BRW_CONDITIONAL_G
, regX
, clampX1
);
1303 emit_cond_mov(regY
, clampY0
, BRW_CONDITIONAL_L
, regY
, clampY0
);
1304 emit_cond_mov(regY
, clampY1
, BRW_CONDITIONAL_G
, regY
, clampY1
);
1308 * Emit code to transform the X and Y coordinates as needed for blending
1309 * together the different samples in an MSAA texture.
1312 brw_blorp_blit_program::single_to_blend()
1314 /* When looking up samples in an MSAA texture using the SAMPLE message,
1315 * Gen6 requires the texture coordinates to be odd integers (so that they
1316 * correspond to the center of a 2x2 block representing the four samples
1317 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1318 * each by 2 and then add 1.
1320 emit_shl(t1
, X
, brw_imm_w(1));
1321 emit_shl(t2
, Y
, brw_imm_w(1));
1322 emit_add(Xp
, t1
, brw_imm_w(1));
1323 emit_add(Yp
, t2
, brw_imm_w(1));
1329 * Count the number of trailing 1 bits in the given value. For example:
1331 * count_trailing_one_bits(0) == 0
1332 * count_trailing_one_bits(7) == 3
1333 * count_trailing_one_bits(11) == 2
1335 inline int count_trailing_one_bits(unsigned value
)
1337 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1338 return __builtin_ctz(~value
);
1340 return _mesa_bitcount(value
& ~(value
+ 1));
1346 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1348 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1351 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1353 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1355 * This ensures that when all samples have the same value, no numerical
1356 * precision is lost, since each addition operation always adds two equal
1357 * values, and summing two equal floating point values does not lose
1360 * We perform this computation by treating the texture_data array as a
1361 * stack and performing the following operations:
1363 * - push sample 0 onto stack
1364 * - push sample 1 onto stack
1365 * - add top two stack entries
1366 * - push sample 2 onto stack
1367 * - push sample 3 onto stack
1368 * - add top two stack entries
1369 * - add top two stack entries
1370 * - divide top stack entry by 4
1372 * Note that after pushing sample i onto the stack, the number of add
1373 * operations we do is equal to the number of trailing 1 bits in i. This
1374 * works provided the total number of samples is a power of two, which it
1375 * always is for i965.
1377 * For integer formats, we replace the add operations with average
1378 * operations and skip the final division.
1380 unsigned stack_depth
= 0;
1381 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1382 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1384 /* Push sample i onto the stack */
1385 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1390 emit_mov(vec16(S
), brw_imm_ud(i
));
1392 texel_fetch(texture_data
[stack_depth
++]);
1394 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1395 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1396 * suggests an optimization:
1398 * "A simple optimization with probable large return in
1399 * performance is to compare the MCS value to zero (indicating
1400 * all samples are on sample slice 0), and sample only from
1401 * sample slice 0 using ld2dss if MCS is zero."
1403 * Note that in the case where the MCS value is zero, sampling from
1404 * sample slice 0 using ld2dss and sampling from sample 0 using
1405 * ld2dms are equivalent (since all samples are on sample slice 0).
1406 * Since we have already sampled from sample 0, all we need to do is
1407 * skip the remaining fetches and averaging if MCS is zero.
1409 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1412 /* Do count_trailing_one_bits(i) times */
1413 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1414 assert(stack_depth
>= 2);
1417 /* TODO: should use a smaller loop bound for non_RGBA formats */
1418 for (int k
= 0; k
< 4; ++k
) {
1419 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1420 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1421 offset(texture_data
[stack_depth
- 1], 2*k
),
1422 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1423 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1428 /* We should have just 1 sample on the stack now. */
1429 assert(stack_depth
== 1);
1431 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1432 /* Scale the result down by a factor of num_samples */
1433 /* TODO: should use a smaller loop bound for non-RGBA formats */
1434 for (int j
= 0; j
< 4; ++j
) {
1435 emit_mul(offset(texture_data
[0], 2*j
),
1436 offset(vec8(texture_data
[0]), 2*j
),
1437 brw_imm_f(1.0/num_samples
));
1441 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1446 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1448 /* We do this computation by performing the following operations:
1450 * In case of 4x, 8x MSAA:
1451 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1452 * which are later used for interpolation
1453 * - linearly interpolate samples a and b in X
1454 * - linearly interpolate samples c and d in X
1455 * - linearly interpolate the results of last two operations in Y
1457 * result = lrp(lrp(a + b) + lrp(c + d))
1459 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1460 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1461 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1462 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1464 for (unsigned i
= 0; i
< 4; ++i
) {
1465 assert(i
< ARRAY_SIZE(texture_data
));
1468 /* Compute pixel coordinates */
1469 emit_add(vec16(x_sample_coords
), Xp_f
,
1470 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1471 emit_add(vec16(y_sample_coords
), Yp_f
,
1472 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1473 emit_mov(vec16(X
), x_sample_coords
);
1474 emit_mov(vec16(Y
), y_sample_coords
);
1476 /* The MCS value we fetch has to match up with the pixel that we're
1477 * sampling from. Since we sample from different pixels in each
1478 * iteration of this "for" loop, the call to mcs_fetch() should be
1479 * here inside the loop after computing the pixel coordinates.
1481 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1484 /* Compute sample index and map the sample index to a sample number.
1485 * Sample index layout shows the numbering of slots in a rectangular
1486 * grid of samples with in a pixel. Sample number layout shows the
1487 * rectangular grid of samples roughly corresponding to the real sample
1488 * locations with in a pixel.
1489 * In case of 4x MSAA, layout of sample indices matches the layout of
1497 * In case of 8x MSAA the two layouts don't match.
1498 * sample index layout : --------- sample number layout : ---------
1499 * | 0 | 1 | | 5 | 2 |
1500 * --------- ---------
1501 * | 2 | 3 | | 4 | 6 |
1502 * --------- ---------
1503 * | 4 | 5 | | 0 | 3 |
1504 * --------- ---------
1505 * | 6 | 7 | | 7 | 1 |
1506 * --------- ---------
1508 emit_frc(vec16(t1_f
), x_sample_coords
);
1509 emit_frc(vec16(t2_f
), y_sample_coords
);
1510 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1511 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1512 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1513 emit_mov(vec16(S
), t1_f
);
1515 if (num_samples
== 8) {
1516 /* Map the sample index to a sample number */
1517 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1519 emit_mov(vec16(t2
), brw_imm_d(5));
1520 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1521 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1522 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1526 emit_mov(vec16(t2
), brw_imm_d(0));
1527 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1528 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1529 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1532 emit_mov(vec16(S
), t2
);
1534 texel_fetch(texture_data
[i
]);
1537 #define SAMPLE(x, y) offset(texture_data[x], y)
1538 for (int index
= 3; index
> 0; ) {
1539 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1540 * Counter value of 8 in 'for' loop below is used to interpolate all
1541 * the color components.
1543 for (int k
= 0; k
< 8; k
+= 2)
1544 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1546 vec8(SAMPLE(index
, k
)),
1547 vec8(SAMPLE(index
- 1, k
)));
1550 for (int k
= 0; k
< 8; k
+= 2)
1551 emit_lrp(vec8(SAMPLE(0, k
)),
1554 vec8(SAMPLE(0, k
)));
1559 * Emit code to look up a value in the texture using the SAMPLE message (which
1560 * does blending of MSAA surfaces).
1563 brw_blorp_blit_program::sample(struct brw_reg dst
)
1565 static const sampler_message_arg args
[2] = {
1566 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1567 SAMPLER_MESSAGE_ARG_V_FLOAT
1570 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1574 * Emit code to look up a value in the texture using the SAMPLE_LD message
1575 * (which does a simple texel fetch).
1578 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1580 static const sampler_message_arg gen6_args
[5] = {
1581 SAMPLER_MESSAGE_ARG_U_INT
,
1582 SAMPLER_MESSAGE_ARG_V_INT
,
1583 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1584 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1585 SAMPLER_MESSAGE_ARG_SI_INT
1587 static const sampler_message_arg gen7_ld_args
[3] = {
1588 SAMPLER_MESSAGE_ARG_U_INT
,
1589 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1590 SAMPLER_MESSAGE_ARG_V_INT
1592 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1593 SAMPLER_MESSAGE_ARG_SI_INT
,
1594 SAMPLER_MESSAGE_ARG_U_INT
,
1595 SAMPLER_MESSAGE_ARG_V_INT
1597 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1598 SAMPLER_MESSAGE_ARG_SI_INT
,
1599 SAMPLER_MESSAGE_ARG_MCS_INT
,
1600 SAMPLER_MESSAGE_ARG_U_INT
,
1601 SAMPLER_MESSAGE_ARG_V_INT
1606 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1609 switch (key
->tex_layout
) {
1610 case INTEL_MSAA_LAYOUT_IMS
:
1611 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1614 * If this field is MSFMT_DEPTH_STENCIL
1615 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1616 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1618 * So fall through to emit the same message as we use for
1619 * INTEL_MSAA_LAYOUT_CMS.
1621 case INTEL_MSAA_LAYOUT_CMS
:
1622 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1623 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1625 case INTEL_MSAA_LAYOUT_UMS
:
1626 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1627 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1629 case INTEL_MSAA_LAYOUT_NONE
:
1631 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1632 ARRAY_SIZE(gen7_ld_args
));
1637 unreachable("Should not get here.");
1642 brw_blorp_blit_program::mcs_fetch()
1644 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1645 SAMPLER_MESSAGE_ARG_U_INT
,
1646 SAMPLER_MESSAGE_ARG_V_INT
1648 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1649 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1653 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1655 const sampler_message_arg
*args
,
1658 struct brw_reg mrf
=
1659 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1660 for (int arg
= 0; arg
< num_args
; ++arg
) {
1661 switch (args
[arg
]) {
1662 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1663 if (key
->bilinear_filter
)
1664 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1665 retype(X
, BRW_REGISTER_TYPE_F
));
1667 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1669 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1670 if (key
->bilinear_filter
)
1671 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1672 retype(Y
, BRW_REGISTER_TYPE_F
));
1674 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1676 case SAMPLER_MESSAGE_ARG_U_INT
:
1679 case SAMPLER_MESSAGE_ARG_V_INT
:
1682 case SAMPLER_MESSAGE_ARG_SI_INT
:
1683 /* Note: on Gen7, this code may be reached with s_is_zero==true
1684 * because in Gen7's ld2dss message, the sample index is the first
1685 * argument. When this happens, we need to move a 0 into the
1686 * appropriate message register.
1689 emit_mov(mrf
, brw_imm_ud(0));
1693 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1694 switch (key
->tex_layout
) {
1695 case INTEL_MSAA_LAYOUT_CMS
:
1696 emit_mov(mrf
, mcs_data
);
1698 case INTEL_MSAA_LAYOUT_IMS
:
1699 /* When sampling from an IMS surface, MCS data is not relevant,
1700 * and the hardware ignores it. So don't bother populating it.
1704 /* We shouldn't be trying to send MCS data with any other
1707 assert (!"Unsupported layout for MCS data");
1711 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1712 emit_mov(mrf
, brw_imm_ud(0));
1718 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1721 mrf
.nr
- base_mrf
/* msg_length */);
1729 #undef SWAP_XY_AND_XPYP
1732 brw_blorp_blit_program::render_target_write()
1734 struct brw_reg mrf_rt_write
=
1735 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1738 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1739 * so that the render target knows which pixels we killed.
1741 bool use_header
= key
->use_kill
;
1743 /* Copy R0/1 to MRF */
1744 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1745 retype(R0
, BRW_REGISTER_TYPE_UD
));
1749 /* Copy texture data to MRFs */
1750 for (int i
= 0; i
< 4; ++i
) {
1751 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1752 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1753 offset(vec8(texture_data
[0]), 2*i
));
1757 /* Now write to the render target and terminate the thread */
1758 emit_render_target_write(
1761 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1767 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1768 GLfloat dst0
, GLfloat dst1
,
1771 float scale
= (src1
- src0
) / (dst1
- dst0
);
1773 /* When not mirroring a coordinate (say, X), we need:
1774 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1776 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1778 * blorp program uses "round toward zero" to convert the
1779 * transformed floating point coordinates to integer coordinates,
1780 * whereas the behaviour we actually want is "round to nearest",
1781 * so 0.5 provides the necessary correction.
1784 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1786 /* When mirroring X we need:
1787 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1789 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1791 multiplier
= -scale
;
1792 offset
= src0
+ (dst1
- 0.5) * scale
;
1798 * Determine which MSAA layout the GPU pipeline should be configured for,
1799 * based on the chip generation, the number of samples, and the true layout of
1800 * the image in memory.
1802 inline intel_msaa_layout
1803 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1804 intel_msaa_layout true_layout
)
1806 if (num_samples
<= 1) {
1807 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1808 * format buffers, by transforming coordinates appropriately.
1810 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1811 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1812 return INTEL_MSAA_LAYOUT_NONE
;
1814 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1817 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1818 if (brw
->gen
== 6) {
1819 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1826 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1827 struct intel_mipmap_tree
*src_mt
,
1828 unsigned src_level
, unsigned src_layer
,
1829 struct intel_mipmap_tree
*dst_mt
,
1830 unsigned dst_level
, unsigned dst_layer
,
1831 GLfloat src_x0
, GLfloat src_y0
,
1832 GLfloat src_x1
, GLfloat src_y1
,
1833 GLfloat dst_x0
, GLfloat dst_y0
,
1834 GLfloat dst_x1
, GLfloat dst_y1
,
1836 bool mirror_x
, bool mirror_y
)
1838 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
1839 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
1841 /* Even though we do multisample resolves at the time of the blit, OpenGL
1842 * specification defines them as if they happen at the time of rendering,
1843 * which means that the type of averaging we do during the resolve should
1844 * only depend on the source format; the destination format should be
1845 * ignored. But, specification doesn't seem to be strict about it.
1847 * It has been observed that mulitisample resolves produce slightly better
1848 * looking images when averaging is done using destination format. NVIDIA's
1849 * proprietary OpenGL driver also follow this approach. So, we choose to
1850 * follow it in our driver.
1852 * When multisampling, if the source and destination formats are equal
1853 * (aside from the color space), we choose to blit in sRGB space to get
1854 * this higher quality image.
1856 if (src
.num_samples
> 1 &&
1857 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1858 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1859 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1860 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1861 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1864 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1865 * texture, the above code configures the source format for L32_FLOAT or
1866 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1867 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1868 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1869 * around the problem by using a source format of R32_FLOAT. This
1870 * shouldn't affect rendering correctness, since the destination format is
1871 * R32_FLOAT, so only the contents of the red channel matters.
1873 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1874 src_mt
->format
== dst_mt
->format
&&
1875 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1876 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1880 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1882 /* texture_data_type indicates the register type that should be used to
1883 * manipulate texture data.
1885 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1886 case GL_UNSIGNED_NORMALIZED
:
1887 case GL_SIGNED_NORMALIZED
:
1889 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1891 case GL_UNSIGNED_INT
:
1892 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1893 /* We process stencil as though it's an unsigned normalized color */
1894 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1896 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1900 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1903 unreachable("Unrecognized blorp format");
1907 /* Gen7's rendering hardware only supports the IMS layout for depth and
1908 * stencil render targets. Blorp always maps its destination surface as
1909 * a color render target (even if it's actually a depth or stencil
1910 * buffer). So if the destination is IMS, we'll have to map it as a
1911 * single-sampled texture and interleave the samples ourselves.
1913 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1914 dst
.num_samples
= 0;
1917 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1918 /* If the destination surface is a W-tiled multisampled stencil buffer
1919 * that we're mapping as Y tiled, then we need to arrange for the WM
1920 * program to run once per sample rather than once per pixel, because
1921 * the memory layout of related samples doesn't match between W and Y
1924 wm_prog_key
.persample_msaa_dispatch
= true;
1927 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1928 /* We are blitting from a multisample buffer to a multisample buffer, so
1929 * we must preserve samples within a pixel. This means we have to
1930 * arrange for the WM program to run once per sample rather than once
1933 wm_prog_key
.persample_msaa_dispatch
= true;
1936 /* Scaled blitting or not. */
1937 wm_prog_key
.blit_scaled
=
1938 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
1939 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
1941 /* Scaling factors used for bilinear filtering in multisample scaled
1944 wm_prog_key
.x_scale
= 2.0;
1945 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
1947 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
1948 wm_prog_key
.bilinear_filter
= true;
1950 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1951 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1952 base_format
!= GL_STENCIL_INDEX
&&
1953 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1954 /* We are downsampling a color buffer, so blend. */
1955 wm_prog_key
.blend
= true;
1958 /* src_samples and dst_samples are the true sample counts */
1959 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1960 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1962 /* tex_samples and rt_samples are the sample counts that are set up in
1965 wm_prog_key
.tex_samples
= src
.num_samples
;
1966 wm_prog_key
.rt_samples
= dst
.num_samples
;
1968 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1969 * use to access the source and destination surfaces.
1971 wm_prog_key
.tex_layout
=
1972 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1973 wm_prog_key
.rt_layout
=
1974 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1976 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1979 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1980 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1982 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1983 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1984 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1985 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1986 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1987 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1988 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
1989 wm_prog_key
.x_scale
- 1.0);
1990 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
1991 wm_prog_key
.y_scale
- 1.0);
1993 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
1994 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
1996 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
1997 /* We must expand the rectangle we send through the rendering pipeline,
1998 * to account for the fact that we are mapping the destination region as
1999 * single-sampled when it is in fact multisampled. We must also align
2000 * it to a multiple of the multisampling pattern, because the
2001 * differences between multisampled and single-sampled surface formats
2002 * will mean that pixels are scrambled within the multisampling pattern.
2003 * TODO: what if this makes the coordinates too large?
2005 * Note: this only works if the destination surface uses the IMS layout.
2006 * If it's UMS, then we have no choice but to set up the rendering
2007 * pipeline as multisampled.
2009 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2010 switch (dst_mt
->num_samples
) {
2012 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2013 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2014 x1
= ALIGN(x1
* 2, 4);
2015 y1
= ALIGN(y1
* 2, 4);
2018 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2019 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2020 x1
= ALIGN(x1
* 4, 8);
2021 y1
= ALIGN(y1
* 2, 4);
2024 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2026 wm_prog_key
.use_kill
= true;
2029 if (dst
.map_stencil_as_y_tiled
) {
2030 /* We must modify the rectangle we send through the rendering pipeline
2031 * (and the size and x/y offset of the destination surface), to account
2032 * for the fact that we are mapping it as Y-tiled when it is in fact
2035 * Both Y tiling and W tiling can be understood as organizations of
2036 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2037 * is different, but the layout of the 32-byte sub-tiles within the 4k
2038 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2039 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2040 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2042 * Therefore, to account for the layout differences within the 32-byte
2043 * sub-tiles, we must expand the rectangle so the X coordinates of its
2044 * edges are multiples of 8 (the W sub-tile width), and its Y
2045 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2046 * Then we need to scale the X and Y coordinates of the rectangle to
2047 * account for the differences in aspect ratio between the Y and W
2048 * sub-tiles. We need to modify the layer width and height similarly.
2050 * A correction needs to be applied when MSAA is in use: since
2051 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2052 * we need to align the Y coordinates to multiples of 8, so that when
2053 * they are divided by two they are still multiples of 4.
2055 * Note: Since the x/y offset of the surface will be applied using the
2056 * SURFACE_STATE command packet, it will be invisible to the swizzling
2057 * code in the shader; therefore it needs to be in a multiple of the
2058 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2059 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2060 * buffer), and the miplevel alignment used for stencil buffers is 8
2061 * pixels horizontally and either 4 or 8 pixels vertically (see
2062 * intel_horizontal_texture_alignment_unit() and
2063 * intel_vertical_texture_alignment_unit()).
2065 * Note: Also, since the SURFACE_STATE command packet can only apply
2066 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2067 * vertically, it is important that the offsets will be multiples of
2068 * these sizes after they are converted into Y-tiled coordinates.
2069 * Fortunately they will be, since we know from above that the offsets
2070 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2071 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2073 * TODO: what if this makes the coordinates (or the texture size) too
2076 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2077 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2078 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2079 x1
= ALIGN(x1
, x_align
) * 2;
2080 y1
= ALIGN(y1
, y_align
) / 2;
2081 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2082 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2085 wm_prog_key
.use_kill
= true;
2088 if (src
.map_stencil_as_y_tiled
) {
2089 /* We must modify the size and x/y offset of the source surface to
2090 * account for the fact that we are mapping it as Y-tiled when it is in
2093 * See the comments above concerning x/y offset alignment for the
2094 * destination surface.
2096 * TODO: what if this makes the texture size too large?
2098 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2099 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2100 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2107 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2108 brw_blorp_prog_data
**prog_data
) const
2110 uint32_t prog_offset
= 0;
2111 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2112 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2113 &prog_offset
, prog_data
)) {
2114 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
,
2115 INTEL_DEBUG
& DEBUG_BLORP
);
2116 GLuint program_size
;
2117 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2118 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2119 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2120 program
, program_size
,
2121 &prog
.prog_data
, sizeof(prog
.prog_data
),
2122 &prog_offset
, prog_data
);