2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/fbobject.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
48 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
50 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
51 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
56 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
57 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
58 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
59 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
60 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
61 GLenum filter
, bool mirror_x
, bool mirror_y
)
63 /* Find source/dst miptrees */
64 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
65 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
67 const bool es3
= _mesa_is_gles3(&brw
->ctx
);
69 brw_blorp_blit_miptrees(brw
,
70 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
71 src_format
, blorp_get_texture_swizzle(src_irb
),
72 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
74 srcX0
, srcY0
, srcX1
, srcY1
,
75 dstX0
, dstY0
, dstX1
, dstY1
,
76 filter
, mirror_x
, mirror_y
,
79 dst_irb
->need_downsample
= true;
83 try_blorp_blit(struct brw_context
*brw
,
84 const struct gl_framebuffer
*read_fb
,
85 const struct gl_framebuffer
*draw_fb
,
86 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
87 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
88 GLenum filter
, GLbitfield buffer_bit
)
90 struct gl_context
*ctx
= &brw
->ctx
;
92 /* Sync up the state of window system buffers. We need to do this before
93 * we go looking for the buffers.
95 intel_prepare_render(brw
);
97 bool mirror_x
, mirror_y
;
98 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
99 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
100 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
101 &mirror_x
, &mirror_y
))
105 struct intel_renderbuffer
*src_irb
;
106 struct intel_renderbuffer
*dst_irb
;
107 struct intel_mipmap_tree
*src_mt
;
108 struct intel_mipmap_tree
*dst_mt
;
109 switch (buffer_bit
) {
110 case GL_COLOR_BUFFER_BIT
:
111 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
112 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
113 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
115 do_blorp_blit(brw
, buffer_bit
,
116 src_irb
, src_irb
->Base
.Base
.Format
,
117 dst_irb
, dst_irb
->Base
.Base
.Format
,
118 srcX0
, srcY0
, srcX1
, srcY1
,
119 dstX0
, dstY0
, dstX1
, dstY1
,
120 filter
, mirror_x
, mirror_y
);
123 case GL_DEPTH_BUFFER_BIT
:
125 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
127 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
128 src_mt
= find_miptree(buffer_bit
, src_irb
);
129 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
131 /* We can't handle format conversions between Z24 and other formats
132 * since we have to lie about the surface format. See the comments in
133 * brw_blorp_surface_info::set().
135 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
136 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
139 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
140 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
141 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
142 filter
, mirror_x
, mirror_y
);
144 case GL_STENCIL_BUFFER_BIT
:
146 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
148 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
149 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
150 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
151 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
152 filter
, mirror_x
, mirror_y
);
155 unreachable("not reached");
162 brw_blorp_copytexsubimage(struct brw_context
*brw
,
163 struct gl_renderbuffer
*src_rb
,
164 struct gl_texture_image
*dst_image
,
166 int srcX0
, int srcY0
,
167 int dstX0
, int dstY0
,
168 int width
, int height
)
170 struct gl_context
*ctx
= &brw
->ctx
;
171 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
172 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
174 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
175 if (brw
->ctx
._ImageTransferState
)
178 /* Sync up the state of window system buffers. We need to do this before
179 * we go looking at the src renderbuffer's miptree.
181 intel_prepare_render(brw
);
183 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
184 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
186 /* There is support for only up to eight samples. */
187 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
190 /* BLORP is only supported from Gen6 onwards. */
194 if (_mesa_get_format_base_format(src_rb
->Format
) !=
195 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
199 /* We can't handle format conversions between Z24 and other formats since
200 * we have to lie about the surface format. See the comments in
201 * brw_blorp_surface_info::set().
203 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
204 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
208 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
211 /* Source clipping shouldn't be necessary, since copytexsubimage (in
212 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
215 * Destination clipping shouldn't be necessary since the restrictions on
216 * glCopyTexSubImage prevent the user from specifying a destination rectangle
217 * that falls outside the bounds of the destination texture.
218 * See error_check_subtexture_dimensions().
221 int srcY1
= srcY0
+ height
;
222 int srcX1
= srcX0
+ width
;
223 int dstX1
= dstX0
+ width
;
224 int dstY1
= dstY0
+ height
;
226 /* Account for the fact that in the system framebuffer, the origin is at
229 bool mirror_y
= false;
230 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
231 GLint tmp
= src_rb
->Height
- srcY0
;
232 srcY0
= src_rb
->Height
- srcY1
;
237 /* Account for face selection and texture view MinLayer */
238 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
239 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
241 brw_blorp_blit_miptrees(brw
,
242 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
243 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
244 dst_mt
, dst_level
, dst_slice
,
245 dst_image
->TexFormat
,
246 srcX0
, srcY0
, srcX1
, srcY1
,
247 dstX0
, dstY0
, dstX1
, dstY1
,
248 GL_NEAREST
, false, mirror_y
,
251 /* If we're copying to a packed depth stencil texture and the source
252 * framebuffer has separate stencil, we need to also copy the stencil data
255 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
256 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
258 src_irb
= intel_renderbuffer(src_rb
);
259 src_mt
= src_irb
->mt
;
261 if (src_mt
->stencil_mt
)
262 src_mt
= src_mt
->stencil_mt
;
263 if (dst_mt
->stencil_mt
)
264 dst_mt
= dst_mt
->stencil_mt
;
266 if (src_mt
!= dst_mt
) {
267 brw_blorp_blit_miptrees(brw
,
268 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
270 blorp_get_texture_swizzle(src_irb
),
271 dst_mt
, dst_level
, dst_slice
,
273 srcX0
, srcY0
, srcX1
, srcY1
,
274 dstX0
, dstY0
, dstX1
, dstY1
,
275 GL_NEAREST
, false, mirror_y
,
285 brw_blorp_framebuffer(struct brw_context
*brw
,
286 struct gl_framebuffer
*readFb
,
287 struct gl_framebuffer
*drawFb
,
288 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
289 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
290 GLbitfield mask
, GLenum filter
)
292 /* BLORP is not supported before Gen6. */
296 /* There is support for only up to eight samples. */
297 if (readFb
->Visual
.samples
> 8 || drawFb
->Visual
.samples
> 8)
300 static GLbitfield buffer_bits
[] = {
303 GL_STENCIL_BUFFER_BIT
,
306 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
307 if ((mask
& buffer_bits
[i
]) &&
308 try_blorp_blit(brw
, readFb
, drawFb
,
309 srcX0
, srcY0
, srcX1
, srcY1
,
310 dstX0
, dstY0
, dstX1
, dstY1
,
311 filter
, buffer_bits
[i
])) {
312 mask
&= ~buffer_bits
[i
];
321 * Enum to specify the order of arguments in a sampler message
323 enum sampler_message_arg
325 SAMPLER_MESSAGE_ARG_U_FLOAT
,
326 SAMPLER_MESSAGE_ARG_V_FLOAT
,
327 SAMPLER_MESSAGE_ARG_U_INT
,
328 SAMPLER_MESSAGE_ARG_V_INT
,
329 SAMPLER_MESSAGE_ARG_R_INT
,
330 SAMPLER_MESSAGE_ARG_SI_INT
,
331 SAMPLER_MESSAGE_ARG_MCS_INT
,
332 SAMPLER_MESSAGE_ARG_ZERO_INT
,
336 * Generator for WM programs used in BLORP blits.
338 * The bulk of the work done by the WM program is to wrap and unwrap the
339 * coordinate transformations used by the hardware to store surfaces in
340 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
341 * sample index for a multisampled surface) to a memory offset by the
342 * following formulas:
344 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
345 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
347 * For a single-sampled surface, or for a multisampled surface using
348 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
351 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
352 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
353 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
354 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
356 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
357 * embeds the sample number into bit 1 of the X and Y coordinates:
359 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
360 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
361 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
362 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
363 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
364 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
365 * S = (Y & 0b10) | (X & 0b10) >> 1
367 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
368 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
371 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
372 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
373 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
374 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
375 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
376 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
377 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
379 * For X tiling, tile() combines together the low-order bits of the X and Y
380 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
381 * bytes wide and 8 rows high:
383 * tile(x_tiled, X, Y, S) = A
384 * where A = tile_num << 12 | offset
385 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
386 * offset = (Y' & 0b111) << 9
387 * | (X & 0b111111111)
389 * Y' = Y + S * qpitch
390 * detile(x_tiled, A) = (X, Y, S)
394 * Y' = (tile_num / tile_pitch) << 3
395 * | (A & 0b111000000000) >> 9
396 * X' = (tile_num % tile_pitch) << 9
397 * | (A & 0b111111111)
399 * (In all tiling formulas, cpp is the number of bytes occupied by a single
400 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
401 * to fill the width of the surface, and qpitch is the spacing (in rows)
402 * between array slices).
404 * For Y tiling, tile() combines together the low-order bits of the X and Y
405 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
406 * bytes wide and 32 rows high:
408 * tile(y_tiled, X, Y, S) = A
409 * where A = tile_num << 12 | offset
410 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
411 * offset = (X' & 0b1110000) << 5
412 * | (Y' & 0b11111) << 4
415 * Y' = Y + S * qpitch
416 * detile(y_tiled, A) = (X, Y, S)
420 * Y' = (tile_num / tile_pitch) << 5
421 * | (A & 0b111110000) >> 4
422 * X' = (tile_num % tile_pitch) << 7
423 * | (A & 0b111000000000) >> 5
426 * For W tiling, tile() combines together the low-order bits of the X and Y
427 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
428 * bytes wide and 64 rows high (note that W tiling is only used for stencil
429 * buffers, which always have cpp = 1 and S=0):
431 * tile(w_tiled, X, Y, S) = A
432 * where A = tile_num << 12 | offset
433 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
434 * offset = (X' & 0b111000) << 6
435 * | (Y' & 0b111100) << 3
436 * | (X' & 0b100) << 2
442 * Y' = Y + S * qpitch
443 * detile(w_tiled, A) = (X, Y, S)
444 * where X = X' / cpp = X'
445 * Y = Y' % qpitch = Y'
447 * Y' = (tile_num / tile_pitch) << 6
448 * | (A & 0b111100000) >> 3
449 * | (A & 0b1000) >> 2
451 * X' = (tile_num % tile_pitch) << 6
452 * | (A & 0b111000000000) >> 6
453 * | (A & 0b10000) >> 2
457 * Finally, for a non-tiled surface, tile() simply combines together the X and
458 * Y coordinates in the natural way:
460 * tile(untiled, X, Y, S) = A
461 * where A = Y * pitch + X'
463 * Y' = Y + S * qpitch
464 * detile(untiled, A) = (X, Y, S)
471 * (In these formulas, pitch is the number of bytes occupied by a single row
474 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
477 brw_blorp_blit_program(struct brw_context
*brw
,
478 const brw_blorp_blit_prog_key
*key
);
480 const GLuint
*compile(struct brw_context
*brw
, bool debug_flag
,
481 GLuint
*program_size
);
483 brw_blorp_prog_data prog_data
;
487 void alloc_push_const_regs(int base_reg
);
488 void compute_frag_coords();
489 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
490 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
491 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
492 void translate_dst_to_src();
493 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
494 struct brw_reg clampX0
, struct brw_reg clampY0
,
495 struct brw_reg clampX1
, struct brw_reg clampY1
);
496 void single_to_blend();
497 void manual_blend_average(unsigned num_samples
);
498 void manual_blend_bilinear(unsigned num_samples
);
499 void sample(struct brw_reg dst
);
500 void texel_fetch(struct brw_reg dst
);
502 void texture_lookup(struct brw_reg dst
, enum opcode op
,
503 const sampler_message_arg
*args
, int num_args
);
504 void render_target_write();
507 * Base-2 logarithm of the maximum number of samples that can be blended.
509 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
511 struct brw_context
*brw
;
512 const brw_blorp_blit_prog_key
*key
;
514 /* Thread dispatch header */
517 /* Pixel X/Y coordinates (always in R1). */
521 struct brw_reg dst_x0
;
522 struct brw_reg dst_x1
;
523 struct brw_reg dst_y0
;
524 struct brw_reg dst_y1
;
525 /* Top right coordinates of the rectangular grid used for scaled blitting */
526 struct brw_reg rect_grid_x1
;
527 struct brw_reg rect_grid_y1
;
529 struct brw_reg multiplier
;
530 struct brw_reg offset
;
531 } x_transform
, y_transform
;
532 struct brw_reg src_z
;
534 /* Data read from texture (4 vec16's per array element) */
535 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
537 /* Auxiliary storage for the contents of the MCS surface.
539 * Since the sampler always returns 8 registers worth of data, this is 8
540 * registers wide, even though we only use the first 2 registers of it.
542 struct brw_reg mcs_data
;
544 /* X coordinates. We have two of them so that we can perform coordinate
545 * transformations easily.
547 struct brw_reg x_coords
[2];
549 /* Y coordinates. We have two of them so that we can perform coordinate
550 * transformations easily.
552 struct brw_reg y_coords
[2];
554 /* X, Y coordinates of the pixel from which we need to fetch the specific
555 * sample. These are used for multisample scaled blitting.
557 struct brw_reg x_sample_coords
;
558 struct brw_reg y_sample_coords
;
560 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
561 struct brw_reg x_frac
;
562 struct brw_reg y_frac
;
564 /* Which element of x_coords and y_coords is currently in use.
568 /* True if, at the point in the program currently being compiled, the
569 * sample index is known to be zero.
573 /* Register storing the sample index when s_is_zero is false. */
574 struct brw_reg sample_index
;
580 /* MRF used for sampling and render target writes */
584 brw_blorp_blit_program::brw_blorp_blit_program(
585 struct brw_context
*brw
, const brw_blorp_blit_prog_key
*key
)
586 : brw_blorp_eu_emitter(), brw(brw
), key(key
)
591 brw_blorp_blit_program::compile(struct brw_context
*brw
, bool debug_flag
,
592 GLuint
*program_size
)
595 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
596 /* If the destination image is W tiled and multisampled, then the thread
597 * must be dispatched once per sample, not once per pixel. This is
598 * necessary because after conversion between W and Y tiling, there's no
599 * guarantee that all samples corresponding to a single pixel will still
602 assert(key
->persample_msaa_dispatch
);
606 /* We are blending, which means we won't have an opportunity to
607 * translate the tiling and sample count for the texture surface. So
608 * the surface state for the texture must be configured with the correct
609 * tiling and sample count.
611 assert(!key
->src_tiled_w
);
612 assert(key
->tex_samples
== key
->src_samples
);
613 assert(key
->tex_layout
== key
->src_layout
);
614 assert(key
->tex_samples
> 0);
617 if (key
->persample_msaa_dispatch
) {
618 /* It only makes sense to do persample dispatch if the render target is
619 * configured as multisampled.
621 assert(key
->rt_samples
> 0);
624 /* Make sure layout is consistent with sample count */
625 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
626 (key
->tex_samples
== 0));
627 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
628 (key
->rt_samples
== 0));
629 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
630 (key
->src_samples
== 0));
631 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
632 (key
->dst_samples
== 0));
634 /* Set up prog_data */
635 memset(&prog_data
, 0, sizeof(prog_data
));
636 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
639 compute_frag_coords();
641 /* Render target and texture hardware don't support W tiling until Gen8. */
642 const bool rt_tiled_w
= false;
643 const bool tex_tiled_w
= brw
->gen
>= 8 && key
->src_tiled_w
;
645 /* The address that data will be written to is determined by the
646 * coordinates supplied to the WM thread and the tiling and sample count of
647 * the render target, according to the formula:
649 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
651 * If the actual tiling and sample count of the destination surface are not
652 * the same as the configuration of the render target, then these
653 * coordinates are wrong and we have to adjust them to compensate for the
656 if (rt_tiled_w
!= key
->dst_tiled_w
||
657 key
->rt_samples
!= key
->dst_samples
||
658 key
->rt_layout
!= key
->dst_layout
) {
659 encode_msaa(key
->rt_samples
, key
->rt_layout
);
660 /* Now (X, Y, S) = detile(rt_tiling, offset) */
661 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
662 /* Now (X, Y, S) = detile(dst_tiling, offset) */
663 decode_msaa(key
->dst_samples
, key
->dst_layout
);
666 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
668 * That is: X, Y and S now contain the true coordinates and sample index of
669 * the data that the WM thread should output.
671 * If we need to kill pixels that are outside the destination rectangle,
672 * now is the time to do it.
676 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
677 y_coords
[xy_coord_index
],
678 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
680 /* Next, apply a translation to obtain coordinates in the source image. */
681 translate_dst_to_src();
683 /* If the source image is not multisampled, then we want to fetch sample
684 * number 0, because that's the only sample there is.
686 if (key
->src_samples
== 0)
689 /* X, Y, and S are now the coordinates of the pixel in the source image
690 * that we want to texture from. Exception: if we are blending, then S is
691 * irrelevant, because we are going to fetch all samples.
693 if (key
->blend
&& !key
->blit_scaled
) {
695 /* Gen6 hardware an automatically blend using the SAMPLE message */
697 sample(texture_data
[0]);
699 /* Gen7+ hardware doesn't automaticaly blend. */
700 manual_blend_average(key
->src_samples
);
702 } else if(key
->blend
&& key
->blit_scaled
) {
703 manual_blend_bilinear(key
->src_samples
);
705 /* We aren't blending, which means we just want to fetch a single sample
706 * from the source surface. The address that we want to fetch from is
707 * related to the X, Y and S values according to the formula:
709 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
711 * If the actual tiling and sample count of the source surface are not
712 * the same as the configuration of the texture, then we need to adjust
713 * the coordinates to compensate for the difference.
715 if ((tex_tiled_w
!= key
->src_tiled_w
||
716 key
->tex_samples
!= key
->src_samples
||
717 key
->tex_layout
!= key
->src_layout
) &&
718 !key
->bilinear_filter
) {
719 encode_msaa(key
->src_samples
, key
->src_layout
);
720 /* Now (X, Y, S) = detile(src_tiling, offset) */
721 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
722 /* Now (X, Y, S) = detile(tex_tiling, offset) */
723 decode_msaa(key
->tex_samples
, key
->tex_layout
);
726 if (key
->bilinear_filter
) {
727 sample(texture_data
[0]);
730 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
732 * In other words: X, Y, and S now contain values which, when passed to
733 * the texturing unit, will cause data to be read from the correct
734 * memory location. So we can fetch the texel now.
736 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
738 texel_fetch(texture_data
[0]);
742 /* Finally, write the fetched (or blended) value to the render target and
743 * terminate the thread.
745 render_target_write();
747 return get_program(brw
, debug_flag
, program_size
);
751 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
753 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
754 #define ALLOC_REG(name, type) \
756 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
757 base_reg + CONST_LOC(name) / 32, \
758 (CONST_LOC(name) % 32) / 4), type)
760 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
761 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
762 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
763 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
764 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
765 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
766 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
767 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
768 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
769 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
770 ALLOC_REG(src_z
, BRW_REGISTER_TYPE_UD
);
776 brw_blorp_blit_program::alloc_regs()
779 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
780 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
781 prog_data
.first_curbe_grf
= reg
;
782 alloc_push_const_regs(reg
);
783 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
784 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
785 this->texture_data
[i
] =
786 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
790 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
792 for (int i
= 0; i
< 2; ++i
) {
794 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
797 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
801 if (key
->blit_scaled
&& key
->blend
) {
802 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
804 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
806 this->x_frac
= brw_vec8_grf(reg
, 0);
808 this->y_frac
= brw_vec8_grf(reg
, 0);
812 this->xy_coord_index
= 0;
814 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
816 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
818 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
821 /* Make sure we didn't run out of registers */
822 assert(reg
<= GEN7_MRF_HACK_START
);
825 this->base_mrf
= mrf
;
828 /* In the code that follows, X and Y can be used to quickly refer to the
829 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
830 * prime") to the inactive elements.
832 * S can be used to quickly refer to sample_index.
834 #define X x_coords[xy_coord_index]
835 #define Y y_coords[xy_coord_index]
836 #define Xp x_coords[!xy_coord_index]
837 #define Yp y_coords[!xy_coord_index]
838 #define S sample_index
840 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
841 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
843 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
846 * Emit code to compute the X and Y coordinates of the pixels being rendered
847 * by this WM invocation.
849 * Assuming the render target is set up for Y tiling, these (X, Y) values are
850 * related to the address offset where outputs will be written by the formula:
852 * (X, Y, S) = decode_msaa(detile(offset)).
854 * (See brw_blorp_blit_program).
857 brw_blorp_blit_program::compute_frag_coords()
859 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
860 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
861 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
862 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
864 * Pixels within a subspan are laid out in this arrangement:
868 * So, to compute the coordinates of each pixel, we need to read every 2nd
869 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
870 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
871 * In other words, the data we want to access is R1.4<2;4,0>UW.
873 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
874 * result, since pixels n+1 and n+3 are in the right half of the subspan.
876 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
877 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
879 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
880 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
881 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
884 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
885 * pixels n+2 and n+3 are in the bottom half of the subspan.
887 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
888 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
890 /* Move the coordinates to UD registers. */
891 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
892 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
895 if (key
->persample_msaa_dispatch
) {
896 switch (key
->rt_samples
) {
899 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
900 * Therefore, subspan 0 will represent sample 0, subspan 1 will
901 * represent sample 1, and so on.
903 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
904 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
905 * populate a temporary variable with the sequence (0, 1, 2, 3), and
906 * then copy from it using vstride=1, width=4, hstride=0.
908 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
909 emit_mov(vec16(t1_uw1
), key
->rt_samples
== 4 ?
910 brw_imm_v(0x3210) : brw_imm_v(0x1010));
911 /* Move to UD sample_index register. */
912 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
913 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
917 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
918 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
919 * subspan 1 will represent sample 1, and so on. We can find the
920 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
921 * Index") and multiplying by two (since samples are always delivered
922 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
925 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
926 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
927 * variable with the sequence (0, 1, 2, 3), and then reading from it
928 * using vstride=1, width=4, hstride=0.
930 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
931 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
932 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
933 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
934 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
935 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
936 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
937 stride(t2_uw1
, 1, 4, 0));
938 emit_add_8(offset(S
, 1),
939 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
940 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
944 unreachable("Unrecognized sample count in "
945 "brw_blorp_blit_program::compute_frag_coords()");
949 /* Either the destination surface is single-sampled, or the WM will be
950 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
951 * per pixel). In either case, it's not meaningful to compute a sample
952 * value. Just set it to 0.
959 * Emit code to compensate for the difference between Y and W tiling.
961 * This code modifies the X and Y coordinates according to the formula:
963 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
965 * (See brw_blorp_blit_program).
967 * It can only translate between W and Y tiling, so new_tiling and old_tiling
968 * are booleans where true represents W tiling and false represents Y tiling.
971 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
973 if (old_tiled_w
== new_tiled_w
)
976 /* In the code that follows, we can safely assume that S = 0, because W
977 * tiling formats always use IMS layout.
982 /* Given X and Y coordinates that describe an address using Y tiling,
983 * translate to the X and Y coordinates that describe the same address
986 * If we break down the low order bits of X and Y, using a
987 * single letter to represent each low-order bit:
989 * X = A << 7 | 0bBCDEFGH
990 * Y = J << 5 | 0bKLMNP (1)
992 * Then we can apply the Y tiling formula to see the memory offset being
995 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
997 * If we apply the W detiling formula to this memory location, that the
998 * corresponding X' and Y' coordinates are:
1000 * X' = A << 6 | 0bBCDPFH (3)
1001 * Y' = J << 6 | 0bKLMNEG
1003 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1004 * we need to make the following computation:
1006 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1007 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1009 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1010 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1011 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1012 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1013 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1014 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1015 emit_or(Xp
, t1
, t2
);
1016 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1017 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1018 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1019 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1020 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1021 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1022 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1023 emit_or(Yp
, t1
, t2
);
1026 /* Applying the same logic as above, but in reverse, we obtain the
1029 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1030 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1032 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1033 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1034 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1035 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1036 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1037 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1038 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1039 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1041 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1042 emit_or(Xp
, t1
, t2
);
1043 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1044 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1045 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1046 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1047 emit_or(Yp
, t1
, t2
);
1053 * Emit code to compensate for the difference between MSAA and non-MSAA
1056 * This code modifies the X and Y coordinates according to the formula:
1058 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1060 * (See brw_blorp_blit_program).
1063 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1064 intel_msaa_layout layout
)
1067 case INTEL_MSAA_LAYOUT_NONE
:
1068 /* No translation necessary, and S should already be zero. */
1071 case INTEL_MSAA_LAYOUT_CMS
:
1072 /* We can't compensate for compressed layout since at this point in the
1073 * program we haven't read from the MCS buffer.
1075 unreachable("Bad layout in encode_msaa");
1076 case INTEL_MSAA_LAYOUT_UMS
:
1077 /* No translation necessary. */
1079 case INTEL_MSAA_LAYOUT_IMS
:
1080 switch (num_samples
) {
1082 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
1083 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1087 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1088 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1089 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1091 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1093 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1094 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1096 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1098 if (num_samples
== 2) {
1103 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1104 emit_or(Xp
, t1
, t2
);
1105 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1106 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1108 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1109 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1111 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1112 emit_or(Yp
, t1
, t2
);
1115 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1116 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1118 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1120 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1121 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1123 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1124 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1125 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1126 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1127 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1130 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1131 emit_or(Xp
, t1
, t2
);
1132 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1133 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1135 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1136 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1138 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1139 emit_or(Yp
, t1
, t2
);
1149 * Emit code to compensate for the difference between MSAA and non-MSAA
1152 * This code modifies the X and Y coordinates according to the formula:
1154 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1156 * (See brw_blorp_blit_program).
1159 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1160 intel_msaa_layout layout
)
1163 case INTEL_MSAA_LAYOUT_NONE
:
1164 /* No translation necessary, and S should already be zero. */
1167 case INTEL_MSAA_LAYOUT_CMS
:
1168 /* We can't compensate for compressed layout since at this point in the
1169 * program we don't have access to the MCS buffer.
1171 unreachable("Bad layout in encode_msaa");
1172 case INTEL_MSAA_LAYOUT_UMS
:
1173 /* No translation necessary. */
1175 case INTEL_MSAA_LAYOUT_IMS
:
1177 switch (num_samples
) {
1179 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
1180 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1181 * S = (X & 0b10) >> 1
1184 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1185 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1186 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1187 * S = (Y & 0b10) | (X & 0b10) >> 1
1189 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1190 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1191 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1192 emit_or(Xp
, t1
, t2
);
1194 if (num_samples
== 2) {
1196 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1197 emit_shr(S
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1199 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1200 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1201 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1202 emit_or(Yp
, t1
, t2
);
1203 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1204 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1205 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1210 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1211 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1212 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1213 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1215 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1216 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1217 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1218 emit_or(Xp
, t1
, t2
);
1219 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1220 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1221 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1222 emit_or(Yp
, t1
, t2
);
1223 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1224 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1225 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1226 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1227 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1238 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1242 brw_blorp_blit_program::translate_dst_to_src()
1244 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1245 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1246 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1247 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1249 /* Move the UD coordinates to float registers. */
1252 /* Scale and offset */
1253 emit_mad(X_f
, x_transform
.offset
, Xp_f
, x_transform
.multiplier
);
1254 emit_mad(Y_f
, y_transform
.offset
, Yp_f
, y_transform
.multiplier
);
1255 if (key
->blit_scaled
&& key
->blend
) {
1256 /* Translate coordinates to lay out the samples in a rectangular grid
1257 * roughly corresponding to sample locations.
1259 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1260 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1261 /* Adjust coordinates so that integers represent pixel centers rather
1264 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1265 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1267 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1268 * texels on texture edges.
1270 clamp_tex_coords(X_f
, Y_f
,
1271 brw_imm_f(0.0), brw_imm_f(0.0),
1272 rect_grid_x1
, rect_grid_y1
);
1274 /* Store the fractional parts to be used as bilinear interpolation
1277 emit_frc(x_frac
, X_f
);
1278 emit_frc(y_frac
, Y_f
);
1280 /* Round the float coordinates down to nearest integer */
1281 emit_rndd(Xp_f
, X_f
);
1282 emit_rndd(Yp_f
, Y_f
);
1283 emit_mul(X_f
, Xp_f
, brw_imm_f(1.0f
/ key
->x_scale
));
1284 emit_mul(Y_f
, Yp_f
, brw_imm_f(1.0f
/ key
->y_scale
));
1286 } else if (!key
->bilinear_filter
) {
1287 /* Round the float coordinates down to nearest integer by moving to
1297 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1298 struct brw_reg regY
,
1299 struct brw_reg clampX0
,
1300 struct brw_reg clampY0
,
1301 struct brw_reg clampX1
,
1302 struct brw_reg clampY1
)
1304 emit_max(regX
, regX
, clampX0
);
1305 emit_max(regY
, regY
, clampY0
);
1306 emit_min(regX
, regX
, clampX1
);
1307 emit_min(regY
, regY
, clampY1
);
1311 * Emit code to transform the X and Y coordinates as needed for blending
1312 * together the different samples in an MSAA texture.
1315 brw_blorp_blit_program::single_to_blend()
1317 /* When looking up samples in an MSAA texture using the SAMPLE message,
1318 * Gen6 requires the texture coordinates to be odd integers (so that they
1319 * correspond to the center of a 2x2 block representing the four samples
1320 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1321 * each by 2 and then add 1.
1323 emit_shl(t1
, X
, brw_imm_w(1));
1324 emit_shl(t2
, Y
, brw_imm_w(1));
1325 emit_add(Xp
, t1
, brw_imm_w(1));
1326 emit_add(Yp
, t2
, brw_imm_w(1));
1332 * Count the number of trailing 1 bits in the given value. For example:
1334 * count_trailing_one_bits(0) == 0
1335 * count_trailing_one_bits(7) == 3
1336 * count_trailing_one_bits(11) == 2
1338 static inline int count_trailing_one_bits(unsigned value
)
1340 #ifdef HAVE___BUILTIN_CTZ
1341 return __builtin_ctz(~value
);
1343 return _mesa_bitcount(value
& ~(value
+ 1));
1349 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1351 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1354 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1356 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1358 * This ensures that when all samples have the same value, no numerical
1359 * precision is lost, since each addition operation always adds two equal
1360 * values, and summing two equal floating point values does not lose
1363 * We perform this computation by treating the texture_data array as a
1364 * stack and performing the following operations:
1366 * - push sample 0 onto stack
1367 * - push sample 1 onto stack
1368 * - add top two stack entries
1369 * - push sample 2 onto stack
1370 * - push sample 3 onto stack
1371 * - add top two stack entries
1372 * - add top two stack entries
1373 * - divide top stack entry by 4
1375 * Note that after pushing sample i onto the stack, the number of add
1376 * operations we do is equal to the number of trailing 1 bits in i. This
1377 * works provided the total number of samples is a power of two, which it
1378 * always is for i965.
1380 * For integer formats, we replace the add operations with average
1381 * operations and skip the final division.
1383 unsigned stack_depth
= 0;
1384 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1385 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1387 /* Push sample i onto the stack */
1388 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1393 emit_mov(vec16(S
), brw_imm_ud(i
));
1395 texel_fetch(texture_data
[stack_depth
++]);
1397 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1398 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1399 * suggests an optimization:
1401 * "A simple optimization with probable large return in
1402 * performance is to compare the MCS value to zero (indicating
1403 * all samples are on sample slice 0), and sample only from
1404 * sample slice 0 using ld2dss if MCS is zero."
1406 * Note that in the case where the MCS value is zero, sampling from
1407 * sample slice 0 using ld2dss and sampling from sample 0 using
1408 * ld2dms are equivalent (since all samples are on sample slice 0).
1409 * Since we have already sampled from sample 0, all we need to do is
1410 * skip the remaining fetches and averaging if MCS is zero.
1412 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1415 /* Do count_trailing_one_bits(i) times */
1416 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1417 assert(stack_depth
>= 2);
1420 /* TODO: should use a smaller loop bound for non_RGBA formats */
1421 for (int k
= 0; k
< 4; ++k
) {
1422 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1423 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1424 offset(texture_data
[stack_depth
- 1], 2*k
),
1425 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1426 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1431 /* We should have just 1 sample on the stack now. */
1432 assert(stack_depth
== 1);
1434 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1435 /* Scale the result down by a factor of num_samples */
1436 /* TODO: should use a smaller loop bound for non-RGBA formats */
1437 for (int j
= 0; j
< 4; ++j
) {
1438 emit_mul(offset(texture_data
[0], 2*j
),
1439 offset(vec8(texture_data
[0]), 2*j
),
1440 brw_imm_f(1.0f
/ num_samples
));
1444 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1449 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1451 /* We do this computation by performing the following operations:
1453 * In case of 4x, 8x MSAA:
1454 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1455 * which are later used for interpolation
1456 * - linearly interpolate samples a and b in X
1457 * - linearly interpolate samples c and d in X
1458 * - linearly interpolate the results of last two operations in Y
1460 * result = lrp(lrp(a + b) + lrp(c + d))
1462 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1463 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1464 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1465 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1467 for (unsigned i
= 0; i
< 4; ++i
) {
1468 assert(i
< ARRAY_SIZE(texture_data
));
1471 /* Compute pixel coordinates */
1472 emit_add(vec16(x_sample_coords
), Xp_f
,
1473 brw_imm_f((float)(i
& 0x1) * (1.0f
/ key
->x_scale
)));
1474 emit_add(vec16(y_sample_coords
), Yp_f
,
1475 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0f
/ key
->y_scale
)));
1476 emit_mov(vec16(X
), x_sample_coords
);
1477 emit_mov(vec16(Y
), y_sample_coords
);
1479 /* The MCS value we fetch has to match up with the pixel that we're
1480 * sampling from. Since we sample from different pixels in each
1481 * iteration of this "for" loop, the call to mcs_fetch() should be
1482 * here inside the loop after computing the pixel coordinates.
1484 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1487 /* Compute sample index and map the sample index to a sample number.
1488 * Sample index layout shows the numbering of slots in a rectangular
1489 * grid of samples with in a pixel. Sample number layout shows the
1490 * rectangular grid of samples roughly corresponding to the real sample
1491 * locations with in a pixel.
1492 * In case of 4x MSAA, layout of sample indices matches the layout of
1500 * In case of 8x MSAA the two layouts don't match.
1501 * sample index layout : --------- sample number layout : ---------
1502 * | 0 | 1 | | 5 | 2 |
1503 * --------- ---------
1504 * | 2 | 3 | | 4 | 6 |
1505 * --------- ---------
1506 * | 4 | 5 | | 0 | 3 |
1507 * --------- ---------
1508 * | 6 | 7 | | 7 | 1 |
1509 * --------- ---------
1511 emit_frc(vec16(t1_f
), x_sample_coords
);
1512 emit_frc(vec16(t2_f
), y_sample_coords
);
1513 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1514 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1515 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1516 emit_mov(vec16(S
), t1_f
);
1518 if (num_samples
== 8) {
1519 /* Map the sample index to a sample number */
1520 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1522 emit_mov(vec16(t2
), brw_imm_d(5));
1523 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1524 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1525 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1529 emit_mov(vec16(t2
), brw_imm_d(0));
1530 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1531 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1532 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1535 emit_mov(vec16(S
), t2
);
1537 texel_fetch(texture_data
[i
]);
1540 #define SAMPLE(x, y) offset(texture_data[x], y)
1541 for (int index
= 3; index
> 0; ) {
1542 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1543 * Counter value of 8 in 'for' loop below is used to interpolate all
1544 * the color components.
1546 for (int k
= 0; k
< 8; k
+= 2)
1547 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1549 vec8(SAMPLE(index
, k
)),
1550 vec8(SAMPLE(index
- 1, k
)));
1553 for (int k
= 0; k
< 8; k
+= 2)
1554 emit_lrp(vec8(SAMPLE(0, k
)),
1557 vec8(SAMPLE(0, k
)));
1562 * Emit code to look up a value in the texture using the SAMPLE message (which
1563 * does blending of MSAA surfaces).
1566 brw_blorp_blit_program::sample(struct brw_reg dst
)
1568 static const sampler_message_arg args
[2] = {
1569 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1570 SAMPLER_MESSAGE_ARG_V_FLOAT
1573 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1577 * Emit code to look up a value in the texture using the SAMPLE_LD message
1578 * (which does a simple texel fetch).
1581 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1583 static const sampler_message_arg gen6_args
[5] = {
1584 SAMPLER_MESSAGE_ARG_U_INT
,
1585 SAMPLER_MESSAGE_ARG_V_INT
,
1586 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1587 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1588 SAMPLER_MESSAGE_ARG_SI_INT
1590 static const sampler_message_arg gen7_ld_args
[] = {
1591 SAMPLER_MESSAGE_ARG_U_INT
,
1592 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1593 SAMPLER_MESSAGE_ARG_V_INT
,
1594 SAMPLER_MESSAGE_ARG_R_INT
1596 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1597 SAMPLER_MESSAGE_ARG_SI_INT
,
1598 SAMPLER_MESSAGE_ARG_U_INT
,
1599 SAMPLER_MESSAGE_ARG_V_INT
1601 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1602 SAMPLER_MESSAGE_ARG_SI_INT
,
1603 SAMPLER_MESSAGE_ARG_MCS_INT
,
1604 SAMPLER_MESSAGE_ARG_U_INT
,
1605 SAMPLER_MESSAGE_ARG_V_INT
1607 static const sampler_message_arg gen9_ld_args
[] = {
1608 SAMPLER_MESSAGE_ARG_U_INT
,
1609 SAMPLER_MESSAGE_ARG_V_INT
,
1610 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1611 SAMPLER_MESSAGE_ARG_R_INT
1616 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1621 switch (key
->tex_layout
) {
1622 case INTEL_MSAA_LAYOUT_IMS
:
1623 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1626 * If this field is MSFMT_DEPTH_STENCIL
1627 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1628 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1630 * So fall through to emit the same message as we use for
1631 * INTEL_MSAA_LAYOUT_CMS.
1633 case INTEL_MSAA_LAYOUT_CMS
:
1634 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1635 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1637 case INTEL_MSAA_LAYOUT_UMS
:
1638 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1639 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1641 case INTEL_MSAA_LAYOUT_NONE
:
1644 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1645 ARRAY_SIZE(gen7_ld_args
));
1647 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen9_ld_args
,
1648 ARRAY_SIZE(gen9_ld_args
));
1654 unreachable("Should not get here.");
1659 brw_blorp_blit_program::mcs_fetch()
1661 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1662 SAMPLER_MESSAGE_ARG_U_INT
,
1663 SAMPLER_MESSAGE_ARG_V_INT
1665 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1666 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1670 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1672 const sampler_message_arg
*args
,
1675 struct brw_reg mrf
=
1676 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1677 for (int arg
= 0; arg
< num_args
; ++arg
) {
1678 switch (args
[arg
]) {
1679 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1680 if (key
->bilinear_filter
)
1681 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1682 retype(X
, BRW_REGISTER_TYPE_F
));
1684 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1686 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1687 if (key
->bilinear_filter
)
1688 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1689 retype(Y
, BRW_REGISTER_TYPE_F
));
1691 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1693 case SAMPLER_MESSAGE_ARG_U_INT
:
1696 case SAMPLER_MESSAGE_ARG_V_INT
:
1699 case SAMPLER_MESSAGE_ARG_R_INT
:
1700 emit_mov(mrf
, src_z
);
1702 case SAMPLER_MESSAGE_ARG_SI_INT
:
1703 /* Note: on Gen7, this code may be reached with s_is_zero==true
1704 * because in Gen7's ld2dss message, the sample index is the first
1705 * argument. When this happens, we need to move a 0 into the
1706 * appropriate message register.
1709 emit_mov(mrf
, brw_imm_ud(0));
1713 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1714 switch (key
->tex_layout
) {
1715 case INTEL_MSAA_LAYOUT_CMS
:
1716 emit_mov(mrf
, mcs_data
);
1718 case INTEL_MSAA_LAYOUT_IMS
:
1719 /* When sampling from an IMS surface, MCS data is not relevant,
1720 * and the hardware ignores it. So don't bother populating it.
1724 /* We shouldn't be trying to send MCS data with any other
1727 assert (!"Unsupported layout for MCS data");
1731 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1732 emit_mov(mrf
, brw_imm_ud(0));
1738 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1741 mrf
.nr
- base_mrf
/* msg_length */);
1749 #undef SWAP_XY_AND_XPYP
1752 brw_blorp_blit_program::render_target_write()
1754 struct brw_reg mrf_rt_write
=
1755 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1758 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1759 * so that the render target knows which pixels we killed.
1761 bool use_header
= key
->use_kill
;
1763 /* Copy R0/1 to MRF */
1764 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1765 retype(R0
, BRW_REGISTER_TYPE_UD
));
1769 /* Copy texture data to MRFs */
1770 for (int i
= 0; i
< 4; ++i
) {
1771 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1772 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1773 offset(vec8(texture_data
[0]), 2*i
));
1777 /* Now write to the render target and terminate the thread */
1778 emit_render_target_write(
1780 brw
->gen
< 8 ? base_mrf
: -1,
1781 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1787 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1788 GLfloat dst0
, GLfloat dst1
,
1791 float scale
= (src1
- src0
) / (dst1
- dst0
);
1793 /* When not mirroring a coordinate (say, X), we need:
1794 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1796 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1798 * blorp program uses "round toward zero" to convert the
1799 * transformed floating point coordinates to integer coordinates,
1800 * whereas the behaviour we actually want is "round to nearest",
1801 * so 0.5 provides the necessary correction.
1804 offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
1806 /* When mirroring X we need:
1807 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1809 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1811 multiplier
= -scale
;
1812 offset
= src0
+ (dst1
- 0.5f
) * scale
;
1818 * Determine which MSAA layout the GPU pipeline should be configured for,
1819 * based on the chip generation, the number of samples, and the true layout of
1820 * the image in memory.
1822 inline intel_msaa_layout
1823 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1824 intel_msaa_layout true_layout
)
1826 if (num_samples
<= 1) {
1827 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1828 * format buffers, by transforming coordinates appropriately.
1830 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1831 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1832 return INTEL_MSAA_LAYOUT_NONE
;
1834 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1837 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1838 if (brw
->gen
== 6) {
1839 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1847 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
1848 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
1849 * the physical layer holding sample 0. So, for example, if
1850 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
1854 brw_blorp_blit_miptrees(struct brw_context
*brw
,
1855 struct intel_mipmap_tree
*src_mt
,
1856 unsigned src_level
, unsigned src_layer
,
1857 mesa_format src_format
, int src_swizzle
,
1858 struct intel_mipmap_tree
*dst_mt
,
1859 unsigned dst_level
, unsigned dst_layer
,
1860 mesa_format dst_format
,
1861 float src_x0
, float src_y0
,
1862 float src_x1
, float src_y1
,
1863 float dst_x0
, float dst_y0
,
1864 float dst_x1
, float dst_y1
,
1865 GLenum filter
, bool mirror_x
, bool mirror_y
,
1866 bool decode_srgb
, bool encode_srgb
)
1868 /* Get ready to blit. This includes depth resolving the src and dst
1869 * buffers if necessary. Note: it's not necessary to do a color resolve on
1870 * the destination buffer because we use the standard render path to render
1871 * to destination color buffers, and the standard render path is
1873 * Lossless compression is only introduced for gen9 onwards whereas
1874 * blorp is not supported even for gen8. Therefore it should be impossible
1875 * to end up here with single sampled compressed surfaces.
1877 assert(!intel_miptree_is_lossless_compressed(brw
, src_mt
));
1878 assert(!intel_miptree_is_lossless_compressed(brw
, dst_mt
));
1879 intel_miptree_resolve_color(brw
, src_mt
, 0);
1880 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
1881 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
1883 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
1884 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
1886 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
1887 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
1888 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
1889 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
1890 mirror_x
, mirror_y
);
1892 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
1893 src_format
= _mesa_get_srgb_format_linear(src_format
);
1895 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
1896 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
1898 brw_blorp_params params
;
1900 params
.src
.set(brw
, src_mt
, src_level
, src_layer
, src_format
, false);
1901 params
.dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, dst_format
, true);
1903 /* Even though we do multisample resolves at the time of the blit, OpenGL
1904 * specification defines them as if they happen at the time of rendering,
1905 * which means that the type of averaging we do during the resolve should
1906 * only depend on the source format; the destination format should be
1907 * ignored. But, specification doesn't seem to be strict about it.
1909 * It has been observed that mulitisample resolves produce slightly better
1910 * looking images when averaging is done using destination format. NVIDIA's
1911 * proprietary OpenGL driver also follow this approach. So, we choose to
1912 * follow it in our driver.
1914 * When multisampling, if the source and destination formats are equal
1915 * (aside from the color space), we choose to blit in sRGB space to get
1916 * this higher quality image.
1918 if (params
.src
.num_samples
> 1 &&
1919 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1920 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1921 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1922 assert(brw
->format_supported_as_render_target
[dst_mt
->format
]);
1923 params
.dst
.brw_surfaceformat
= brw
->render_target_format
[dst_mt
->format
];
1924 params
.src
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1927 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1928 * texture, the above code configures the source format for L32_FLOAT or
1929 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1930 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1931 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1932 * around the problem by using a source format of R32_FLOAT. This
1933 * shouldn't affect rendering correctness, since the destination format is
1934 * R32_FLOAT, so only the contents of the red channel matters.
1936 if (brw
->gen
== 6 &&
1937 params
.src
.num_samples
> 1 && params
.dst
.num_samples
<= 1 &&
1938 src_mt
->format
== dst_mt
->format
&&
1939 params
.dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1940 params
.src
.brw_surfaceformat
= params
.dst
.brw_surfaceformat
;
1943 struct brw_blorp_blit_prog_key wm_prog_key
;
1944 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1946 /* texture_data_type indicates the register type that should be used to
1947 * manipulate texture data.
1949 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1950 case GL_UNSIGNED_NORMALIZED
:
1951 case GL_SIGNED_NORMALIZED
:
1953 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1955 case GL_UNSIGNED_INT
:
1956 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1957 /* We process stencil as though it's an unsigned normalized color */
1958 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1960 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1964 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1967 unreachable("Unrecognized blorp format");
1971 /* Gen7's rendering hardware only supports the IMS layout for depth and
1972 * stencil render targets. Blorp always maps its destination surface as
1973 * a color render target (even if it's actually a depth or stencil
1974 * buffer). So if the destination is IMS, we'll have to map it as a
1975 * single-sampled texture and interleave the samples ourselves.
1977 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1978 params
.dst
.num_samples
= 0;
1981 if (params
.dst
.map_stencil_as_y_tiled
&& params
.dst
.num_samples
> 1) {
1982 /* If the destination surface is a W-tiled multisampled stencil buffer
1983 * that we're mapping as Y tiled, then we need to arrange for the WM
1984 * program to run once per sample rather than once per pixel, because
1985 * the memory layout of related samples doesn't match between W and Y
1988 wm_prog_key
.persample_msaa_dispatch
= true;
1991 if (params
.src
.num_samples
> 0 && params
.dst
.num_samples
> 1) {
1992 /* We are blitting from a multisample buffer to a multisample buffer, so
1993 * we must preserve samples within a pixel. This means we have to
1994 * arrange for the WM program to run once per sample rather than once
1997 wm_prog_key
.persample_msaa_dispatch
= true;
2000 /* Scaled blitting or not. */
2001 wm_prog_key
.blit_scaled
=
2002 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2003 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2005 /* Scaling factors used for bilinear filtering in multisample scaled
2008 wm_prog_key
.x_scale
= 2.0f
;
2009 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0f
;
2011 if (filter
== GL_LINEAR
&&
2012 params
.src
.num_samples
<= 1 && params
.dst
.num_samples
<= 1)
2013 wm_prog_key
.bilinear_filter
= true;
2015 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2016 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2017 base_format
!= GL_STENCIL_INDEX
&&
2018 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2019 /* We are downsampling a color buffer, so blend. */
2020 wm_prog_key
.blend
= true;
2023 /* src_samples and dst_samples are the true sample counts */
2024 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2025 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2027 /* tex_samples and rt_samples are the sample counts that are set up in
2030 wm_prog_key
.tex_samples
= params
.src
.num_samples
;
2031 wm_prog_key
.rt_samples
= params
.dst
.num_samples
;
2033 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2034 * use to access the source and destination surfaces.
2036 wm_prog_key
.tex_layout
=
2037 compute_msaa_layout_for_pipeline(brw
, params
.src
.num_samples
,
2038 params
.src
.msaa_layout
);
2039 wm_prog_key
.rt_layout
=
2040 compute_msaa_layout_for_pipeline(brw
, params
.dst
.num_samples
,
2041 params
.dst
.msaa_layout
);
2043 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2046 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2047 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2049 wm_prog_key
.src_tiled_w
= params
.src
.map_stencil_as_y_tiled
;
2050 wm_prog_key
.dst_tiled_w
= params
.dst
.map_stencil_as_y_tiled
;
2051 /* Round floating point values to nearest integer to avoid "off by one texel"
2052 * kind of errors when blitting.
2054 params
.x0
= params
.wm_push_consts
.dst_x0
= roundf(dst_x0
);
2055 params
.y0
= params
.wm_push_consts
.dst_y0
= roundf(dst_y0
);
2056 params
.x1
= params
.wm_push_consts
.dst_x1
= roundf(dst_x1
);
2057 params
.y1
= params
.wm_push_consts
.dst_y1
= roundf(dst_y1
);
2058 params
.wm_push_consts
.rect_grid_x1
=
2059 minify(src_mt
->logical_width0
, src_level
) * wm_prog_key
.x_scale
- 1.0f
;
2060 params
.wm_push_consts
.rect_grid_y1
=
2061 minify(src_mt
->logical_height0
, src_level
) * wm_prog_key
.y_scale
- 1.0f
;
2063 params
.wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2064 params
.wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2066 params
.wm_push_consts
.src_z
=
2067 params
.src
.mt
->target
== GL_TEXTURE_3D
? params
.src
.layer
: 0;
2069 if (params
.dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2070 /* We must expand the rectangle we send through the rendering pipeline,
2071 * to account for the fact that we are mapping the destination region as
2072 * single-sampled when it is in fact multisampled. We must also align
2073 * it to a multiple of the multisampling pattern, because the
2074 * differences between multisampled and single-sampled surface formats
2075 * will mean that pixels are scrambled within the multisampling pattern.
2076 * TODO: what if this makes the coordinates too large?
2078 * Note: this only works if the destination surface uses the IMS layout.
2079 * If it's UMS, then we have no choice but to set up the rendering
2080 * pipeline as multisampled.
2082 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2083 switch (dst_mt
->num_samples
) {
2085 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
2086 params
.y0
= ROUND_DOWN_TO(params
.y0
, 4);
2087 params
.x1
= ALIGN(params
.x1
* 2, 4);
2088 params
.y1
= ALIGN(params
.y1
, 4);
2091 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
2092 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
2093 params
.x1
= ALIGN(params
.x1
* 2, 4);
2094 params
.y1
= ALIGN(params
.y1
* 2, 4);
2097 params
.x0
= ROUND_DOWN_TO(params
.x0
* 4, 8);
2098 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
2099 params
.x1
= ALIGN(params
.x1
* 4, 8);
2100 params
.y1
= ALIGN(params
.y1
* 2, 4);
2103 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2105 wm_prog_key
.use_kill
= true;
2108 if (params
.dst
.map_stencil_as_y_tiled
) {
2109 /* We must modify the rectangle we send through the rendering pipeline
2110 * (and the size and x/y offset of the destination surface), to account
2111 * for the fact that we are mapping it as Y-tiled when it is in fact
2114 * Both Y tiling and W tiling can be understood as organizations of
2115 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2116 * is different, but the layout of the 32-byte sub-tiles within the 4k
2117 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2118 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2119 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2121 * Therefore, to account for the layout differences within the 32-byte
2122 * sub-tiles, we must expand the rectangle so the X coordinates of its
2123 * edges are multiples of 8 (the W sub-tile width), and its Y
2124 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2125 * Then we need to scale the X and Y coordinates of the rectangle to
2126 * account for the differences in aspect ratio between the Y and W
2127 * sub-tiles. We need to modify the layer width and height similarly.
2129 * A correction needs to be applied when MSAA is in use: since
2130 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2131 * we need to align the Y coordinates to multiples of 8, so that when
2132 * they are divided by two they are still multiples of 4.
2134 * Note: Since the x/y offset of the surface will be applied using the
2135 * SURFACE_STATE command packet, it will be invisible to the swizzling
2136 * code in the shader; therefore it needs to be in a multiple of the
2137 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2138 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2139 * buffer), and the miplevel alignment used for stencil buffers is 8
2140 * pixels horizontally and either 4 or 8 pixels vertically (see
2141 * intel_horizontal_texture_alignment_unit() and
2142 * intel_vertical_texture_alignment_unit()).
2144 * Note: Also, since the SURFACE_STATE command packet can only apply
2145 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2146 * vertically, it is important that the offsets will be multiples of
2147 * these sizes after they are converted into Y-tiled coordinates.
2148 * Fortunately they will be, since we know from above that the offsets
2149 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2150 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2152 * TODO: what if this makes the coordinates (or the texture size) too
2155 const unsigned x_align
= 8, y_align
= params
.dst
.num_samples
!= 0 ? 8 : 4;
2156 params
.x0
= ROUND_DOWN_TO(params
.x0
, x_align
) * 2;
2157 params
.y0
= ROUND_DOWN_TO(params
.y0
, y_align
) / 2;
2158 params
.x1
= ALIGN(params
.x1
, x_align
) * 2;
2159 params
.y1
= ALIGN(params
.y1
, y_align
) / 2;
2160 params
.dst
.width
= ALIGN(params
.dst
.width
, x_align
) * 2;
2161 params
.dst
.height
= ALIGN(params
.dst
.height
, y_align
) / 2;
2162 params
.dst
.x_offset
*= 2;
2163 params
.dst
.y_offset
/= 2;
2164 wm_prog_key
.use_kill
= true;
2167 if (params
.src
.map_stencil_as_y_tiled
) {
2168 /* We must modify the size and x/y offset of the source surface to
2169 * account for the fact that we are mapping it as Y-tiled when it is in
2172 * See the comments above concerning x/y offset alignment for the
2173 * destination surface.
2175 * TODO: what if this makes the texture size too large?
2177 const unsigned x_align
= 8, y_align
= params
.src
.num_samples
!= 0 ? 8 : 4;
2178 params
.src
.width
= ALIGN(params
.src
.width
, x_align
) * 2;
2179 params
.src
.height
= ALIGN(params
.src
.height
, y_align
) / 2;
2180 params
.src
.x_offset
*= 2;
2181 params
.src
.y_offset
/= 2;
2184 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2185 &wm_prog_key
, sizeof(wm_prog_key
),
2186 ¶ms
.wm_prog_kernel
, ¶ms
.wm_prog_data
)) {
2187 brw_blorp_blit_program
prog(brw
, &wm_prog_key
);
2188 GLuint program_size
;
2189 const GLuint
*program
= prog
.compile(brw
, INTEL_DEBUG
& DEBUG_BLORP
,
2191 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2192 &wm_prog_key
, sizeof(wm_prog_key
),
2193 program
, program_size
,
2194 &prog
.prog_data
, sizeof(prog
.prog_data
),
2195 ¶ms
.wm_prog_kernel
, ¶ms
.wm_prog_data
);
2198 params
.src
.swizzle
= src_swizzle
;
2200 brw_blorp_exec(brw
, ¶ms
);
2202 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);