2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
27 #include "glsl/ralloc.h"
29 #include "intel_fbo.h"
31 #include "brw_blorp.h"
32 #include "brw_context.h"
34 #include "brw_state.h"
38 * Helper function for handling mirror image blits.
40 * If coord0 > coord1, swap them and invert the "mirror" boolean.
43 fixup_mirroring(bool &mirror
, GLint
&coord0
, GLint
&coord1
)
45 if (coord0
> coord1
) {
55 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
56 * destination coordinates.
58 * Return true if there is still blitting to do, false if all pixels got
59 * rejected by the clip and/or scissor.
61 * For clarity, the nomenclature of this function assumes we are clipping and
62 * scissoring the X coordinate; the exact same logic applies for Y
65 * Note: this function may also be used to account for clipping of source
66 * coordinates, by swapping the roles of src and dst.
69 clip_or_scissor(bool mirror
, GLint
&src_x0
, GLint
&src_x1
, GLint
&dst_x0
,
70 GLint
&dst_x1
, GLint fb_xmin
, GLint fb_xmax
)
72 /* If we are going to scissor everything away, stop. */
73 if (!(fb_xmin
< fb_xmax
&&
80 /* Clip the destination rectangle, and keep track of how many pixels we
81 * clipped off of the left and right sides of it.
83 GLint pixels_clipped_left
= 0;
84 GLint pixels_clipped_right
= 0;
85 if (dst_x0
< fb_xmin
) {
86 pixels_clipped_left
= fb_xmin
- dst_x0
;
89 if (fb_xmax
< dst_x1
) {
90 pixels_clipped_right
= dst_x1
- fb_xmax
;
94 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
95 * the source coordinates, we need to flip them to account for the
99 GLint tmp
= pixels_clipped_left
;
100 pixels_clipped_left
= pixels_clipped_right
;
101 pixels_clipped_right
= tmp
;
104 /* Adjust the source rectangle to remove the pixels corresponding to those
105 * that were clipped/scissored out of the destination rectangle.
107 src_x0
+= pixels_clipped_left
;
108 src_x1
-= pixels_clipped_right
;
114 static struct intel_mipmap_tree
*
115 find_miptree(GLbitfield buffer_bit
, struct gl_renderbuffer
*rb
)
117 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
118 struct intel_mipmap_tree
*mt
= irb
->mt
;
119 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
125 brw_blorp_blit_miptrees(struct intel_context
*intel
,
126 struct intel_mipmap_tree
*src_mt
,
127 struct intel_mipmap_tree
*dst_mt
,
128 int src_x0
, int src_y0
,
129 int dst_x0
, int dst_y0
,
130 int dst_x1
, int dst_y1
,
131 bool mirror_x
, bool mirror_y
)
133 brw_blorp_blit_params
params(brw_context(&intel
->ctx
),
139 brw_blorp_exec(intel
, ¶ms
);
143 do_blorp_blit(struct intel_context
*intel
, GLbitfield buffer_bit
,
144 struct gl_renderbuffer
*src_rb
, struct gl_renderbuffer
*dst_rb
,
145 GLint srcX0
, GLint srcY0
,
146 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
147 bool mirror_x
, bool mirror_y
)
149 /* Find source/dst miptrees */
150 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_rb
);
151 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_rb
);
153 /* Get ready to blit. This includes depth resolving the src and dst
154 * buffers if necessary.
156 intel_renderbuffer_resolve_depth(intel
, intel_renderbuffer(src_rb
));
157 intel_renderbuffer_resolve_depth(intel
, intel_renderbuffer(dst_rb
));
160 brw_blorp_blit_miptrees(intel
, src_mt
, dst_mt
,
161 srcX0
, srcY0
, dstX0
, dstY0
, dstX1
, dstY1
,
164 intel_renderbuffer_set_needs_hiz_resolve(intel_renderbuffer(dst_rb
));
165 intel_renderbuffer_set_needs_downsample(intel_renderbuffer(dst_rb
));
170 formats_match(GLbitfield buffer_bit
, struct gl_renderbuffer
*src_rb
,
171 struct gl_renderbuffer
*dst_rb
)
173 /* Note: don't just check gl_renderbuffer::Format, because in some cases
174 * multiple gl_formats resolve to the same native type in the miptree (for
175 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
176 * between those formats.
178 return find_miptree(buffer_bit
, src_rb
)->format
==
179 find_miptree(buffer_bit
, dst_rb
)->format
;
184 try_blorp_blit(struct intel_context
*intel
,
185 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
186 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
187 GLenum filter
, GLbitfield buffer_bit
)
189 struct gl_context
*ctx
= &intel
->ctx
;
191 /* Sync up the state of window system buffers. We need to do this before
192 * we go looking for the buffers.
194 intel_prepare_render(intel
);
196 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
197 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
199 /* Detect if the blit needs to be mirrored */
200 bool mirror_x
= false, mirror_y
= false;
201 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
202 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
203 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
204 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
206 /* Make sure width and height match */
207 if (srcX1
- srcX0
!= dstX1
- dstX0
) return false;
208 if (srcY1
- srcY0
!= dstY1
- dstY0
) return false;
210 /* If the destination rectangle needs to be clipped or scissored, do so.
212 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
213 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
214 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
215 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
216 /* Everything got clipped/scissored away, so the blit was successful. */
220 /* If the source rectangle needs to be clipped or scissored, do so. */
221 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
222 0, read_fb
->Width
) &&
223 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
224 0, read_fb
->Height
))) {
225 /* Everything got clipped/scissored away, so the blit was successful. */
229 /* Account for the fact that in the system framebuffer, the origin is at
232 if (_mesa_is_winsys_fbo(read_fb
)) {
233 GLint tmp
= read_fb
->Height
- srcY0
;
234 srcY0
= read_fb
->Height
- srcY1
;
236 mirror_y
= !mirror_y
;
238 if (_mesa_is_winsys_fbo(draw_fb
)) {
239 GLint tmp
= draw_fb
->Height
- dstY0
;
240 dstY0
= draw_fb
->Height
- dstY1
;
242 mirror_y
= !mirror_y
;
246 struct gl_renderbuffer
*src_rb
;
247 struct gl_renderbuffer
*dst_rb
;
248 switch (buffer_bit
) {
249 case GL_COLOR_BUFFER_BIT
:
250 src_rb
= read_fb
->_ColorReadBuffer
;
251 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
252 dst_rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
253 if (dst_rb
&& !formats_match(buffer_bit
, src_rb
, dst_rb
))
256 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
257 dst_rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[i
];
258 do_blorp_blit(intel
, buffer_bit
, src_rb
, dst_rb
, srcX0
, srcY0
,
259 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
262 case GL_DEPTH_BUFFER_BIT
:
263 src_rb
= read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
264 dst_rb
= draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
;
265 if (!formats_match(buffer_bit
, src_rb
, dst_rb
))
267 do_blorp_blit(intel
, buffer_bit
, src_rb
, dst_rb
, srcX0
, srcY0
,
268 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
270 case GL_STENCIL_BUFFER_BIT
:
271 src_rb
= read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
272 dst_rb
= draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
273 if (!formats_match(buffer_bit
, src_rb
, dst_rb
))
275 do_blorp_blit(intel
, buffer_bit
, src_rb
, dst_rb
, srcX0
, srcY0
,
276 dstX0
, dstY0
, dstX1
, dstY1
, mirror_x
, mirror_y
);
286 brw_blorp_framebuffer(struct intel_context
*intel
,
287 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
288 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
289 GLbitfield mask
, GLenum filter
)
291 /* BLORP is not supported before Gen6. */
295 static GLbitfield buffer_bits
[] = {
298 GL_STENCIL_BUFFER_BIT
,
301 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
302 if ((mask
& buffer_bits
[i
]) &&
303 try_blorp_blit(intel
,
304 srcX0
, srcY0
, srcX1
, srcY1
,
305 dstX0
, dstY0
, dstX1
, dstY1
,
306 filter
, buffer_bits
[i
])) {
307 mask
&= ~buffer_bits
[i
];
316 * Enum to specify the order of arguments in a sampler message
318 enum sampler_message_arg
320 SAMPLER_MESSAGE_ARG_U_FLOAT
,
321 SAMPLER_MESSAGE_ARG_V_FLOAT
,
322 SAMPLER_MESSAGE_ARG_U_INT
,
323 SAMPLER_MESSAGE_ARG_V_INT
,
324 SAMPLER_MESSAGE_ARG_SI_INT
,
325 SAMPLER_MESSAGE_ARG_MCS_INT
,
326 SAMPLER_MESSAGE_ARG_ZERO_INT
,
330 * Generator for WM programs used in BLORP blits.
332 * The bulk of the work done by the WM program is to wrap and unwrap the
333 * coordinate transformations used by the hardware to store surfaces in
334 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
335 * sample index for a multisampled surface) to a memory offset by the
336 * following formulas:
338 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
339 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
341 * For a single-sampled surface, or for a multisampled surface using
342 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
345 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
346 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
347 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
348 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
350 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
351 * embeds the sample number into bit 1 of the X and Y coordinates:
353 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
354 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
355 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
356 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
357 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
358 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
359 * S = (Y & 0b10) | (X & 0b10) >> 1
361 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
362 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
365 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
366 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
367 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
368 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
369 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
370 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
371 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
373 * For X tiling, tile() combines together the low-order bits of the X and Y
374 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
375 * bytes wide and 8 rows high:
377 * tile(x_tiled, X, Y, S) = A
378 * where A = tile_num << 12 | offset
379 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
380 * offset = (Y' & 0b111) << 9
381 * | (X & 0b111111111)
383 * Y' = Y + S * qpitch
384 * detile(x_tiled, A) = (X, Y, S)
388 * Y' = (tile_num / tile_pitch) << 3
389 * | (A & 0b111000000000) >> 9
390 * X' = (tile_num % tile_pitch) << 9
391 * | (A & 0b111111111)
393 * (In all tiling formulas, cpp is the number of bytes occupied by a single
394 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
395 * to fill the width of the surface, and qpitch is the spacing (in rows)
396 * between array slices).
398 * For Y tiling, tile() combines together the low-order bits of the X and Y
399 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
400 * bytes wide and 32 rows high:
402 * tile(y_tiled, X, Y, S) = A
403 * where A = tile_num << 12 | offset
404 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
405 * offset = (X' & 0b1110000) << 5
406 * | (Y' & 0b11111) << 4
409 * Y' = Y + S * qpitch
410 * detile(y_tiled, A) = (X, Y, S)
414 * Y' = (tile_num / tile_pitch) << 5
415 * | (A & 0b111110000) >> 4
416 * X' = (tile_num % tile_pitch) << 7
417 * | (A & 0b111000000000) >> 5
420 * For W tiling, tile() combines together the low-order bits of the X and Y
421 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
422 * bytes wide and 64 rows high (note that W tiling is only used for stencil
423 * buffers, which always have cpp = 1 and S=0):
425 * tile(w_tiled, X, Y, S) = A
426 * where A = tile_num << 12 | offset
427 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
428 * offset = (X' & 0b111000) << 6
429 * | (Y' & 0b111100) << 3
430 * | (X' & 0b100) << 2
436 * Y' = Y + S * qpitch
437 * detile(w_tiled, A) = (X, Y, S)
438 * where X = X' / cpp = X'
439 * Y = Y' % qpitch = Y'
441 * Y' = (tile_num / tile_pitch) << 6
442 * | (A & 0b111100000) >> 3
443 * | (A & 0b1000) >> 2
445 * X' = (tile_num % tile_pitch) << 6
446 * | (A & 0b111000000000) >> 6
447 * | (A & 0b10000) >> 2
451 * Finally, for a non-tiled surface, tile() simply combines together the X and
452 * Y coordinates in the natural way:
454 * tile(untiled, X, Y, S) = A
455 * where A = Y * pitch + X'
457 * Y' = Y + S * qpitch
458 * detile(untiled, A) = (X, Y, S)
465 * (In these formulas, pitch is the number of bytes occupied by a single row
468 class brw_blorp_blit_program
471 brw_blorp_blit_program(struct brw_context
*brw
,
472 const brw_blorp_blit_prog_key
*key
);
473 ~brw_blorp_blit_program();
475 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
477 brw_blorp_prog_data prog_data
;
481 void alloc_push_const_regs(int base_reg
);
482 void compute_frag_coords();
483 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
484 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
485 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
486 void kill_if_outside_dst_rect();
487 void translate_dst_to_src();
488 void single_to_blend();
489 void manual_blend(unsigned num_samples
);
490 void sample(struct brw_reg dst
);
491 void texel_fetch(struct brw_reg dst
);
493 void expand_to_32_bits(struct brw_reg src
, struct brw_reg dst
);
494 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
495 const sampler_message_arg
*args
, int num_args
);
496 void render_target_write();
499 * Base-2 logarithm of the maximum number of samples that can be blended.
501 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
504 struct brw_context
*brw
;
505 const brw_blorp_blit_prog_key
*key
;
506 struct brw_compile func
;
508 /* Thread dispatch header */
511 /* Pixel X/Y coordinates (always in R1). */
515 struct brw_reg dst_x0
;
516 struct brw_reg dst_x1
;
517 struct brw_reg dst_y0
;
518 struct brw_reg dst_y1
;
520 struct brw_reg multiplier
;
521 struct brw_reg offset
;
522 } x_transform
, y_transform
;
524 /* Data read from texture (4 vec16's per array element) */
525 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
527 /* Auxiliary storage for the contents of the MCS surface.
529 * Since the sampler always returns 8 registers worth of data, this is 8
530 * registers wide, even though we only use the first 2 registers of it.
532 struct brw_reg mcs_data
;
534 /* X coordinates. We have two of them so that we can perform coordinate
535 * transformations easily.
537 struct brw_reg x_coords
[2];
539 /* Y coordinates. We have two of them so that we can perform coordinate
540 * transformations easily.
542 struct brw_reg y_coords
[2];
544 /* Which element of x_coords and y_coords is currently in use.
548 /* True if, at the point in the program currently being compiled, the
549 * sample index is known to be zero.
553 /* Register storing the sample index when s_is_zero is false. */
554 struct brw_reg sample_index
;
560 /* MRF used for sampling and render target writes */
564 brw_blorp_blit_program::brw_blorp_blit_program(
565 struct brw_context
*brw
,
566 const brw_blorp_blit_prog_key
*key
)
567 : mem_ctx(ralloc_context(NULL
)),
571 brw_init_compile(brw
, &func
, mem_ctx
);
574 brw_blorp_blit_program::~brw_blorp_blit_program()
576 ralloc_free(mem_ctx
);
580 brw_blorp_blit_program::compile(struct brw_context
*brw
,
581 GLuint
*program_size
)
584 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
585 /* If the destination image is W tiled and multisampled, then the thread
586 * must be dispatched once per sample, not once per pixel. This is
587 * necessary because after conversion between W and Y tiling, there's no
588 * guarantee that all samples corresponding to a single pixel will still
591 assert(key
->persample_msaa_dispatch
);
595 /* We are blending, which means we won't have an opportunity to
596 * translate the tiling and sample count for the texture surface. So
597 * the surface state for the texture must be configured with the correct
598 * tiling and sample count.
600 assert(!key
->src_tiled_w
);
601 assert(key
->tex_samples
== key
->src_samples
);
602 assert(key
->tex_layout
== key
->src_layout
);
603 assert(key
->tex_samples
> 0);
606 if (key
->persample_msaa_dispatch
) {
607 /* It only makes sense to do persample dispatch if the render target is
608 * configured as multisampled.
610 assert(key
->rt_samples
> 0);
613 /* Make sure layout is consistent with sample count */
614 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
615 (key
->tex_samples
== 0));
616 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
617 (key
->rt_samples
== 0));
618 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
619 (key
->src_samples
== 0));
620 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
621 (key
->dst_samples
== 0));
623 /* Set up prog_data */
624 memset(&prog_data
, 0, sizeof(prog_data
));
625 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
627 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
630 compute_frag_coords();
632 /* Render target and texture hardware don't support W tiling. */
633 const bool rt_tiled_w
= false;
634 const bool tex_tiled_w
= false;
636 /* The address that data will be written to is determined by the
637 * coordinates supplied to the WM thread and the tiling and sample count of
638 * the render target, according to the formula:
640 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
642 * If the actual tiling and sample count of the destination surface are not
643 * the same as the configuration of the render target, then these
644 * coordinates are wrong and we have to adjust them to compensate for the
647 if (rt_tiled_w
!= key
->dst_tiled_w
||
648 key
->rt_samples
!= key
->dst_samples
||
649 key
->rt_layout
!= key
->dst_layout
) {
650 encode_msaa(key
->rt_samples
, key
->rt_layout
);
651 /* Now (X, Y, S) = detile(rt_tiling, offset) */
652 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
653 /* Now (X, Y, S) = detile(dst_tiling, offset) */
654 decode_msaa(key
->dst_samples
, key
->dst_layout
);
657 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
659 * That is: X, Y and S now contain the true coordinates and sample index of
660 * the data that the WM thread should output.
662 * If we need to kill pixels that are outside the destination rectangle,
663 * now is the time to do it.
667 kill_if_outside_dst_rect();
669 /* Next, apply a translation to obtain coordinates in the source image. */
670 translate_dst_to_src();
672 /* If the source image is not multisampled, then we want to fetch sample
673 * number 0, because that's the only sample there is.
675 if (key
->src_samples
== 0)
678 /* X, Y, and S are now the coordinates of the pixel in the source image
679 * that we want to texture from. Exception: if we are blending, then S is
680 * irrelevant, because we are going to fetch all samples.
683 if (brw
->intel
.gen
== 6) {
684 /* Gen6 hardware an automatically blend using the SAMPLE message */
686 sample(texture_data
[0]);
688 /* Gen7+ hardware doesn't automaticaly blend. */
689 manual_blend(key
->src_samples
);
692 /* We aren't blending, which means we just want to fetch a single sample
693 * from the source surface. The address that we want to fetch from is
694 * related to the X, Y and S values according to the formula:
696 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
698 * If the actual tiling and sample count of the source surface are not
699 * the same as the configuration of the texture, then we need to adjust
700 * the coordinates to compensate for the difference.
702 if (tex_tiled_w
!= key
->src_tiled_w
||
703 key
->tex_samples
!= key
->src_samples
||
704 key
->tex_layout
!= key
->src_layout
) {
705 encode_msaa(key
->src_samples
, key
->src_layout
);
706 /* Now (X, Y, S) = detile(src_tiling, offset) */
707 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
708 /* Now (X, Y, S) = detile(tex_tiling, offset) */
709 decode_msaa(key
->tex_samples
, key
->tex_layout
);
712 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
714 * In other words: X, Y, and S now contain values which, when passed to
715 * the texturing unit, will cause data to be read from the correct
716 * memory location. So we can fetch the texel now.
718 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
720 texel_fetch(texture_data
[0]);
723 /* Finally, write the fetched (or blended) value to the render target and
724 * terminate the thread.
726 render_target_write();
727 return brw_get_program(&func
, program_size
);
731 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
733 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
734 #define ALLOC_REG(name) \
736 brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, base_reg, CONST_LOC(name) / 2)
742 ALLOC_REG(x_transform
.multiplier
);
743 ALLOC_REG(x_transform
.offset
);
744 ALLOC_REG(y_transform
.multiplier
);
745 ALLOC_REG(y_transform
.offset
);
751 brw_blorp_blit_program::alloc_regs()
754 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
755 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
756 prog_data
.first_curbe_grf
= reg
;
757 alloc_push_const_regs(reg
);
758 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
759 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
760 this->texture_data
[i
] =
761 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
765 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
766 for (int i
= 0; i
< 2; ++i
) {
768 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
770 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
772 this->xy_coord_index
= 0;
774 = vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
775 this->t1
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
776 this->t2
= vec16(retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
));
778 /* Make sure we didn't run out of registers */
779 assert(reg
<= GEN7_MRF_HACK_START
);
782 this->base_mrf
= mrf
;
785 /* In the code that follows, X and Y can be used to quickly refer to the
786 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
787 * prime") to the inactive elements.
789 * S can be used to quickly refer to sample_index.
791 #define X x_coords[xy_coord_index]
792 #define Y y_coords[xy_coord_index]
793 #define Xp x_coords[!xy_coord_index]
794 #define Yp y_coords[!xy_coord_index]
795 #define S sample_index
797 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
798 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
800 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
803 * Emit code to compute the X and Y coordinates of the pixels being rendered
804 * by this WM invocation.
806 * Assuming the render target is set up for Y tiling, these (X, Y) values are
807 * related to the address offset where outputs will be written by the formula:
809 * (X, Y, S) = decode_msaa(detile(offset)).
811 * (See brw_blorp_blit_program).
814 brw_blorp_blit_program::compute_frag_coords()
816 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
817 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
818 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
819 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
821 * Pixels within a subspan are laid out in this arrangement:
825 * So, to compute the coordinates of each pixel, we need to read every 2nd
826 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
827 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
828 * In other words, the data we want to access is R1.4<2;4,0>UW.
830 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
831 * result, since pixels n+1 and n+3 are in the right half of the subspan.
833 brw_ADD(&func
, X
, stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
835 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
836 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
837 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
840 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
841 * pixels n+2 and n+3 are in the bottom half of the subspan.
843 brw_ADD(&func
, Y
, stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
845 if (key
->persample_msaa_dispatch
) {
846 switch (key
->rt_samples
) {
848 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
849 * Therefore, subspan 0 will represent sample 0, subspan 1 will
850 * represent sample 1, and so on.
852 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
853 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
854 * populate a temporary variable with the sequence (0, 1, 2, 3), and
855 * then copy from it using vstride=1, width=4, hstride=0.
857 brw_MOV(&func
, t1
, brw_imm_v(0x3210));
858 brw_MOV(&func
, S
, stride(t1
, 1, 4, 0));
861 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
862 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
863 * subspan 1 will represent sample 1, and so on. We can find the
864 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
865 * Index") and multiplying by two (since samples are always delivered
866 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
869 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
870 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
871 * variable with the sequence (0, 1, 2, 3), and then reading from it
872 * using vstride=1, width=4, hstride=0.
874 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
875 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
876 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
877 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
878 brw_MOV(&func
, t2
, brw_imm_v(0x3210));
879 brw_ADD(&func
, S
, retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
880 stride(t2
, 1, 4, 0));
884 assert(!"Unrecognized sample count in "
885 "brw_blorp_blit_program::compute_frag_coords()");
890 /* Either the destination surface is single-sampled, or the WM will be
891 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
892 * per pixel). In either case, it's not meaningful to compute a sample
893 * value. Just set it to 0.
900 * Emit code to compensate for the difference between Y and W tiling.
902 * This code modifies the X and Y coordinates according to the formula:
904 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
906 * (See brw_blorp_blit_program).
908 * It can only translate between W and Y tiling, so new_tiling and old_tiling
909 * are booleans where true represents W tiling and false represents Y tiling.
912 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
914 if (old_tiled_w
== new_tiled_w
)
917 /* In the code that follows, we can safely assume that S = 0, because W
918 * tiling formats always use IMS layout.
923 /* Given X and Y coordinates that describe an address using Y tiling,
924 * translate to the X and Y coordinates that describe the same address
927 * If we break down the low order bits of X and Y, using a
928 * single letter to represent each low-order bit:
930 * X = A << 7 | 0bBCDEFGH
931 * Y = J << 5 | 0bKLMNP (1)
933 * Then we can apply the Y tiling formula to see the memory offset being
936 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
938 * If we apply the W detiling formula to this memory location, that the
939 * corresponding X' and Y' coordinates are:
941 * X' = A << 6 | 0bBCDPFH (3)
942 * Y' = J << 6 | 0bKLMNEG
944 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
945 * we need to make the following computation:
947 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
948 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
950 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
951 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
952 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
953 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
954 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
955 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
956 brw_OR(&func
, Xp
, t1
, t2
);
957 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
958 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
959 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
960 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
961 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
962 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
963 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
964 brw_OR(&func
, Yp
, t1
, t2
);
967 /* Applying the same logic as above, but in reverse, we obtain the
970 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
971 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
973 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
974 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
975 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
976 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
977 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
978 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
979 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
980 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
982 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
983 brw_OR(&func
, Xp
, t1
, t2
);
984 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
985 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
986 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
987 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
988 brw_OR(&func
, Yp
, t1
, t2
);
994 * Emit code to compensate for the difference between MSAA and non-MSAA
997 * This code modifies the X and Y coordinates according to the formula:
999 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1001 * (See brw_blorp_blit_program).
1004 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1005 intel_msaa_layout layout
)
1008 case INTEL_MSAA_LAYOUT_NONE
:
1009 /* No translation necessary, and S should already be zero. */
1012 case INTEL_MSAA_LAYOUT_CMS
:
1013 /* We can't compensate for compressed layout since at this point in the
1014 * program we haven't read from the MCS buffer.
1016 assert(!"Bad layout in encode_msaa");
1018 case INTEL_MSAA_LAYOUT_UMS
:
1019 /* No translation necessary. */
1021 case INTEL_MSAA_LAYOUT_IMS
:
1022 switch (num_samples
) {
1024 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1025 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1026 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1028 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1030 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1031 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1033 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1035 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1036 brw_OR(&func
, Xp
, t1
, t2
);
1037 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1038 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1040 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1041 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1043 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1044 brw_OR(&func
, Yp
, t1
, t2
);
1047 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1048 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1050 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1052 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1053 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1055 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1056 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1057 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1058 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1059 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1062 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1063 brw_OR(&func
, Xp
, t1
, t2
);
1064 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1065 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1067 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1068 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1070 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1071 brw_OR(&func
, Yp
, t1
, t2
);
1081 * Emit code to compensate for the difference between MSAA and non-MSAA
1084 * This code modifies the X and Y coordinates according to the formula:
1086 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1088 * (See brw_blorp_blit_program).
1091 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1092 intel_msaa_layout layout
)
1095 case INTEL_MSAA_LAYOUT_NONE
:
1096 /* No translation necessary, and S should already be zero. */
1099 case INTEL_MSAA_LAYOUT_CMS
:
1100 /* We can't compensate for compressed layout since at this point in the
1101 * program we don't have access to the MCS buffer.
1103 assert(!"Bad layout in encode_msaa");
1105 case INTEL_MSAA_LAYOUT_UMS
:
1106 /* No translation necessary. */
1108 case INTEL_MSAA_LAYOUT_IMS
:
1110 switch (num_samples
) {
1112 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1113 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1114 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1115 * S = (Y & 0b10) | (X & 0b10) >> 1
1117 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1118 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1119 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1120 brw_OR(&func
, Xp
, t1
, t2
);
1121 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1122 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1123 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1124 brw_OR(&func
, Yp
, t1
, t2
);
1125 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1126 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1127 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1128 brw_OR(&func
, S
, t1
, t2
);
1131 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1132 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1133 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1134 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1136 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1137 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1138 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1139 brw_OR(&func
, Xp
, t1
, t2
);
1140 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1141 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1142 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1143 brw_OR(&func
, Yp
, t1
, t2
);
1144 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1145 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1146 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1147 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1148 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1149 brw_OR(&func
, S
, t1
, t2
);
1159 * Emit code that kills pixels whose X and Y coordinates are outside the
1160 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1164 brw_blorp_blit_program::kill_if_outside_dst_rect()
1166 struct brw_reg f0
= brw_flag_reg();
1167 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1168 struct brw_reg null16
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
1170 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1171 brw_CMP(&func
, null16
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1172 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1173 brw_CMP(&func
, null16
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1175 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1176 brw_push_insn_state(&func
);
1177 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1178 brw_AND(&func
, g1
, f0
, g1
);
1179 brw_pop_insn_state(&func
);
1183 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1187 brw_blorp_blit_program::translate_dst_to_src()
1189 brw_MUL(&func
, Xp
, X
, x_transform
.multiplier
);
1190 brw_MUL(&func
, Yp
, Y
, y_transform
.multiplier
);
1191 brw_ADD(&func
, Xp
, Xp
, x_transform
.offset
);
1192 brw_ADD(&func
, Yp
, Yp
, y_transform
.offset
);
1197 * Emit code to transform the X and Y coordinates as needed for blending
1198 * together the different samples in an MSAA texture.
1201 brw_blorp_blit_program::single_to_blend()
1203 /* When looking up samples in an MSAA texture using the SAMPLE message,
1204 * Gen6 requires the texture coordinates to be odd integers (so that they
1205 * correspond to the center of a 2x2 block representing the four samples
1206 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1207 * each by 2 and then add 1.
1209 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1210 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1211 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1212 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1218 * Count the number of trailing 1 bits in the given value. For example:
1220 * count_trailing_one_bits(0) == 0
1221 * count_trailing_one_bits(7) == 3
1222 * count_trailing_one_bits(11) == 2
1224 inline int count_trailing_one_bits(unsigned value
)
1226 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1227 return __builtin_ctz(~value
);
1229 return _mesa_bitcount(value
& ~(value
+ 1));
1235 brw_blorp_blit_program::manual_blend(unsigned num_samples
)
1237 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1240 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1242 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1244 * This ensures that when all samples have the same value, no numerical
1245 * precision is lost, since each addition operation always adds two equal
1246 * values, and summing two equal floating point values does not lose
1249 * We perform this computation by treating the texture_data array as a
1250 * stack and performing the following operations:
1252 * - push sample 0 onto stack
1253 * - push sample 1 onto stack
1254 * - add top two stack entries
1255 * - push sample 2 onto stack
1256 * - push sample 3 onto stack
1257 * - add top two stack entries
1258 * - add top two stack entries
1259 * - divide top stack entry by 4
1261 * Note that after pushing sample i onto the stack, the number of add
1262 * operations we do is equal to the number of trailing 1 bits in i. This
1263 * works provided the total number of samples is a power of two, which it
1264 * always is for i965.
1266 * For integer formats, we replace the add operations with average
1267 * operations and skip the final division.
1269 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1273 brw_op2_ptr combine_op
=
1274 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1275 unsigned stack_depth
= 0;
1276 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1277 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1279 /* Push sample i onto the stack */
1280 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1285 brw_MOV(&func
, S
, brw_imm_uw(i
));
1287 texel_fetch(texture_data
[stack_depth
++]);
1289 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1290 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1291 * suggests an optimization:
1293 * "A simple optimization with probable large return in
1294 * performance is to compare the MCS value to zero (indicating
1295 * all samples are on sample slice 0), and sample only from
1296 * sample slice 0 using ld2dss if MCS is zero."
1298 * Note that in the case where the MCS value is zero, sampling from
1299 * sample slice 0 using ld2dss and sampling from sample 0 using
1300 * ld2dms are equivalent (since all samples are on sample slice 0).
1301 * Since we have already sampled from sample 0, all we need to do is
1302 * skip the remaining fetches and averaging if MCS is zero.
1304 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1305 mcs_data
, brw_imm_ud(0));
1306 brw_IF(&func
, BRW_EXECUTE_16
);
1309 /* Do count_trailing_one_bits(i) times */
1310 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1311 assert(stack_depth
>= 2);
1314 /* TODO: should use a smaller loop bound for non_RGBA formats */
1315 for (int k
= 0; k
< 4; ++k
) {
1316 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1317 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1318 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1323 /* We should have just 1 sample on the stack now. */
1324 assert(stack_depth
== 1);
1326 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1327 /* Scale the result down by a factor of num_samples */
1328 /* TODO: should use a smaller loop bound for non-RGBA formats */
1329 for (int j
= 0; j
< 4; ++j
) {
1330 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1331 offset(vec8(texture_data
[0]), 2*j
),
1332 brw_imm_f(1.0/num_samples
));
1336 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1341 * Emit code to look up a value in the texture using the SAMPLE message (which
1342 * does blending of MSAA surfaces).
1345 brw_blorp_blit_program::sample(struct brw_reg dst
)
1347 static const sampler_message_arg args
[2] = {
1348 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1349 SAMPLER_MESSAGE_ARG_V_FLOAT
1352 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
, ARRAY_SIZE(args
));
1356 * Emit code to look up a value in the texture using the SAMPLE_LD message
1357 * (which does a simple texel fetch).
1360 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1362 static const sampler_message_arg gen6_args
[5] = {
1363 SAMPLER_MESSAGE_ARG_U_INT
,
1364 SAMPLER_MESSAGE_ARG_V_INT
,
1365 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1366 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1367 SAMPLER_MESSAGE_ARG_SI_INT
1369 static const sampler_message_arg gen7_ld_args
[3] = {
1370 SAMPLER_MESSAGE_ARG_U_INT
,
1371 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1372 SAMPLER_MESSAGE_ARG_V_INT
1374 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1375 SAMPLER_MESSAGE_ARG_SI_INT
,
1376 SAMPLER_MESSAGE_ARG_U_INT
,
1377 SAMPLER_MESSAGE_ARG_V_INT
1379 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1380 SAMPLER_MESSAGE_ARG_SI_INT
,
1381 SAMPLER_MESSAGE_ARG_MCS_INT
,
1382 SAMPLER_MESSAGE_ARG_U_INT
,
1383 SAMPLER_MESSAGE_ARG_V_INT
1386 switch (brw
->intel
.gen
) {
1388 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1392 switch (key
->tex_layout
) {
1393 case INTEL_MSAA_LAYOUT_IMS
:
1394 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1397 * If this field is MSFMT_DEPTH_STENCIL
1398 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1399 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1401 * So fall through to emit the same message as we use for
1402 * INTEL_MSAA_LAYOUT_CMS.
1404 case INTEL_MSAA_LAYOUT_CMS
:
1405 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1406 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1408 case INTEL_MSAA_LAYOUT_UMS
:
1409 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1410 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1412 case INTEL_MSAA_LAYOUT_NONE
:
1414 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1415 ARRAY_SIZE(gen7_ld_args
));
1420 assert(!"Should not get here.");
1426 brw_blorp_blit_program::mcs_fetch()
1428 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1429 SAMPLER_MESSAGE_ARG_U_INT
,
1430 SAMPLER_MESSAGE_ARG_V_INT
1432 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1433 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1437 brw_blorp_blit_program::expand_to_32_bits(struct brw_reg src
,
1440 brw_MOV(&func
, vec8(dst
), vec8(src
));
1441 brw_set_compression_control(&func
, BRW_COMPRESSION_2NDHALF
);
1442 brw_MOV(&func
, offset(vec8(dst
), 1), suboffset(vec8(src
), 8));
1443 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1447 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1449 const sampler_message_arg
*args
,
1452 struct brw_reg mrf
=
1453 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1454 for (int arg
= 0; arg
< num_args
; ++arg
) {
1455 switch (args
[arg
]) {
1456 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1457 expand_to_32_bits(X
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1459 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1460 expand_to_32_bits(Y
, retype(mrf
, BRW_REGISTER_TYPE_F
));
1462 case SAMPLER_MESSAGE_ARG_U_INT
:
1463 expand_to_32_bits(X
, mrf
);
1465 case SAMPLER_MESSAGE_ARG_V_INT
:
1466 expand_to_32_bits(Y
, mrf
);
1468 case SAMPLER_MESSAGE_ARG_SI_INT
:
1469 /* Note: on Gen7, this code may be reached with s_is_zero==true
1470 * because in Gen7's ld2dss message, the sample index is the first
1471 * argument. When this happens, we need to move a 0 into the
1472 * appropriate message register.
1475 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1477 expand_to_32_bits(S
, mrf
);
1479 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1480 switch (key
->tex_layout
) {
1481 case INTEL_MSAA_LAYOUT_CMS
:
1482 brw_MOV(&func
, mrf
, mcs_data
);
1484 case INTEL_MSAA_LAYOUT_IMS
:
1485 /* When sampling from an IMS surface, MCS data is not relevant,
1486 * and the hardware ignores it. So don't bother populating it.
1490 /* We shouldn't be trying to send MCS data with any other
1493 assert (!"Unsupported layout for MCS data");
1497 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1498 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1505 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1506 base_mrf
/* msg_reg_nr */,
1507 brw_message_reg(base_mrf
) /* src0 */,
1508 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1512 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1513 mrf
.nr
- base_mrf
/* msg_length */,
1514 0 /* header_present */,
1515 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1516 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1524 #undef SWAP_XY_AND_XPYP
1527 brw_blorp_blit_program::render_target_write()
1529 struct brw_reg mrf_rt_write
=
1530 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1533 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1534 * so that the render target knows which pixels we killed.
1536 bool use_header
= key
->use_kill
;
1538 /* Copy R0/1 to MRF */
1539 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1540 retype(R0
, BRW_REGISTER_TYPE_UD
));
1544 /* Copy texture data to MRFs */
1545 for (int i
= 0; i
< 4; ++i
) {
1546 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1547 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1548 offset(vec8(texture_data
[0]), 2*i
));
1552 /* Now write to the render target and terminate the thread */
1554 16 /* dispatch_width */,
1555 base_mrf
/* msg_reg_nr */,
1556 mrf_rt_write
/* src0 */,
1557 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1558 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1559 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1560 0 /* response_length */,
1567 brw_blorp_coord_transform_params::setup(GLuint src0
, GLuint dst0
, GLuint dst1
,
1571 /* When not mirroring a coordinate (say, X), we need:
1572 * x' - src_x0 = x - dst_x0
1574 * x' = 1*x + (src_x0 - dst_x0)
1577 offset
= src0
- dst0
;
1579 /* When mirroring X we need:
1580 * x' - src_x0 = dst_x1 - x - 1
1582 * x' = -1*x + (src_x0 + dst_x1 - 1)
1585 offset
= src0
+ dst1
- 1;
1591 * Determine which MSAA layout the GPU pipeline should be configured for,
1592 * based on the chip generation, the number of samples, and the true layout of
1593 * the image in memory.
1595 inline intel_msaa_layout
1596 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1597 intel_msaa_layout true_layout
)
1599 if (num_samples
<= 1) {
1600 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1601 * format buffers, by transforming coordinates appropriately.
1603 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1604 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1605 return INTEL_MSAA_LAYOUT_NONE
;
1607 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1610 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1611 if (brw
->intel
.gen
== 6) {
1612 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1619 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1620 struct intel_mipmap_tree
*src_mt
,
1621 struct intel_mipmap_tree
*dst_mt
,
1622 GLuint src_x0
, GLuint src_y0
,
1623 GLuint dst_x0
, GLuint dst_y0
,
1624 GLuint dst_x1
, GLuint dst_y1
,
1625 bool mirror_x
, bool mirror_y
)
1627 src
.set(brw
, src_mt
, 0, 0);
1628 dst
.set(brw
, dst_mt
, 0, 0);
1631 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1633 /* texture_data_type indicates the register type that should be used to
1634 * manipulate texture data.
1636 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1637 case GL_UNSIGNED_NORMALIZED
:
1638 case GL_SIGNED_NORMALIZED
:
1640 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1642 case GL_UNSIGNED_INT
:
1643 if (src_mt
->format
== MESA_FORMAT_S8
) {
1644 /* We process stencil as though it's an unsigned normalized color */
1645 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1647 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1651 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1654 assert(!"Unrecognized blorp format");
1658 if (brw
->intel
.gen
> 6) {
1659 /* Gen7's rendering hardware only supports the IMS layout for depth and
1660 * stencil render targets. Blorp always maps its destination surface as
1661 * a color render target (even if it's actually a depth or stencil
1662 * buffer). So if the destination is IMS, we'll have to map it as a
1663 * single-sampled texture and interleave the samples ourselves.
1665 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1666 dst
.num_samples
= 0;
1669 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1670 /* If the destination surface is a W-tiled multisampled stencil buffer
1671 * that we're mapping as Y tiled, then we need to arrange for the WM
1672 * program to run once per sample rather than once per pixel, because
1673 * the memory layout of related samples doesn't match between W and Y
1676 wm_prog_key
.persample_msaa_dispatch
= true;
1679 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1680 /* We are blitting from a multisample buffer to a multisample buffer, so
1681 * we must preserve samples within a pixel. This means we have to
1682 * arrange for the WM program to run once per sample rather than once
1685 wm_prog_key
.persample_msaa_dispatch
= true;
1688 /* The render path must be configured to use the same number of samples as
1689 * the destination buffer.
1691 num_samples
= dst
.num_samples
;
1693 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
1694 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
1695 base_format
!= GL_STENCIL_INDEX
&&
1696 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
1697 /* We are downsampling a color buffer, so blend. */
1698 wm_prog_key
.blend
= true;
1701 /* src_samples and dst_samples are the true sample counts */
1702 wm_prog_key
.src_samples
= src_mt
->num_samples
;
1703 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
1705 /* tex_samples and rt_samples are the sample counts that are set up in
1708 wm_prog_key
.tex_samples
= src
.num_samples
;
1709 wm_prog_key
.rt_samples
= dst
.num_samples
;
1711 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
1712 * use to access the source and destination surfaces.
1714 wm_prog_key
.tex_layout
=
1715 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
1716 wm_prog_key
.rt_layout
=
1717 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
1719 /* src_layout and dst_layout indicate the true MSAA layout used by src and
1722 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
1723 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
1725 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
1726 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
1727 x0
= wm_push_consts
.dst_x0
= dst_x0
;
1728 y0
= wm_push_consts
.dst_y0
= dst_y0
;
1729 x1
= wm_push_consts
.dst_x1
= dst_x1
;
1730 y1
= wm_push_consts
.dst_y1
= dst_y1
;
1731 wm_push_consts
.x_transform
.setup(src_x0
, dst_x0
, dst_x1
, mirror_x
);
1732 wm_push_consts
.y_transform
.setup(src_y0
, dst_y0
, dst_y1
, mirror_y
);
1734 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
1735 /* We must expand the rectangle we send through the rendering pipeline,
1736 * to account for the fact that we are mapping the destination region as
1737 * single-sampled when it is in fact multisampled. We must also align
1738 * it to a multiple of the multisampling pattern, because the
1739 * differences between multisampled and single-sampled surface formats
1740 * will mean that pixels are scrambled within the multisampling pattern.
1741 * TODO: what if this makes the coordinates too large?
1743 * Note: this only works if the destination surface uses the IMS layout.
1744 * If it's UMS, then we have no choice but to set up the rendering
1745 * pipeline as multisampled.
1747 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
1748 switch (dst_mt
->num_samples
) {
1750 x0
= ROUND_DOWN_TO(x0
* 2, 4);
1751 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1752 x1
= ALIGN(x1
* 2, 4);
1753 y1
= ALIGN(y1
* 2, 4);
1756 x0
= ROUND_DOWN_TO(x0
* 4, 8);
1757 y0
= ROUND_DOWN_TO(y0
* 2, 4);
1758 x1
= ALIGN(x1
* 4, 8);
1759 y1
= ALIGN(y1
* 2, 4);
1762 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
1765 wm_prog_key
.use_kill
= true;
1768 if (dst
.map_stencil_as_y_tiled
) {
1769 /* We must modify the rectangle we send through the rendering pipeline,
1770 * to account for the fact that we are mapping it as Y-tiled when it is
1771 * in fact W-tiled. Y tiles have dimensions 128x32 whereas W tiles have
1772 * dimensions 64x64. We must also align it to a multiple of the tile
1773 * size, because the differences between W and Y tiling formats will
1774 * mean that pixels are scrambled within the tile.
1776 * Note: if the destination surface configured to use IMS layout, then
1777 * the effective tile size we need to align it to is smaller, because
1778 * each pixel covers a 2x2 or a 4x2 block of samples.
1780 * TODO: what if this makes the coordinates too large?
1782 unsigned x_align
= 64, y_align
= 64;
1783 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
) {
1784 x_align
/= (dst_mt
->num_samples
== 4 ? 2 : 4);
1787 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
1788 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
1789 x1
= ALIGN(x1
, x_align
) * 2;
1790 y1
= ALIGN(y1
, y_align
) / 2;
1791 wm_prog_key
.use_kill
= true;
1796 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
1797 brw_blorp_prog_data
**prog_data
) const
1799 uint32_t prog_offset
;
1800 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1801 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1802 &prog_offset
, prog_data
)) {
1803 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
1804 GLuint program_size
;
1805 const GLuint
*program
= prog
.compile(brw
, &program_size
);
1806 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
1807 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
1808 program
, program_size
,
1809 &prog
.prog_data
, sizeof(prog
.prog_data
),
1810 &prog_offset
, prog_data
);