2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "glsl/ralloc.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
35 #include "brw_state.h"
37 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 * Helper function for handling mirror image blits.
42 * If coord0 > coord1, swap them and invert the "mirror" boolean.
45 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
47 if (coord0
> coord1
) {
57 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
58 * destination coordinates.
60 * Return true if there is still blitting to do, false if all pixels got
61 * rejected by the clip and/or scissor.
63 * For clarity, the nomenclature of this function assumes we are clipping and
64 * scissoring the X coordinate; the exact same logic applies for Y
67 * Note: this function may also be used to account for clipping of source
68 * coordinates, by swapping the roles of src and dst.
71 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
72 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
74 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
75 /* If we are going to scissor everything away, stop. */
76 if (!(fb_xmin
< fb_xmax
&&
83 /* Clip the destination rectangle, and keep track of how many pixels we
84 * clipped off of the left and right sides of it.
86 GLint pixels_clipped_left
= 0;
87 GLint pixels_clipped_right
= 0;
88 if (dst_x0
< fb_xmin
) {
89 pixels_clipped_left
= fb_xmin
- dst_x0
;
92 if (fb_xmax
< dst_x1
) {
93 pixels_clipped_right
= dst_x1
- fb_xmax
;
97 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
98 * the source coordinates, we need to flip them to account for the
102 GLint tmp
= pixels_clipped_left
;
103 pixels_clipped_left
= pixels_clipped_right
;
104 pixels_clipped_right
= tmp
;
107 /* Adjust the source rectangle to remove the pixels corresponding to those
108 * that were clipped/scissored out of the destination rectangle.
110 src_x0
+= pixels_clipped_left
* scale
;
111 src_x1
-= pixels_clipped_right
* scale
;
117 static struct intel_mipmap_tree
*
118 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
120 struct intel_mipmap_tree
*mt
= irb
->mt
;
121 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
127 brw_blorp_blit_miptrees(struct brw_context
*brw
,
128 struct intel_mipmap_tree
*src_mt
,
129 unsigned src_level
, unsigned src_layer
,
130 struct intel_mipmap_tree
*dst_mt
,
131 unsigned dst_level
, unsigned dst_layer
,
132 float src_x0
, float src_y0
,
133 float src_x1
, float src_y1
,
134 float dst_x0
, float dst_y0
,
135 float dst_x1
, float dst_y1
,
136 GLenum filter
, bool mirror_x
, bool mirror_y
)
138 /* Get ready to blit. This includes depth resolving the src and dst
139 * buffers if necessary. Note: it's not necessary to do a color resolve on
140 * the destination buffer because we use the standard render path to render
141 * to destination color buffers, and the standard render path is
144 intel_miptree_resolve_color(brw
, src_mt
);
145 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
146 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
148 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
149 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
151 _mesa_get_format_name(src_mt
->format
), src_mt
,
152 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
153 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
154 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
157 brw_blorp_blit_params
params(brw
,
158 src_mt
, src_level
, src_layer
,
159 dst_mt
, dst_level
, dst_layer
,
164 filter
, mirror_x
, mirror_y
);
165 brw_blorp_exec(brw
, ¶ms
);
167 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
171 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
172 struct intel_renderbuffer
*src_irb
,
173 struct intel_renderbuffer
*dst_irb
,
174 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
175 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
176 GLenum filter
, bool mirror_x
, bool mirror_y
)
178 /* Find source/dst miptrees */
179 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
180 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
183 brw_blorp_blit_miptrees(brw
,
184 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
185 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
186 srcX0
, srcY0
, srcX1
, srcY1
,
187 dstX0
, dstY0
, dstX1
, dstY1
,
188 filter
, mirror_x
, mirror_y
);
190 intel_renderbuffer_set_needs_downsample(dst_irb
);
194 color_formats_match(gl_format src_format
, gl_format dst_format
)
196 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
197 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
199 /* Normally, we require the formats to be equal. However, we also support
200 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
201 * (overriding alpha to 1.0 via blending).
203 return linear_src_format
== linear_dst_format
||
204 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
205 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
206 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
207 linear_dst_format
== MESA_FORMAT_XRGB8888
);
211 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
212 struct intel_renderbuffer
*dst_irb
)
214 /* Note: don't just check gl_renderbuffer::Format, because in some cases
215 * multiple gl_formats resolve to the same native type in the miptree (for
216 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
217 * between those formats.
219 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
220 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
222 return color_formats_match(src_format
, dst_format
);
226 try_blorp_blit(struct brw_context
*brw
,
227 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
228 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
229 GLenum filter
, GLbitfield buffer_bit
)
231 struct gl_context
*ctx
= &brw
->ctx
;
233 /* Sync up the state of window system buffers. We need to do this before
234 * we go looking for the buffers.
236 intel_prepare_render(brw
);
238 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
239 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
241 /* Detect if the blit needs to be mirrored */
242 bool mirror_x
= false, mirror_y
= false;
243 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
244 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
245 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
246 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
248 /* If the destination rectangle needs to be clipped or scissored, do so.
250 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
251 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
252 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
253 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
254 /* Everything got clipped/scissored away, so the blit was successful. */
258 /* If the source rectangle needs to be clipped or scissored, do so. */
259 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
260 0, read_fb
->Width
) &&
261 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
262 0, read_fb
->Height
))) {
263 /* Everything got clipped/scissored away, so the blit was successful. */
267 /* Account for the fact that in the system framebuffer, the origin is at
270 if (_mesa_is_winsys_fbo(read_fb
)) {
271 GLint tmp
= read_fb
->Height
- srcY0
;
272 srcY0
= read_fb
->Height
- srcY1
;
274 mirror_y
= !mirror_y
;
276 if (_mesa_is_winsys_fbo(draw_fb
)) {
277 GLint tmp
= draw_fb
->Height
- dstY0
;
278 dstY0
= draw_fb
->Height
- dstY1
;
280 mirror_y
= !mirror_y
;
284 struct intel_renderbuffer
*src_irb
;
285 struct intel_renderbuffer
*dst_irb
;
286 switch (buffer_bit
) {
287 case GL_COLOR_BUFFER_BIT
:
288 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
289 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
290 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
291 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
294 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
295 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
297 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
298 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
299 filter
, mirror_x
, mirror_y
);
302 case GL_DEPTH_BUFFER_BIT
:
304 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
306 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
307 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
309 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
310 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
311 filter
, mirror_x
, mirror_y
);
313 case GL_STENCIL_BUFFER_BIT
:
315 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
317 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
318 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
320 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
321 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
322 filter
, mirror_x
, mirror_y
);
332 brw_blorp_copytexsubimage(struct brw_context
*brw
,
333 struct gl_renderbuffer
*src_rb
,
334 struct gl_texture_image
*dst_image
,
336 int srcX0
, int srcY0
,
337 int dstX0
, int dstY0
,
338 int width
, int height
)
340 struct gl_context
*ctx
= &brw
->ctx
;
341 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
342 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
344 /* Sync up the state of window system buffers. We need to do this before
345 * we go looking at the src renderbuffer's miptree.
347 intel_prepare_render(brw
);
349 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
350 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
352 /* BLORP is not supported before Gen6. */
356 if (!color_formats_match(src_mt
->format
, dst_mt
->format
)) {
360 /* Source clipping shouldn't be necessary, since copytexsubimage (in
361 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
364 * Destination clipping shouldn't be necessary since the restrictions on
365 * glCopyTexSubImage prevent the user from specifying a destination rectangle
366 * that falls outside the bounds of the destination texture.
367 * See error_check_subtexture_dimensions().
370 int srcY1
= srcY0
+ height
;
371 int srcX1
= srcX0
+ width
;
372 int dstX1
= dstX0
+ width
;
373 int dstY1
= dstY0
+ height
;
375 /* Account for the fact that in the system framebuffer, the origin is at
378 bool mirror_y
= false;
379 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
380 GLint tmp
= src_rb
->Height
- srcY0
;
381 srcY0
= src_rb
->Height
- srcY1
;
386 brw_blorp_blit_miptrees(brw
,
387 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
388 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
389 srcX0
, srcY0
, srcX1
, srcY1
,
390 dstX0
, dstY0
, dstX1
, dstY1
,
391 GL_NEAREST
, false, mirror_y
);
393 /* If we're copying to a packed depth stencil texture and the source
394 * framebuffer has separate stencil, we need to also copy the stencil data
397 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
398 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
400 src_irb
= intel_renderbuffer(src_rb
);
401 src_mt
= src_irb
->mt
;
403 if (src_mt
->stencil_mt
)
404 src_mt
= src_mt
->stencil_mt
;
405 if (dst_mt
->stencil_mt
)
406 dst_mt
= dst_mt
->stencil_mt
;
408 if (src_mt
!= dst_mt
) {
409 brw_blorp_blit_miptrees(brw
,
410 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
411 dst_mt
, dst_image
->Level
,
412 dst_image
->Face
+ slice
,
413 srcX0
, srcY0
, srcX1
, srcY1
,
414 dstX0
, dstY0
, dstX1
, dstY1
,
415 GL_NEAREST
, false, mirror_y
);
424 brw_blorp_framebuffer(struct brw_context
*brw
,
425 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
426 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
427 GLbitfield mask
, GLenum filter
)
429 /* BLORP is not supported before Gen6. */
433 static GLbitfield buffer_bits
[] = {
436 GL_STENCIL_BUFFER_BIT
,
439 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
440 if ((mask
& buffer_bits
[i
]) &&
442 srcX0
, srcY0
, srcX1
, srcY1
,
443 dstX0
, dstY0
, dstX1
, dstY1
,
444 filter
, buffer_bits
[i
])) {
445 mask
&= ~buffer_bits
[i
];
454 * Enum to specify the order of arguments in a sampler message
456 enum sampler_message_arg
458 SAMPLER_MESSAGE_ARG_U_FLOAT
,
459 SAMPLER_MESSAGE_ARG_V_FLOAT
,
460 SAMPLER_MESSAGE_ARG_U_INT
,
461 SAMPLER_MESSAGE_ARG_V_INT
,
462 SAMPLER_MESSAGE_ARG_SI_INT
,
463 SAMPLER_MESSAGE_ARG_MCS_INT
,
464 SAMPLER_MESSAGE_ARG_ZERO_INT
,
468 * Generator for WM programs used in BLORP blits.
470 * The bulk of the work done by the WM program is to wrap and unwrap the
471 * coordinate transformations used by the hardware to store surfaces in
472 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
473 * sample index for a multisampled surface) to a memory offset by the
474 * following formulas:
476 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
477 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
479 * For a single-sampled surface, or for a multisampled surface using
480 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
483 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
484 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
485 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
486 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
488 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
489 * embeds the sample number into bit 1 of the X and Y coordinates:
491 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
492 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
493 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
494 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
495 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
496 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
497 * S = (Y & 0b10) | (X & 0b10) >> 1
499 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
500 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
503 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
504 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
505 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
506 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
507 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
508 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
509 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
511 * For X tiling, tile() combines together the low-order bits of the X and Y
512 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
513 * bytes wide and 8 rows high:
515 * tile(x_tiled, X, Y, S) = A
516 * where A = tile_num << 12 | offset
517 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
518 * offset = (Y' & 0b111) << 9
519 * | (X & 0b111111111)
521 * Y' = Y + S * qpitch
522 * detile(x_tiled, A) = (X, Y, S)
526 * Y' = (tile_num / tile_pitch) << 3
527 * | (A & 0b111000000000) >> 9
528 * X' = (tile_num % tile_pitch) << 9
529 * | (A & 0b111111111)
531 * (In all tiling formulas, cpp is the number of bytes occupied by a single
532 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
533 * to fill the width of the surface, and qpitch is the spacing (in rows)
534 * between array slices).
536 * For Y tiling, tile() combines together the low-order bits of the X and Y
537 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
538 * bytes wide and 32 rows high:
540 * tile(y_tiled, X, Y, S) = A
541 * where A = tile_num << 12 | offset
542 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
543 * offset = (X' & 0b1110000) << 5
544 * | (Y' & 0b11111) << 4
547 * Y' = Y + S * qpitch
548 * detile(y_tiled, A) = (X, Y, S)
552 * Y' = (tile_num / tile_pitch) << 5
553 * | (A & 0b111110000) >> 4
554 * X' = (tile_num % tile_pitch) << 7
555 * | (A & 0b111000000000) >> 5
558 * For W tiling, tile() combines together the low-order bits of the X and Y
559 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
560 * bytes wide and 64 rows high (note that W tiling is only used for stencil
561 * buffers, which always have cpp = 1 and S=0):
563 * tile(w_tiled, X, Y, S) = A
564 * where A = tile_num << 12 | offset
565 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
566 * offset = (X' & 0b111000) << 6
567 * | (Y' & 0b111100) << 3
568 * | (X' & 0b100) << 2
574 * Y' = Y + S * qpitch
575 * detile(w_tiled, A) = (X, Y, S)
576 * where X = X' / cpp = X'
577 * Y = Y' % qpitch = Y'
579 * Y' = (tile_num / tile_pitch) << 6
580 * | (A & 0b111100000) >> 3
581 * | (A & 0b1000) >> 2
583 * X' = (tile_num % tile_pitch) << 6
584 * | (A & 0b111000000000) >> 6
585 * | (A & 0b10000) >> 2
589 * Finally, for a non-tiled surface, tile() simply combines together the X and
590 * Y coordinates in the natural way:
592 * tile(untiled, X, Y, S) = A
593 * where A = Y * pitch + X'
595 * Y' = Y + S * qpitch
596 * detile(untiled, A) = (X, Y, S)
603 * (In these formulas, pitch is the number of bytes occupied by a single row
606 class brw_blorp_blit_program
609 brw_blorp_blit_program(struct brw_context
*brw
,
610 const brw_blorp_blit_prog_key
*key
);
611 ~brw_blorp_blit_program();
613 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
);
615 brw_blorp_prog_data prog_data
;
619 void alloc_push_const_regs(int base_reg
);
620 void compute_frag_coords();
621 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
622 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
623 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
624 void kill_if_outside_dst_rect();
625 void translate_dst_to_src();
626 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
627 struct brw_reg clampX0
, struct brw_reg clampY0
,
628 struct brw_reg clampX1
, struct brw_reg clampY1
);
629 void single_to_blend();
630 void manual_blend_average(unsigned num_samples
);
631 void manual_blend_bilinear(unsigned num_samples
);
632 void sample(struct brw_reg dst
);
633 void texel_fetch(struct brw_reg dst
);
635 void texture_lookup(struct brw_reg dst
, GLuint msg_type
,
636 const sampler_message_arg
*args
, int num_args
);
637 void render_target_write();
640 * Base-2 logarithm of the maximum number of samples that can be blended.
642 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
645 struct brw_context
*brw
;
646 const brw_blorp_blit_prog_key
*key
;
647 struct brw_compile func
;
649 /* Thread dispatch header */
652 /* Pixel X/Y coordinates (always in R1). */
656 struct brw_reg dst_x0
;
657 struct brw_reg dst_x1
;
658 struct brw_reg dst_y0
;
659 struct brw_reg dst_y1
;
660 /* Top right coordinates of the rectangular grid used for scaled blitting */
661 struct brw_reg rect_grid_x1
;
662 struct brw_reg rect_grid_y1
;
664 struct brw_reg multiplier
;
665 struct brw_reg offset
;
666 } x_transform
, y_transform
;
668 /* Data read from texture (4 vec16's per array element) */
669 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
671 /* Auxiliary storage for the contents of the MCS surface.
673 * Since the sampler always returns 8 registers worth of data, this is 8
674 * registers wide, even though we only use the first 2 registers of it.
676 struct brw_reg mcs_data
;
678 /* X coordinates. We have two of them so that we can perform coordinate
679 * transformations easily.
681 struct brw_reg x_coords
[2];
683 /* Y coordinates. We have two of them so that we can perform coordinate
684 * transformations easily.
686 struct brw_reg y_coords
[2];
688 /* X, Y coordinates of the pixel from which we need to fetch the specific
689 * sample. These are used for multisample scaled blitting.
691 struct brw_reg x_sample_coords
;
692 struct brw_reg y_sample_coords
;
694 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
695 struct brw_reg x_frac
;
696 struct brw_reg y_frac
;
698 /* Which element of x_coords and y_coords is currently in use.
702 /* True if, at the point in the program currently being compiled, the
703 * sample index is known to be zero.
707 /* Register storing the sample index when s_is_zero is false. */
708 struct brw_reg sample_index
;
714 /* MRF used for sampling and render target writes */
718 brw_blorp_blit_program::brw_blorp_blit_program(
719 struct brw_context
*brw
,
720 const brw_blorp_blit_prog_key
*key
)
721 : mem_ctx(ralloc_context(NULL
)),
725 brw_init_compile(brw
, &func
, mem_ctx
);
728 brw_blorp_blit_program::~brw_blorp_blit_program()
730 ralloc_free(mem_ctx
);
734 brw_blorp_blit_program::compile(struct brw_context
*brw
,
735 GLuint
*program_size
)
738 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
739 /* If the destination image is W tiled and multisampled, then the thread
740 * must be dispatched once per sample, not once per pixel. This is
741 * necessary because after conversion between W and Y tiling, there's no
742 * guarantee that all samples corresponding to a single pixel will still
745 assert(key
->persample_msaa_dispatch
);
749 /* We are blending, which means we won't have an opportunity to
750 * translate the tiling and sample count for the texture surface. So
751 * the surface state for the texture must be configured with the correct
752 * tiling and sample count.
754 assert(!key
->src_tiled_w
);
755 assert(key
->tex_samples
== key
->src_samples
);
756 assert(key
->tex_layout
== key
->src_layout
);
757 assert(key
->tex_samples
> 0);
760 if (key
->persample_msaa_dispatch
) {
761 /* It only makes sense to do persample dispatch if the render target is
762 * configured as multisampled.
764 assert(key
->rt_samples
> 0);
767 /* Make sure layout is consistent with sample count */
768 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
769 (key
->tex_samples
== 0));
770 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
771 (key
->rt_samples
== 0));
772 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
773 (key
->src_samples
== 0));
774 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
775 (key
->dst_samples
== 0));
777 /* Set up prog_data */
778 memset(&prog_data
, 0, sizeof(prog_data
));
779 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
781 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
784 compute_frag_coords();
786 /* Render target and texture hardware don't support W tiling. */
787 const bool rt_tiled_w
= false;
788 const bool tex_tiled_w
= false;
790 /* The address that data will be written to is determined by the
791 * coordinates supplied to the WM thread and the tiling and sample count of
792 * the render target, according to the formula:
794 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
796 * If the actual tiling and sample count of the destination surface are not
797 * the same as the configuration of the render target, then these
798 * coordinates are wrong and we have to adjust them to compensate for the
801 if (rt_tiled_w
!= key
->dst_tiled_w
||
802 key
->rt_samples
!= key
->dst_samples
||
803 key
->rt_layout
!= key
->dst_layout
) {
804 encode_msaa(key
->rt_samples
, key
->rt_layout
);
805 /* Now (X, Y, S) = detile(rt_tiling, offset) */
806 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
807 /* Now (X, Y, S) = detile(dst_tiling, offset) */
808 decode_msaa(key
->dst_samples
, key
->dst_layout
);
811 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
813 * That is: X, Y and S now contain the true coordinates and sample index of
814 * the data that the WM thread should output.
816 * If we need to kill pixels that are outside the destination rectangle,
817 * now is the time to do it.
821 kill_if_outside_dst_rect();
823 /* Next, apply a translation to obtain coordinates in the source image. */
824 translate_dst_to_src();
826 /* If the source image is not multisampled, then we want to fetch sample
827 * number 0, because that's the only sample there is.
829 if (key
->src_samples
== 0)
832 /* X, Y, and S are now the coordinates of the pixel in the source image
833 * that we want to texture from. Exception: if we are blending, then S is
834 * irrelevant, because we are going to fetch all samples.
836 if (key
->blend
&& !key
->blit_scaled
) {
838 /* Gen6 hardware an automatically blend using the SAMPLE message */
840 sample(texture_data
[0]);
842 /* Gen7+ hardware doesn't automaticaly blend. */
843 manual_blend_average(key
->src_samples
);
845 } else if(key
->blend
&& key
->blit_scaled
) {
846 manual_blend_bilinear(key
->src_samples
);
848 /* We aren't blending, which means we just want to fetch a single sample
849 * from the source surface. The address that we want to fetch from is
850 * related to the X, Y and S values according to the formula:
852 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
854 * If the actual tiling and sample count of the source surface are not
855 * the same as the configuration of the texture, then we need to adjust
856 * the coordinates to compensate for the difference.
858 if ((tex_tiled_w
!= key
->src_tiled_w
||
859 key
->tex_samples
!= key
->src_samples
||
860 key
->tex_layout
!= key
->src_layout
) &&
861 !key
->bilinear_filter
) {
862 encode_msaa(key
->src_samples
, key
->src_layout
);
863 /* Now (X, Y, S) = detile(src_tiling, offset) */
864 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
865 /* Now (X, Y, S) = detile(tex_tiling, offset) */
866 decode_msaa(key
->tex_samples
, key
->tex_layout
);
869 if (key
->bilinear_filter
) {
870 sample(texture_data
[0]);
873 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
875 * In other words: X, Y, and S now contain values which, when passed to
876 * the texturing unit, will cause data to be read from the correct
877 * memory location. So we can fetch the texel now.
879 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
881 texel_fetch(texture_data
[0]);
885 /* Finally, write the fetched (or blended) value to the render target and
886 * terminate the thread.
888 render_target_write();
890 if (unlikely(INTEL_DEBUG
& DEBUG_BLORP
)) {
891 printf("Native code for BLORP blit:\n");
892 brw_dump_compile(&func
, stdout
, 0, func
.next_insn_offset
);
895 return brw_get_program(&func
, program_size
);
899 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
901 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
902 #define ALLOC_REG(name, type) \
904 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
905 base_reg + CONST_LOC(name) / 32, \
906 (CONST_LOC(name) % 32) / 4), type)
908 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
909 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
910 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
911 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
912 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
913 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
914 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
915 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
916 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
917 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
923 brw_blorp_blit_program::alloc_regs()
926 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
927 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
928 prog_data
.first_curbe_grf
= reg
;
929 alloc_push_const_regs(reg
);
930 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
931 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
932 this->texture_data
[i
] =
933 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
937 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
939 for (int i
= 0; i
< 2; ++i
) {
941 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
944 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
948 if (key
->blit_scaled
&& key
->blend
) {
949 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
951 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
953 this->x_frac
= brw_vec8_grf(reg
, 0);
955 this->y_frac
= brw_vec8_grf(reg
, 0);
959 this->xy_coord_index
= 0;
961 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
963 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
965 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
968 /* Make sure we didn't run out of registers */
969 assert(reg
<= GEN7_MRF_HACK_START
);
972 this->base_mrf
= mrf
;
975 /* In the code that follows, X and Y can be used to quickly refer to the
976 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
977 * prime") to the inactive elements.
979 * S can be used to quickly refer to sample_index.
981 #define X x_coords[xy_coord_index]
982 #define Y y_coords[xy_coord_index]
983 #define Xp x_coords[!xy_coord_index]
984 #define Yp y_coords[!xy_coord_index]
985 #define S sample_index
987 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
988 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
990 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
993 * Emit code to compute the X and Y coordinates of the pixels being rendered
994 * by this WM invocation.
996 * Assuming the render target is set up for Y tiling, these (X, Y) values are
997 * related to the address offset where outputs will be written by the formula:
999 * (X, Y, S) = decode_msaa(detile(offset)).
1001 * (See brw_blorp_blit_program).
1004 brw_blorp_blit_program::compute_frag_coords()
1006 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1007 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1008 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1009 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1011 * Pixels within a subspan are laid out in this arrangement:
1015 * So, to compute the coordinates of each pixel, we need to read every 2nd
1016 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1017 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1018 * In other words, the data we want to access is R1.4<2;4,0>UW.
1020 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1021 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1023 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1024 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1026 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1027 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1028 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1031 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1032 * pixels n+2 and n+3 are in the bottom half of the subspan.
1034 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1035 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1037 /* Move the coordinates to UD registers. */
1038 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1039 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1042 if (key
->persample_msaa_dispatch
) {
1043 switch (key
->rt_samples
) {
1045 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1046 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1047 * represent sample 1, and so on.
1049 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1050 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1051 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1052 * then copy from it using vstride=1, width=4, hstride=0.
1054 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1055 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1056 /* Move to UD sample_index register. */
1057 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1058 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1062 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1063 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1064 * subspan 1 will represent sample 1, and so on. We can find the
1065 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1066 * Index") and multiplying by two (since samples are always delivered
1067 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1070 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1071 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1072 * variable with the sequence (0, 1, 2, 3), and then reading from it
1073 * using vstride=1, width=4, hstride=0.
1075 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1076 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1077 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1078 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1079 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1080 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1081 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1082 stride(t2_uw1
, 1, 4, 0));
1083 brw_ADD(&func
, offset(S
, 1),
1084 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1085 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1089 assert(!"Unrecognized sample count in "
1090 "brw_blorp_blit_program::compute_frag_coords()");
1095 /* Either the destination surface is single-sampled, or the WM will be
1096 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1097 * per pixel). In either case, it's not meaningful to compute a sample
1098 * value. Just set it to 0.
1105 * Emit code to compensate for the difference between Y and W tiling.
1107 * This code modifies the X and Y coordinates according to the formula:
1109 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1111 * (See brw_blorp_blit_program).
1113 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1114 * are booleans where true represents W tiling and false represents Y tiling.
1117 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1119 if (old_tiled_w
== new_tiled_w
)
1122 /* In the code that follows, we can safely assume that S = 0, because W
1123 * tiling formats always use IMS layout.
1127 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1129 /* Given X and Y coordinates that describe an address using Y tiling,
1130 * translate to the X and Y coordinates that describe the same address
1133 * If we break down the low order bits of X and Y, using a
1134 * single letter to represent each low-order bit:
1136 * X = A << 7 | 0bBCDEFGH
1137 * Y = J << 5 | 0bKLMNP (1)
1139 * Then we can apply the Y tiling formula to see the memory offset being
1142 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1144 * If we apply the W detiling formula to this memory location, that the
1145 * corresponding X' and Y' coordinates are:
1147 * X' = A << 6 | 0bBCDPFH (3)
1148 * Y' = J << 6 | 0bKLMNEG
1150 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1151 * we need to make the following computation:
1153 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1154 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1156 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1157 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1158 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1159 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1160 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1161 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1162 brw_OR(&func
, Xp
, t1
, t2
);
1163 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1164 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1165 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1166 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1167 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1168 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1169 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1170 brw_OR(&func
, Yp
, t1
, t2
);
1173 /* Applying the same logic as above, but in reverse, we obtain the
1176 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1177 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1179 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1180 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1181 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1182 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1183 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1184 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1185 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1186 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1188 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1189 brw_OR(&func
, Xp
, t1
, t2
);
1190 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1191 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1192 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1193 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1194 brw_OR(&func
, Yp
, t1
, t2
);
1197 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1201 * Emit code to compensate for the difference between MSAA and non-MSAA
1204 * This code modifies the X and Y coordinates according to the formula:
1206 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1208 * (See brw_blorp_blit_program).
1211 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1212 intel_msaa_layout layout
)
1214 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1216 case INTEL_MSAA_LAYOUT_NONE
:
1217 /* No translation necessary, and S should already be zero. */
1220 case INTEL_MSAA_LAYOUT_CMS
:
1221 /* We can't compensate for compressed layout since at this point in the
1222 * program we haven't read from the MCS buffer.
1224 assert(!"Bad layout in encode_msaa");
1226 case INTEL_MSAA_LAYOUT_UMS
:
1227 /* No translation necessary. */
1229 case INTEL_MSAA_LAYOUT_IMS
:
1230 switch (num_samples
) {
1232 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1233 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1234 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1236 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1238 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1239 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1241 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1243 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1244 brw_OR(&func
, Xp
, t1
, t2
);
1245 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1246 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1248 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1249 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1251 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1252 brw_OR(&func
, Yp
, t1
, t2
);
1255 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1256 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1258 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1260 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1261 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1263 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1264 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1265 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1266 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1267 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1270 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1271 brw_OR(&func
, Xp
, t1
, t2
);
1272 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1273 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1275 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1276 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1278 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1279 brw_OR(&func
, Yp
, t1
, t2
);
1286 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1290 * Emit code to compensate for the difference between MSAA and non-MSAA
1293 * This code modifies the X and Y coordinates according to the formula:
1295 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1297 * (See brw_blorp_blit_program).
1300 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1301 intel_msaa_layout layout
)
1303 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1305 case INTEL_MSAA_LAYOUT_NONE
:
1306 /* No translation necessary, and S should already be zero. */
1309 case INTEL_MSAA_LAYOUT_CMS
:
1310 /* We can't compensate for compressed layout since at this point in the
1311 * program we don't have access to the MCS buffer.
1313 assert(!"Bad layout in encode_msaa");
1315 case INTEL_MSAA_LAYOUT_UMS
:
1316 /* No translation necessary. */
1318 case INTEL_MSAA_LAYOUT_IMS
:
1320 switch (num_samples
) {
1322 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1323 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1324 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1325 * S = (Y & 0b10) | (X & 0b10) >> 1
1327 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1328 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1329 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1330 brw_OR(&func
, Xp
, t1
, t2
);
1331 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1332 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1333 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1334 brw_OR(&func
, Yp
, t1
, t2
);
1335 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1336 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1337 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1338 brw_OR(&func
, S
, t1
, t2
);
1341 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1342 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1343 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1344 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1346 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1347 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1348 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1349 brw_OR(&func
, Xp
, t1
, t2
);
1350 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1351 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1352 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1353 brw_OR(&func
, Yp
, t1
, t2
);
1354 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1355 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1356 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1357 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1358 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1359 brw_OR(&func
, S
, t1
, t2
);
1366 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1370 * Emit code that kills pixels whose X and Y coordinates are outside the
1371 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
1375 brw_blorp_blit_program::kill_if_outside_dst_rect()
1377 struct brw_reg f0
= brw_flag_reg(0, 0);
1378 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1379 struct brw_reg null32
= vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
1381 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, X
, dst_x0
);
1382 brw_CMP(&func
, null32
, BRW_CONDITIONAL_GE
, Y
, dst_y0
);
1383 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, X
, dst_x1
);
1384 brw_CMP(&func
, null32
, BRW_CONDITIONAL_L
, Y
, dst_y1
);
1386 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1387 brw_push_insn_state(&func
);
1388 brw_set_mask_control(&func
, BRW_MASK_DISABLE
);
1389 brw_AND(&func
, g1
, f0
, g1
);
1390 brw_pop_insn_state(&func
);
1393 #define X_f retype(X, BRW_REGISTER_TYPE_F)
1394 #define Y_f retype(Y, BRW_REGISTER_TYPE_F)
1395 #define Xp_f retype(Xp, BRW_REGISTER_TYPE_F)
1396 #define Yp_f retype(Yp, BRW_REGISTER_TYPE_F)
1398 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1402 brw_blorp_blit_program::translate_dst_to_src()
1404 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1405 /* Move the UD coordinates to float registers. */
1406 brw_MOV(&func
, Xp_f
, X
);
1407 brw_MOV(&func
, Yp_f
, Y
);
1408 /* Scale and offset */
1409 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1410 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1411 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1412 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1413 if (key
->blit_scaled
&& key
->blend
) {
1414 /* Translate coordinates to lay out the samples in a rectangular grid
1415 * roughly corresponding to sample locations.
1417 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1418 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1419 /* Adjust coordinates so that integers represent pixel centers rather
1422 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1423 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1425 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1426 * texels on texture edges.
1428 clamp_tex_coords(X_f
, Y_f
,
1429 brw_imm_f(0.0), brw_imm_f(0.0),
1430 rect_grid_x1
, rect_grid_y1
);
1432 /* Store the fractional parts to be used as bilinear interpolation
1435 brw_FRC(&func
, x_frac
, X_f
);
1436 brw_FRC(&func
, y_frac
, Y_f
);
1438 /* Round the float coordinates down to nearest integer */
1439 brw_RNDD(&func
, Xp_f
, X_f
);
1440 brw_RNDD(&func
, Yp_f
, Y_f
);
1441 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1442 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1444 } else if (!key
->bilinear_filter
) {
1445 /* Round the float coordinates down to nearest integer by moving to
1448 brw_MOV(&func
, Xp
, X_f
);
1449 brw_MOV(&func
, Yp
, Y_f
);
1452 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1456 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1457 struct brw_reg regY
,
1458 struct brw_reg clampX0
,
1459 struct brw_reg clampY0
,
1460 struct brw_reg clampX1
,
1461 struct brw_reg clampY1
)
1463 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regX
, clampX0
);
1464 brw_MOV(&func
, regX
, clampX0
);
1465 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1467 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regX
, clampX1
);
1468 brw_MOV(&func
, regX
, clampX1
);
1469 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1471 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
, regY
, clampY0
);
1472 brw_MOV(&func
, regY
, clampY0
);
1473 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1475 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_G
, regY
, clampY1
);
1476 brw_MOV(&func
, regY
, clampY1
);
1477 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1485 * Emit code to transform the X and Y coordinates as needed for blending
1486 * together the different samples in an MSAA texture.
1489 brw_blorp_blit_program::single_to_blend()
1491 /* When looking up samples in an MSAA texture using the SAMPLE message,
1492 * Gen6 requires the texture coordinates to be odd integers (so that they
1493 * correspond to the center of a 2x2 block representing the four samples
1494 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1495 * each by 2 and then add 1.
1497 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1498 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1499 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1500 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1501 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1502 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1508 * Count the number of trailing 1 bits in the given value. For example:
1510 * count_trailing_one_bits(0) == 0
1511 * count_trailing_one_bits(7) == 3
1512 * count_trailing_one_bits(11) == 2
1514 inline int count_trailing_one_bits(unsigned value
)
1516 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1517 return __builtin_ctz(~value
);
1519 return _mesa_bitcount(value
& ~(value
+ 1));
1525 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1527 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1530 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1532 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1534 * This ensures that when all samples have the same value, no numerical
1535 * precision is lost, since each addition operation always adds two equal
1536 * values, and summing two equal floating point values does not lose
1539 * We perform this computation by treating the texture_data array as a
1540 * stack and performing the following operations:
1542 * - push sample 0 onto stack
1543 * - push sample 1 onto stack
1544 * - add top two stack entries
1545 * - push sample 2 onto stack
1546 * - push sample 3 onto stack
1547 * - add top two stack entries
1548 * - add top two stack entries
1549 * - divide top stack entry by 4
1551 * Note that after pushing sample i onto the stack, the number of add
1552 * operations we do is equal to the number of trailing 1 bits in i. This
1553 * works provided the total number of samples is a power of two, which it
1554 * always is for i965.
1556 * For integer formats, we replace the add operations with average
1557 * operations and skip the final division.
1559 typedef struct brw_instruction
*(*brw_op2_ptr
)(struct brw_compile
*,
1563 brw_op2_ptr combine_op
=
1564 key
->texture_data_type
== BRW_REGISTER_TYPE_F
? brw_ADD
: brw_AVG
;
1565 unsigned stack_depth
= 0;
1566 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1567 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1569 /* Push sample i onto the stack */
1570 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1575 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1577 texel_fetch(texture_data
[stack_depth
++]);
1579 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1580 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1581 * suggests an optimization:
1583 * "A simple optimization with probable large return in
1584 * performance is to compare the MCS value to zero (indicating
1585 * all samples are on sample slice 0), and sample only from
1586 * sample slice 0 using ld2dss if MCS is zero."
1588 * Note that in the case where the MCS value is zero, sampling from
1589 * sample slice 0 using ld2dss and sampling from sample 0 using
1590 * ld2dms are equivalent (since all samples are on sample slice 0).
1591 * Since we have already sampled from sample 0, all we need to do is
1592 * skip the remaining fetches and averaging if MCS is zero.
1594 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1595 mcs_data
, brw_imm_ud(0));
1596 brw_IF(&func
, BRW_EXECUTE_16
);
1599 /* Do count_trailing_one_bits(i) times */
1600 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1601 assert(stack_depth
>= 2);
1604 /* TODO: should use a smaller loop bound for non_RGBA formats */
1605 for (int k
= 0; k
< 4; ++k
) {
1606 combine_op(&func
, offset(texture_data
[stack_depth
- 1], 2*k
),
1607 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1608 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1613 /* We should have just 1 sample on the stack now. */
1614 assert(stack_depth
== 1);
1616 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1617 /* Scale the result down by a factor of num_samples */
1618 /* TODO: should use a smaller loop bound for non-RGBA formats */
1619 for (int j
= 0; j
< 4; ++j
) {
1620 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1621 offset(vec8(texture_data
[0]), 2*j
),
1622 brw_imm_f(1.0/num_samples
));
1626 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1631 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1633 /* We do this computation by performing the following operations:
1635 * In case of 4x, 8x MSAA:
1636 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1637 * which are later used for interpolation
1638 * - linearly interpolate samples a and b in X
1639 * - linearly interpolate samples c and d in X
1640 * - linearly interpolate the results of last two operations in Y
1642 * result = lrp(lrp(a + b) + lrp(c + d))
1644 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1645 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1646 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1647 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1649 for (unsigned i
= 0; i
< 4; ++i
) {
1650 assert(i
< ARRAY_SIZE(texture_data
));
1653 /* Compute pixel coordinates */
1654 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1655 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1656 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1657 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1658 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1659 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1661 /* The MCS value we fetch has to match up with the pixel that we're
1662 * sampling from. Since we sample from different pixels in each
1663 * iteration of this "for" loop, the call to mcs_fetch() should be
1664 * here inside the loop after computing the pixel coordinates.
1666 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1669 /* Compute sample index and map the sample index to a sample number.
1670 * Sample index layout shows the numbering of slots in a rectangular
1671 * grid of samples with in a pixel. Sample number layout shows the
1672 * rectangular grid of samples roughly corresponding to the real sample
1673 * locations with in a pixel.
1674 * In case of 4x MSAA, layout of sample indices matches the layout of
1682 * In case of 8x MSAA the two layouts don't match.
1683 * sample index layout : --------- sample number layout : ---------
1684 * | 0 | 1 | | 5 | 2 |
1685 * --------- ---------
1686 * | 2 | 3 | | 4 | 6 |
1687 * --------- ---------
1688 * | 4 | 5 | | 0 | 3 |
1689 * --------- ---------
1690 * | 6 | 7 | | 7 | 1 |
1691 * --------- ---------
1693 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1694 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1695 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1696 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1697 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1698 brw_MOV(&func
, vec16(S
), t1_f
);
1700 if (num_samples
== 8) {
1701 /* Map the sample index to a sample number */
1702 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1704 brw_IF(&func
, BRW_EXECUTE_16
);
1706 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1707 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1709 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1710 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1711 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1713 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1714 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1715 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1717 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1718 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1722 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1723 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1725 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1726 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1727 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1729 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1730 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1731 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1733 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1734 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1737 brw_MOV(&func
, vec16(S
), t2
);
1739 texel_fetch(texture_data
[i
]);
1742 #define SAMPLE(x, y) offset(texture_data[x], y)
1743 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1744 for (int index
= 3; index
> 0; ) {
1745 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1746 * Counter value of 8 in 'for' loop below is used to interpolate all
1747 * the color components.
1749 for (int k
= 0; k
< 8; ++k
)
1751 vec8(SAMPLE(index
- 1, k
)),
1752 offset(x_frac
, k
& 1),
1754 SAMPLE(index
- 1, k
));
1757 for (int k
= 0; k
< 8; ++k
)
1760 offset(y_frac
, k
& 1),
1762 vec8(SAMPLE(0, k
)));
1763 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1768 * Emit code to look up a value in the texture using the SAMPLE message (which
1769 * does blending of MSAA surfaces).
1772 brw_blorp_blit_program::sample(struct brw_reg dst
)
1774 static const sampler_message_arg args
[2] = {
1775 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1776 SAMPLER_MESSAGE_ARG_V_FLOAT
1779 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE
, args
,
1784 * Emit code to look up a value in the texture using the SAMPLE_LD message
1785 * (which does a simple texel fetch).
1788 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1790 static const sampler_message_arg gen6_args
[5] = {
1791 SAMPLER_MESSAGE_ARG_U_INT
,
1792 SAMPLER_MESSAGE_ARG_V_INT
,
1793 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1794 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1795 SAMPLER_MESSAGE_ARG_SI_INT
1797 static const sampler_message_arg gen7_ld_args
[3] = {
1798 SAMPLER_MESSAGE_ARG_U_INT
,
1799 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1800 SAMPLER_MESSAGE_ARG_V_INT
1802 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1803 SAMPLER_MESSAGE_ARG_SI_INT
,
1804 SAMPLER_MESSAGE_ARG_U_INT
,
1805 SAMPLER_MESSAGE_ARG_V_INT
1807 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1808 SAMPLER_MESSAGE_ARG_SI_INT
,
1809 SAMPLER_MESSAGE_ARG_MCS_INT
,
1810 SAMPLER_MESSAGE_ARG_U_INT
,
1811 SAMPLER_MESSAGE_ARG_V_INT
1816 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen6_args
,
1820 switch (key
->tex_layout
) {
1821 case INTEL_MSAA_LAYOUT_IMS
:
1822 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1825 * If this field is MSFMT_DEPTH_STENCIL
1826 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1827 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1829 * So fall through to emit the same message as we use for
1830 * INTEL_MSAA_LAYOUT_CMS.
1832 case INTEL_MSAA_LAYOUT_CMS
:
1833 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
,
1834 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1836 case INTEL_MSAA_LAYOUT_UMS
:
1837 texture_lookup(dst
, GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
,
1838 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1840 case INTEL_MSAA_LAYOUT_NONE
:
1842 texture_lookup(dst
, GEN5_SAMPLER_MESSAGE_SAMPLE_LD
, gen7_ld_args
,
1843 ARRAY_SIZE(gen7_ld_args
));
1848 assert(!"Should not get here.");
1854 brw_blorp_blit_program::mcs_fetch()
1856 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1857 SAMPLER_MESSAGE_ARG_U_INT
,
1858 SAMPLER_MESSAGE_ARG_V_INT
1860 texture_lookup(vec16(mcs_data
), GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
,
1861 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1865 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1867 const sampler_message_arg
*args
,
1870 struct brw_reg mrf
=
1871 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1872 for (int arg
= 0; arg
< num_args
; ++arg
) {
1873 switch (args
[arg
]) {
1874 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1875 if (key
->bilinear_filter
)
1876 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1877 retype(X
, BRW_REGISTER_TYPE_F
));
1879 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1881 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1882 if (key
->bilinear_filter
)
1883 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1884 retype(Y
, BRW_REGISTER_TYPE_F
));
1886 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1888 case SAMPLER_MESSAGE_ARG_U_INT
:
1889 brw_MOV(&func
, mrf
, X
);
1891 case SAMPLER_MESSAGE_ARG_V_INT
:
1892 brw_MOV(&func
, mrf
, Y
);
1894 case SAMPLER_MESSAGE_ARG_SI_INT
:
1895 /* Note: on Gen7, this code may be reached with s_is_zero==true
1896 * because in Gen7's ld2dss message, the sample index is the first
1897 * argument. When this happens, we need to move a 0 into the
1898 * appropriate message register.
1901 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1903 brw_MOV(&func
, mrf
, S
);
1905 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1906 switch (key
->tex_layout
) {
1907 case INTEL_MSAA_LAYOUT_CMS
:
1908 brw_MOV(&func
, mrf
, mcs_data
);
1910 case INTEL_MSAA_LAYOUT_IMS
:
1911 /* When sampling from an IMS surface, MCS data is not relevant,
1912 * and the hardware ignores it. So don't bother populating it.
1916 /* We shouldn't be trying to send MCS data with any other
1919 assert (!"Unsupported layout for MCS data");
1923 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1924 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1931 retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1932 base_mrf
/* msg_reg_nr */,
1933 brw_message_reg(base_mrf
) /* src0 */,
1934 BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX
,
1937 8 /* response_length. TODO: should be smaller for non-RGBA formats? */,
1938 mrf
.nr
- base_mrf
/* msg_length */,
1939 0 /* header_present */,
1940 BRW_SAMPLER_SIMD_MODE_SIMD16
,
1941 BRW_SAMPLER_RETURN_FORMAT_FLOAT32
);
1949 #undef SWAP_XY_AND_XPYP
1952 brw_blorp_blit_program::render_target_write()
1954 struct brw_reg mrf_rt_write
=
1955 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1958 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1959 * so that the render target knows which pixels we killed.
1961 bool use_header
= key
->use_kill
;
1963 /* Copy R0/1 to MRF */
1964 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1965 retype(R0
, BRW_REGISTER_TYPE_UD
));
1969 /* Copy texture data to MRFs */
1970 for (int i
= 0; i
< 4; ++i
) {
1971 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1972 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1973 offset(vec8(texture_data
[0]), 2*i
));
1977 /* Now write to the render target and terminate the thread */
1979 16 /* dispatch_width */,
1980 base_mrf
/* msg_reg_nr */,
1981 mrf_rt_write
/* src0 */,
1982 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
,
1983 BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX
,
1984 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1985 0 /* response_length */,
1992 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1993 GLfloat dst0
, GLfloat dst1
,
1996 float scale
= (src1
- src0
) / (dst1
- dst0
);
1998 /* When not mirroring a coordinate (say, X), we need:
1999 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
2001 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
2003 * blorp program uses "round toward zero" to convert the
2004 * transformed floating point coordinates to integer coordinates,
2005 * whereas the behaviour we actually want is "round to nearest",
2006 * so 0.5 provides the necessary correction.
2009 offset
= src0
+ (-dst0
+ 0.5) * scale
;
2011 /* When mirroring X we need:
2012 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2014 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2016 multiplier
= -scale
;
2017 offset
= src0
+ (dst1
- 0.5) * scale
;
2023 * Determine which MSAA layout the GPU pipeline should be configured for,
2024 * based on the chip generation, the number of samples, and the true layout of
2025 * the image in memory.
2027 inline intel_msaa_layout
2028 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2029 intel_msaa_layout true_layout
)
2031 if (num_samples
<= 1) {
2032 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2033 * format buffers, by transforming coordinates appropriately.
2035 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2036 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2037 return INTEL_MSAA_LAYOUT_NONE
;
2039 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2042 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2043 if (brw
->gen
== 6) {
2044 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2051 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2052 struct intel_mipmap_tree
*src_mt
,
2053 unsigned src_level
, unsigned src_layer
,
2054 struct intel_mipmap_tree
*dst_mt
,
2055 unsigned dst_level
, unsigned dst_layer
,
2056 GLfloat src_x0
, GLfloat src_y0
,
2057 GLfloat src_x1
, GLfloat src_y1
,
2058 GLfloat dst_x0
, GLfloat dst_y0
,
2059 GLfloat dst_x1
, GLfloat dst_y1
,
2061 bool mirror_x
, bool mirror_y
)
2063 struct gl_context
*ctx
= &brw
->ctx
;
2064 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2066 src
.set(brw
, src_mt
, src_level
, src_layer
);
2067 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
);
2069 /* Even though we do multisample resolves at the time of the blit, OpenGL
2070 * specification defines them as if they happen at the time of rendering,
2071 * which means that the type of averaging we do during the resolve should
2072 * only depend on the source format; the destination format should be
2073 * ignored. But, specification doesn't seem to be strict about it.
2075 * It has been observed that mulitisample resolves produce slightly better
2076 * looking images when averaging is done using destination format. NVIDIA's
2077 * proprietary OpenGL driver also follow this approach. So, we choose to
2078 * follow it in our driver.
2080 * Following if-else block takes care of this exception made for
2081 * multisampled resolves.
2083 if (src
.num_samples
> 1)
2084 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2086 dst
.brw_surfaceformat
= src
.brw_surfaceformat
;
2089 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2091 /* texture_data_type indicates the register type that should be used to
2092 * manipulate texture data.
2094 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2095 case GL_UNSIGNED_NORMALIZED
:
2096 case GL_SIGNED_NORMALIZED
:
2098 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2100 case GL_UNSIGNED_INT
:
2101 if (src_mt
->format
== MESA_FORMAT_S8
) {
2102 /* We process stencil as though it's an unsigned normalized color */
2103 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2105 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2109 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2112 assert(!"Unrecognized blorp format");
2117 /* Gen7's rendering hardware only supports the IMS layout for depth and
2118 * stencil render targets. Blorp always maps its destination surface as
2119 * a color render target (even if it's actually a depth or stencil
2120 * buffer). So if the destination is IMS, we'll have to map it as a
2121 * single-sampled texture and interleave the samples ourselves.
2123 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2124 dst
.num_samples
= 0;
2127 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2128 /* If the destination surface is a W-tiled multisampled stencil buffer
2129 * that we're mapping as Y tiled, then we need to arrange for the WM
2130 * program to run once per sample rather than once per pixel, because
2131 * the memory layout of related samples doesn't match between W and Y
2134 wm_prog_key
.persample_msaa_dispatch
= true;
2137 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2138 /* We are blitting from a multisample buffer to a multisample buffer, so
2139 * we must preserve samples within a pixel. This means we have to
2140 * arrange for the WM program to run once per sample rather than once
2143 wm_prog_key
.persample_msaa_dispatch
= true;
2146 /* Scaled blitting or not. */
2147 wm_prog_key
.blit_scaled
=
2148 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2149 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2151 /* Scaling factors used for bilinear filtering in multisample scaled
2154 wm_prog_key
.x_scale
= 2.0;
2155 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2157 if (filter
== GL_LINEAR
)
2158 wm_prog_key
.bilinear_filter
= true;
2160 /* The render path must be configured to use the same number of samples as
2161 * the destination buffer.
2163 num_samples
= dst
.num_samples
;
2165 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2166 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2167 base_format
!= GL_STENCIL_INDEX
&&
2168 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2169 /* We are downsampling a color buffer, so blend. */
2170 wm_prog_key
.blend
= true;
2173 /* src_samples and dst_samples are the true sample counts */
2174 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2175 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2177 /* tex_samples and rt_samples are the sample counts that are set up in
2180 wm_prog_key
.tex_samples
= src
.num_samples
;
2181 wm_prog_key
.rt_samples
= dst
.num_samples
;
2183 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2184 * use to access the source and destination surfaces.
2186 wm_prog_key
.tex_layout
=
2187 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2188 wm_prog_key
.rt_layout
=
2189 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2191 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2194 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2195 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2197 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2198 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2199 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2200 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2201 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2202 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2203 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2204 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2206 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2207 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2209 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2210 /* We must expand the rectangle we send through the rendering pipeline,
2211 * to account for the fact that we are mapping the destination region as
2212 * single-sampled when it is in fact multisampled. We must also align
2213 * it to a multiple of the multisampling pattern, because the
2214 * differences between multisampled and single-sampled surface formats
2215 * will mean that pixels are scrambled within the multisampling pattern.
2216 * TODO: what if this makes the coordinates too large?
2218 * Note: this only works if the destination surface uses the IMS layout.
2219 * If it's UMS, then we have no choice but to set up the rendering
2220 * pipeline as multisampled.
2222 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2223 switch (dst_mt
->num_samples
) {
2225 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2226 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2227 x1
= ALIGN(x1
* 2, 4);
2228 y1
= ALIGN(y1
* 2, 4);
2231 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2232 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2233 x1
= ALIGN(x1
* 4, 8);
2234 y1
= ALIGN(y1
* 2, 4);
2237 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2240 wm_prog_key
.use_kill
= true;
2243 if (dst
.map_stencil_as_y_tiled
) {
2244 /* We must modify the rectangle we send through the rendering pipeline
2245 * (and the size and x/y offset of the destination surface), to account
2246 * for the fact that we are mapping it as Y-tiled when it is in fact
2249 * Both Y tiling and W tiling can be understood as organizations of
2250 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2251 * is different, but the layout of the 32-byte sub-tiles within the 4k
2252 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2253 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2254 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2256 * Therefore, to account for the layout differences within the 32-byte
2257 * sub-tiles, we must expand the rectangle so the X coordinates of its
2258 * edges are multiples of 8 (the W sub-tile width), and its Y
2259 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2260 * Then we need to scale the X and Y coordinates of the rectangle to
2261 * account for the differences in aspect ratio between the Y and W
2262 * sub-tiles. We need to modify the layer width and height similarly.
2264 * A correction needs to be applied when MSAA is in use: since
2265 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2266 * we need to align the Y coordinates to multiples of 8, so that when
2267 * they are divided by two they are still multiples of 4.
2269 * Note: Since the x/y offset of the surface will be applied using the
2270 * SURFACE_STATE command packet, it will be invisible to the swizzling
2271 * code in the shader; therefore it needs to be in a multiple of the
2272 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2273 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2274 * buffer), and the miplevel alignment used for stencil buffers is 8
2275 * pixels horizontally and either 4 or 8 pixels vertically (see
2276 * intel_horizontal_texture_alignment_unit() and
2277 * intel_vertical_texture_alignment_unit()).
2279 * Note: Also, since the SURFACE_STATE command packet can only apply
2280 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2281 * vertically, it is important that the offsets will be multiples of
2282 * these sizes after they are converted into Y-tiled coordinates.
2283 * Fortunately they will be, since we know from above that the offsets
2284 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2285 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2287 * TODO: what if this makes the coordinates (or the texture size) too
2290 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2291 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2292 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2293 x1
= ALIGN(x1
, x_align
) * 2;
2294 y1
= ALIGN(y1
, y_align
) / 2;
2295 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2296 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2299 wm_prog_key
.use_kill
= true;
2302 if (src
.map_stencil_as_y_tiled
) {
2303 /* We must modify the size and x/y offset of the source surface to
2304 * account for the fact that we are mapping it as Y-tiled when it is in
2307 * See the comments above concerning x/y offset alignment for the
2308 * destination surface.
2310 * TODO: what if this makes the texture size too large?
2312 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2313 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2314 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2321 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2322 brw_blorp_prog_data
**prog_data
) const
2324 uint32_t prog_offset
= 0;
2325 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2326 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2327 &prog_offset
, prog_data
)) {
2328 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2329 GLuint program_size
;
2330 const GLuint
*program
= prog
.compile(brw
, &program_size
);
2331 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2332 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2333 program
, program_size
,
2334 &prog
.prog_data
, sizeof(prog
.prog_data
),
2335 &prog_offset
, prog_data
);