2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 * Helper function for handling mirror image blits.
40 * If coord0 > coord1, swap them and invert the "mirror" boolean.
43 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
45 if (coord0
> coord1
) {
55 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
56 * destination coordinates.
58 * Return true if there is still blitting to do, false if all pixels got
59 * rejected by the clip and/or scissor.
61 * For clarity, the nomenclature of this function assumes we are clipping and
62 * scissoring the X coordinate; the exact same logic applies for Y
65 * Note: this function may also be used to account for clipping of source
66 * coordinates, by swapping the roles of src and dst.
69 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
70 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
72 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
73 /* If we are going to scissor everything away, stop. */
74 if (!(fb_xmin
< fb_xmax
&&
81 /* Clip the destination rectangle, and keep track of how many pixels we
82 * clipped off of the left and right sides of it.
84 GLint pixels_clipped_left
= 0;
85 GLint pixels_clipped_right
= 0;
86 if (dst_x0
< fb_xmin
) {
87 pixels_clipped_left
= fb_xmin
- dst_x0
;
90 if (fb_xmax
< dst_x1
) {
91 pixels_clipped_right
= dst_x1
- fb_xmax
;
95 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
96 * the source coordinates, we need to flip them to account for the
100 GLint tmp
= pixels_clipped_left
;
101 pixels_clipped_left
= pixels_clipped_right
;
102 pixels_clipped_right
= tmp
;
105 /* Adjust the source rectangle to remove the pixels corresponding to those
106 * that were clipped/scissored out of the destination rectangle.
108 src_x0
+= pixels_clipped_left
* scale
;
109 src_x1
-= pixels_clipped_right
* scale
;
115 static struct intel_mipmap_tree
*
116 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
118 struct intel_mipmap_tree
*mt
= irb
->mt
;
119 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
126 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
127 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
128 * the physical layer holding sample 0. So, for example, if
129 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
133 brw_blorp_blit_miptrees(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*src_mt
,
135 unsigned src_level
, unsigned src_layer
,
136 struct intel_mipmap_tree
*dst_mt
,
137 unsigned dst_level
, unsigned dst_layer
,
138 float src_x0
, float src_y0
,
139 float src_x1
, float src_y1
,
140 float dst_x0
, float dst_y0
,
141 float dst_x1
, float dst_y1
,
142 GLenum filter
, bool mirror_x
, bool mirror_y
)
144 /* Get ready to blit. This includes depth resolving the src and dst
145 * buffers if necessary. Note: it's not necessary to do a color resolve on
146 * the destination buffer because we use the standard render path to render
147 * to destination color buffers, and the standard render path is
150 intel_miptree_resolve_color(brw
, src_mt
);
151 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
152 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
154 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
155 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
157 _mesa_get_format_name(src_mt
->format
), src_mt
,
158 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
159 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
160 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
163 brw_blorp_blit_params
params(brw
,
164 src_mt
, src_level
, src_layer
,
165 dst_mt
, dst_level
, dst_layer
,
170 filter
, mirror_x
, mirror_y
);
171 brw_blorp_exec(brw
, ¶ms
);
173 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
177 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
178 struct intel_renderbuffer
*src_irb
,
179 struct intel_renderbuffer
*dst_irb
,
180 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
181 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
182 GLenum filter
, bool mirror_x
, bool mirror_y
)
184 /* Find source/dst miptrees */
185 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
186 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
189 brw_blorp_blit_miptrees(brw
,
190 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
191 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
192 srcX0
, srcY0
, srcX1
, srcY1
,
193 dstX0
, dstY0
, dstX1
, dstY1
,
194 filter
, mirror_x
, mirror_y
);
196 intel_renderbuffer_set_needs_downsample(dst_irb
);
200 color_formats_match(gl_format src_format
, gl_format dst_format
)
202 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
203 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
205 /* Normally, we require the formats to be equal. However, we also support
206 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
207 * (overriding alpha to 1.0 via blending).
209 return linear_src_format
== linear_dst_format
||
210 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
211 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
212 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
213 linear_dst_format
== MESA_FORMAT_XRGB8888
);
217 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
218 struct intel_renderbuffer
*dst_irb
)
220 /* Note: don't just check gl_renderbuffer::Format, because in some cases
221 * multiple gl_formats resolve to the same native type in the miptree (for
222 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
223 * between those formats.
225 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
226 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
228 return color_formats_match(src_format
, dst_format
);
232 try_blorp_blit(struct brw_context
*brw
,
233 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
234 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
235 GLenum filter
, GLbitfield buffer_bit
)
237 struct gl_context
*ctx
= &brw
->ctx
;
239 /* Sync up the state of window system buffers. We need to do this before
240 * we go looking for the buffers.
242 intel_prepare_render(brw
);
244 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
245 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
247 /* Detect if the blit needs to be mirrored */
248 bool mirror_x
= false, mirror_y
= false;
249 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
250 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
251 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
252 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
254 /* If the destination rectangle needs to be clipped or scissored, do so.
256 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
257 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
258 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
259 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
260 /* Everything got clipped/scissored away, so the blit was successful. */
264 /* If the source rectangle needs to be clipped or scissored, do so. */
265 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
266 0, read_fb
->Width
) &&
267 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
268 0, read_fb
->Height
))) {
269 /* Everything got clipped/scissored away, so the blit was successful. */
273 /* Account for the fact that in the system framebuffer, the origin is at
276 if (_mesa_is_winsys_fbo(read_fb
)) {
277 GLint tmp
= read_fb
->Height
- srcY0
;
278 srcY0
= read_fb
->Height
- srcY1
;
280 mirror_y
= !mirror_y
;
282 if (_mesa_is_winsys_fbo(draw_fb
)) {
283 GLint tmp
= draw_fb
->Height
- dstY0
;
284 dstY0
= draw_fb
->Height
- dstY1
;
286 mirror_y
= !mirror_y
;
290 struct intel_renderbuffer
*src_irb
;
291 struct intel_renderbuffer
*dst_irb
;
292 switch (buffer_bit
) {
293 case GL_COLOR_BUFFER_BIT
:
294 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
295 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
296 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
297 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
300 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
301 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
303 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
304 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
305 filter
, mirror_x
, mirror_y
);
308 case GL_DEPTH_BUFFER_BIT
:
310 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
312 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
313 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
315 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
316 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
317 filter
, mirror_x
, mirror_y
);
319 case GL_STENCIL_BUFFER_BIT
:
321 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
323 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
324 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
326 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
327 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
328 filter
, mirror_x
, mirror_y
);
338 brw_blorp_copytexsubimage(struct brw_context
*brw
,
339 struct gl_renderbuffer
*src_rb
,
340 struct gl_texture_image
*dst_image
,
342 int srcX0
, int srcY0
,
343 int dstX0
, int dstY0
,
344 int width
, int height
)
346 struct gl_context
*ctx
= &brw
->ctx
;
347 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
348 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
350 /* Sync up the state of window system buffers. We need to do this before
351 * we go looking at the src renderbuffer's miptree.
353 intel_prepare_render(brw
);
355 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
356 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
358 /* BLORP is not supported before Gen6. */
359 if (brw
->gen
< 6 || brw
->gen
>= 8)
362 if (_mesa_get_format_base_format(src_mt
->format
) !=
363 _mesa_get_format_base_format(dst_mt
->format
)) {
367 /* We can't handle format conversions between Z24 and other formats since
368 * we have to lie about the surface format. See the comments in
369 * brw_blorp_surface_info::set().
371 if ((src_mt
->format
== MESA_FORMAT_X8_Z24
) !=
372 (dst_mt
->format
== MESA_FORMAT_X8_Z24
)) {
376 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
379 /* Source clipping shouldn't be necessary, since copytexsubimage (in
380 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
383 * Destination clipping shouldn't be necessary since the restrictions on
384 * glCopyTexSubImage prevent the user from specifying a destination rectangle
385 * that falls outside the bounds of the destination texture.
386 * See error_check_subtexture_dimensions().
389 int srcY1
= srcY0
+ height
;
390 int srcX1
= srcX0
+ width
;
391 int dstX1
= dstX0
+ width
;
392 int dstY1
= dstY0
+ height
;
394 /* Account for the fact that in the system framebuffer, the origin is at
397 bool mirror_y
= false;
398 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
399 GLint tmp
= src_rb
->Height
- srcY0
;
400 srcY0
= src_rb
->Height
- srcY1
;
405 brw_blorp_blit_miptrees(brw
,
406 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
407 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
408 srcX0
, srcY0
, srcX1
, srcY1
,
409 dstX0
, dstY0
, dstX1
, dstY1
,
410 GL_NEAREST
, false, mirror_y
);
412 /* If we're copying to a packed depth stencil texture and the source
413 * framebuffer has separate stencil, we need to also copy the stencil data
416 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
417 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
419 src_irb
= intel_renderbuffer(src_rb
);
420 src_mt
= src_irb
->mt
;
422 if (src_mt
->stencil_mt
)
423 src_mt
= src_mt
->stencil_mt
;
424 if (dst_mt
->stencil_mt
)
425 dst_mt
= dst_mt
->stencil_mt
;
427 if (src_mt
!= dst_mt
) {
428 brw_blorp_blit_miptrees(brw
,
429 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
430 dst_mt
, dst_image
->Level
,
431 dst_image
->Face
+ slice
,
432 srcX0
, srcY0
, srcX1
, srcY1
,
433 dstX0
, dstY0
, dstX1
, dstY1
,
434 GL_NEAREST
, false, mirror_y
);
443 brw_blorp_framebuffer(struct brw_context
*brw
,
444 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
445 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
446 GLbitfield mask
, GLenum filter
)
448 /* BLORP is not supported before Gen6. */
449 if (brw
->gen
< 6 || brw
->gen
>= 8)
452 static GLbitfield buffer_bits
[] = {
455 GL_STENCIL_BUFFER_BIT
,
458 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
459 if ((mask
& buffer_bits
[i
]) &&
461 srcX0
, srcY0
, srcX1
, srcY1
,
462 dstX0
, dstY0
, dstX1
, dstY1
,
463 filter
, buffer_bits
[i
])) {
464 mask
&= ~buffer_bits
[i
];
473 * Enum to specify the order of arguments in a sampler message
475 enum sampler_message_arg
477 SAMPLER_MESSAGE_ARG_U_FLOAT
,
478 SAMPLER_MESSAGE_ARG_V_FLOAT
,
479 SAMPLER_MESSAGE_ARG_U_INT
,
480 SAMPLER_MESSAGE_ARG_V_INT
,
481 SAMPLER_MESSAGE_ARG_SI_INT
,
482 SAMPLER_MESSAGE_ARG_MCS_INT
,
483 SAMPLER_MESSAGE_ARG_ZERO_INT
,
487 * Generator for WM programs used in BLORP blits.
489 * The bulk of the work done by the WM program is to wrap and unwrap the
490 * coordinate transformations used by the hardware to store surfaces in
491 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
492 * sample index for a multisampled surface) to a memory offset by the
493 * following formulas:
495 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
496 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
498 * For a single-sampled surface, or for a multisampled surface using
499 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
502 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
503 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
504 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
505 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
507 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
508 * embeds the sample number into bit 1 of the X and Y coordinates:
510 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
511 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
512 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
513 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
514 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
515 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
516 * S = (Y & 0b10) | (X & 0b10) >> 1
518 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
519 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
522 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
523 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
524 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
525 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
526 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
527 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
528 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
530 * For X tiling, tile() combines together the low-order bits of the X and Y
531 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
532 * bytes wide and 8 rows high:
534 * tile(x_tiled, X, Y, S) = A
535 * where A = tile_num << 12 | offset
536 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
537 * offset = (Y' & 0b111) << 9
538 * | (X & 0b111111111)
540 * Y' = Y + S * qpitch
541 * detile(x_tiled, A) = (X, Y, S)
545 * Y' = (tile_num / tile_pitch) << 3
546 * | (A & 0b111000000000) >> 9
547 * X' = (tile_num % tile_pitch) << 9
548 * | (A & 0b111111111)
550 * (In all tiling formulas, cpp is the number of bytes occupied by a single
551 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
552 * to fill the width of the surface, and qpitch is the spacing (in rows)
553 * between array slices).
555 * For Y tiling, tile() combines together the low-order bits of the X and Y
556 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
557 * bytes wide and 32 rows high:
559 * tile(y_tiled, X, Y, S) = A
560 * where A = tile_num << 12 | offset
561 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
562 * offset = (X' & 0b1110000) << 5
563 * | (Y' & 0b11111) << 4
566 * Y' = Y + S * qpitch
567 * detile(y_tiled, A) = (X, Y, S)
571 * Y' = (tile_num / tile_pitch) << 5
572 * | (A & 0b111110000) >> 4
573 * X' = (tile_num % tile_pitch) << 7
574 * | (A & 0b111000000000) >> 5
577 * For W tiling, tile() combines together the low-order bits of the X and Y
578 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
579 * bytes wide and 64 rows high (note that W tiling is only used for stencil
580 * buffers, which always have cpp = 1 and S=0):
582 * tile(w_tiled, X, Y, S) = A
583 * where A = tile_num << 12 | offset
584 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
585 * offset = (X' & 0b111000) << 6
586 * | (Y' & 0b111100) << 3
587 * | (X' & 0b100) << 2
593 * Y' = Y + S * qpitch
594 * detile(w_tiled, A) = (X, Y, S)
595 * where X = X' / cpp = X'
596 * Y = Y' % qpitch = Y'
598 * Y' = (tile_num / tile_pitch) << 6
599 * | (A & 0b111100000) >> 3
600 * | (A & 0b1000) >> 2
602 * X' = (tile_num % tile_pitch) << 6
603 * | (A & 0b111000000000) >> 6
604 * | (A & 0b10000) >> 2
608 * Finally, for a non-tiled surface, tile() simply combines together the X and
609 * Y coordinates in the natural way:
611 * tile(untiled, X, Y, S) = A
612 * where A = Y * pitch + X'
614 * Y' = Y + S * qpitch
615 * detile(untiled, A) = (X, Y, S)
622 * (In these formulas, pitch is the number of bytes occupied by a single row
625 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
628 brw_blorp_blit_program(struct brw_context
*brw
,
629 const brw_blorp_blit_prog_key
*key
);
631 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
,
632 FILE *dump_file
= stdout
);
634 brw_blorp_prog_data prog_data
;
638 void alloc_push_const_regs(int base_reg
);
639 void compute_frag_coords();
640 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
641 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
642 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
643 void translate_dst_to_src();
644 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
645 struct brw_reg clampX0
, struct brw_reg clampY0
,
646 struct brw_reg clampX1
, struct brw_reg clampY1
);
647 void single_to_blend();
648 void manual_blend_average(unsigned num_samples
);
649 void manual_blend_bilinear(unsigned num_samples
);
650 void sample(struct brw_reg dst
);
651 void texel_fetch(struct brw_reg dst
);
653 void texture_lookup(struct brw_reg dst
, enum opcode op
,
654 const sampler_message_arg
*args
, int num_args
);
655 void render_target_write();
657 void emit_lrp(const struct brw_reg
&dst
,
658 const struct brw_reg
&src1
,
659 const struct brw_reg
&src2
,
660 const struct brw_reg
&src3
);
663 * Base-2 logarithm of the maximum number of samples that can be blended.
665 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
667 struct brw_context
*brw
;
668 const brw_blorp_blit_prog_key
*key
;
670 /* Thread dispatch header */
673 /* Pixel X/Y coordinates (always in R1). */
677 struct brw_reg dst_x0
;
678 struct brw_reg dst_x1
;
679 struct brw_reg dst_y0
;
680 struct brw_reg dst_y1
;
681 /* Top right coordinates of the rectangular grid used for scaled blitting */
682 struct brw_reg rect_grid_x1
;
683 struct brw_reg rect_grid_y1
;
685 struct brw_reg multiplier
;
686 struct brw_reg offset
;
687 } x_transform
, y_transform
;
689 /* Data read from texture (4 vec16's per array element) */
690 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
692 /* Auxiliary storage for the contents of the MCS surface.
694 * Since the sampler always returns 8 registers worth of data, this is 8
695 * registers wide, even though we only use the first 2 registers of it.
697 struct brw_reg mcs_data
;
699 /* X coordinates. We have two of them so that we can perform coordinate
700 * transformations easily.
702 struct brw_reg x_coords
[2];
704 /* Y coordinates. We have two of them so that we can perform coordinate
705 * transformations easily.
707 struct brw_reg y_coords
[2];
709 /* X, Y coordinates of the pixel from which we need to fetch the specific
710 * sample. These are used for multisample scaled blitting.
712 struct brw_reg x_sample_coords
;
713 struct brw_reg y_sample_coords
;
715 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
716 struct brw_reg x_frac
;
717 struct brw_reg y_frac
;
719 /* Which element of x_coords and y_coords is currently in use.
723 /* True if, at the point in the program currently being compiled, the
724 * sample index is known to be zero.
728 /* Register storing the sample index when s_is_zero is false. */
729 struct brw_reg sample_index
;
735 /* MRF used for sampling and render target writes */
739 brw_blorp_blit_program::brw_blorp_blit_program(
740 struct brw_context
*brw
,
741 const brw_blorp_blit_prog_key
*key
)
742 : brw_blorp_eu_emitter(brw
),
749 brw_blorp_blit_program::compile(struct brw_context
*brw
,
750 GLuint
*program_size
,
754 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
755 /* If the destination image is W tiled and multisampled, then the thread
756 * must be dispatched once per sample, not once per pixel. This is
757 * necessary because after conversion between W and Y tiling, there's no
758 * guarantee that all samples corresponding to a single pixel will still
761 assert(key
->persample_msaa_dispatch
);
765 /* We are blending, which means we won't have an opportunity to
766 * translate the tiling and sample count for the texture surface. So
767 * the surface state for the texture must be configured with the correct
768 * tiling and sample count.
770 assert(!key
->src_tiled_w
);
771 assert(key
->tex_samples
== key
->src_samples
);
772 assert(key
->tex_layout
== key
->src_layout
);
773 assert(key
->tex_samples
> 0);
776 if (key
->persample_msaa_dispatch
) {
777 /* It only makes sense to do persample dispatch if the render target is
778 * configured as multisampled.
780 assert(key
->rt_samples
> 0);
783 /* Make sure layout is consistent with sample count */
784 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
785 (key
->tex_samples
== 0));
786 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
787 (key
->rt_samples
== 0));
788 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
789 (key
->src_samples
== 0));
790 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
791 (key
->dst_samples
== 0));
793 /* Set up prog_data */
794 memset(&prog_data
, 0, sizeof(prog_data
));
795 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
798 compute_frag_coords();
800 /* Render target and texture hardware don't support W tiling. */
801 const bool rt_tiled_w
= false;
802 const bool tex_tiled_w
= false;
804 /* The address that data will be written to is determined by the
805 * coordinates supplied to the WM thread and the tiling and sample count of
806 * the render target, according to the formula:
808 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
810 * If the actual tiling and sample count of the destination surface are not
811 * the same as the configuration of the render target, then these
812 * coordinates are wrong and we have to adjust them to compensate for the
815 if (rt_tiled_w
!= key
->dst_tiled_w
||
816 key
->rt_samples
!= key
->dst_samples
||
817 key
->rt_layout
!= key
->dst_layout
) {
818 encode_msaa(key
->rt_samples
, key
->rt_layout
);
819 /* Now (X, Y, S) = detile(rt_tiling, offset) */
820 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
821 /* Now (X, Y, S) = detile(dst_tiling, offset) */
822 decode_msaa(key
->dst_samples
, key
->dst_layout
);
825 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
827 * That is: X, Y and S now contain the true coordinates and sample index of
828 * the data that the WM thread should output.
830 * If we need to kill pixels that are outside the destination rectangle,
831 * now is the time to do it.
835 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
836 y_coords
[xy_coord_index
],
837 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
839 /* Next, apply a translation to obtain coordinates in the source image. */
840 translate_dst_to_src();
842 /* If the source image is not multisampled, then we want to fetch sample
843 * number 0, because that's the only sample there is.
845 if (key
->src_samples
== 0)
848 /* X, Y, and S are now the coordinates of the pixel in the source image
849 * that we want to texture from. Exception: if we are blending, then S is
850 * irrelevant, because we are going to fetch all samples.
852 if (key
->blend
&& !key
->blit_scaled
) {
854 /* Gen6 hardware an automatically blend using the SAMPLE message */
856 sample(texture_data
[0]);
858 /* Gen7+ hardware doesn't automaticaly blend. */
859 manual_blend_average(key
->src_samples
);
861 } else if(key
->blend
&& key
->blit_scaled
) {
862 manual_blend_bilinear(key
->src_samples
);
864 /* We aren't blending, which means we just want to fetch a single sample
865 * from the source surface. The address that we want to fetch from is
866 * related to the X, Y and S values according to the formula:
868 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
870 * If the actual tiling and sample count of the source surface are not
871 * the same as the configuration of the texture, then we need to adjust
872 * the coordinates to compensate for the difference.
874 if ((tex_tiled_w
!= key
->src_tiled_w
||
875 key
->tex_samples
!= key
->src_samples
||
876 key
->tex_layout
!= key
->src_layout
) &&
877 !key
->bilinear_filter
) {
878 encode_msaa(key
->src_samples
, key
->src_layout
);
879 /* Now (X, Y, S) = detile(src_tiling, offset) */
880 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
881 /* Now (X, Y, S) = detile(tex_tiling, offset) */
882 decode_msaa(key
->tex_samples
, key
->tex_layout
);
885 if (key
->bilinear_filter
) {
886 sample(texture_data
[0]);
889 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
891 * In other words: X, Y, and S now contain values which, when passed to
892 * the texturing unit, will cause data to be read from the correct
893 * memory location. So we can fetch the texel now.
895 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
897 texel_fetch(texture_data
[0]);
901 /* Finally, write the fetched (or blended) value to the render target and
902 * terminate the thread.
904 render_target_write();
906 return get_program(program_size
, dump_file
);
910 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
912 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
913 #define ALLOC_REG(name, type) \
915 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
916 base_reg + CONST_LOC(name) / 32, \
917 (CONST_LOC(name) % 32) / 4), type)
919 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
920 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
921 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
922 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
923 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
924 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
925 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
926 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
927 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
928 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
934 brw_blorp_blit_program::alloc_regs()
937 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
938 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
939 prog_data
.first_curbe_grf
= reg
;
940 alloc_push_const_regs(reg
);
941 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
942 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
943 this->texture_data
[i
] =
944 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
948 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
950 for (int i
= 0; i
< 2; ++i
) {
952 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
955 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
959 if (key
->blit_scaled
&& key
->blend
) {
960 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
962 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
964 this->x_frac
= brw_vec8_grf(reg
, 0);
966 this->y_frac
= brw_vec8_grf(reg
, 0);
970 this->xy_coord_index
= 0;
972 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
974 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
976 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
979 /* Make sure we didn't run out of registers */
980 assert(reg
<= GEN7_MRF_HACK_START
);
983 this->base_mrf
= mrf
;
986 /* In the code that follows, X and Y can be used to quickly refer to the
987 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
988 * prime") to the inactive elements.
990 * S can be used to quickly refer to sample_index.
992 #define X x_coords[xy_coord_index]
993 #define Y y_coords[xy_coord_index]
994 #define Xp x_coords[!xy_coord_index]
995 #define Yp y_coords[!xy_coord_index]
996 #define S sample_index
998 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
999 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
1001 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
1004 * Emit code to compute the X and Y coordinates of the pixels being rendered
1005 * by this WM invocation.
1007 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1008 * related to the address offset where outputs will be written by the formula:
1010 * (X, Y, S) = decode_msaa(detile(offset)).
1012 * (See brw_blorp_blit_program).
1015 brw_blorp_blit_program::compute_frag_coords()
1017 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1018 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1019 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1020 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1022 * Pixels within a subspan are laid out in this arrangement:
1026 * So, to compute the coordinates of each pixel, we need to read every 2nd
1027 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1028 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1029 * In other words, the data we want to access is R1.4<2;4,0>UW.
1031 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1032 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1034 brw_ADD(&func
, vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1035 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1037 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1038 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1039 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1042 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1043 * pixels n+2 and n+3 are in the bottom half of the subspan.
1045 brw_ADD(&func
, vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1046 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1048 /* Move the coordinates to UD registers. */
1049 brw_MOV(&func
, vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1050 brw_MOV(&func
, vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1053 if (key
->persample_msaa_dispatch
) {
1054 switch (key
->rt_samples
) {
1056 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1057 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1058 * represent sample 1, and so on.
1060 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1061 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1062 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1063 * then copy from it using vstride=1, width=4, hstride=0.
1065 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1066 brw_MOV(&func
, vec16(t1_uw1
), brw_imm_v(0x3210));
1067 /* Move to UD sample_index register. */
1068 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1069 brw_MOV(&func
, S
, stride(t1_uw1
, 1, 4, 0));
1070 brw_MOV(&func
, offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1071 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1075 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1076 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1077 * subspan 1 will represent sample 1, and so on. We can find the
1078 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1079 * Index") and multiplying by two (since samples are always delivered
1080 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1083 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1084 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1085 * variable with the sequence (0, 1, 2, 3), and then reading from it
1086 * using vstride=1, width=4, hstride=0.
1088 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1089 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1090 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1091 brw_AND(&func
, t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1092 brw_SHR(&func
, t1_ud1
, t1_ud1
, brw_imm_ud(5));
1093 brw_MOV(&func
, vec16(t2_uw1
), brw_imm_v(0x3210));
1094 brw_ADD(&func
, vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1095 stride(t2_uw1
, 1, 4, 0));
1096 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1097 brw_ADD(&func
, offset(S
, 1),
1098 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1099 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1100 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1104 assert(!"Unrecognized sample count in "
1105 "brw_blorp_blit_program::compute_frag_coords()");
1110 /* Either the destination surface is single-sampled, or the WM will be
1111 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1112 * per pixel). In either case, it's not meaningful to compute a sample
1113 * value. Just set it to 0.
1120 * Emit code to compensate for the difference between Y and W tiling.
1122 * This code modifies the X and Y coordinates according to the formula:
1124 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1126 * (See brw_blorp_blit_program).
1128 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1129 * are booleans where true represents W tiling and false represents Y tiling.
1132 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1134 if (old_tiled_w
== new_tiled_w
)
1137 /* In the code that follows, we can safely assume that S = 0, because W
1138 * tiling formats always use IMS layout.
1143 /* Given X and Y coordinates that describe an address using Y tiling,
1144 * translate to the X and Y coordinates that describe the same address
1147 * If we break down the low order bits of X and Y, using a
1148 * single letter to represent each low-order bit:
1150 * X = A << 7 | 0bBCDEFGH
1151 * Y = J << 5 | 0bKLMNP (1)
1153 * Then we can apply the Y tiling formula to see the memory offset being
1156 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1158 * If we apply the W detiling formula to this memory location, that the
1159 * corresponding X' and Y' coordinates are:
1161 * X' = A << 6 | 0bBCDPFH (3)
1162 * Y' = J << 6 | 0bKLMNEG
1164 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1165 * we need to make the following computation:
1167 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1168 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1170 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1171 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1172 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1173 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1174 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1175 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1176 brw_OR(&func
, Xp
, t1
, t2
);
1177 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1178 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1179 brw_AND(&func
, t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1180 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1181 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1182 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1183 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1184 brw_OR(&func
, Yp
, t1
, t2
);
1187 /* Applying the same logic as above, but in reverse, we obtain the
1190 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1191 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1193 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1194 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1195 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1196 brw_SHL(&func
, t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1197 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1198 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1199 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1200 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1202 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1203 brw_OR(&func
, Xp
, t1
, t2
);
1204 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1205 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1206 brw_AND(&func
, t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1207 brw_SHR(&func
, t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1208 brw_OR(&func
, Yp
, t1
, t2
);
1214 * Emit code to compensate for the difference between MSAA and non-MSAA
1217 * This code modifies the X and Y coordinates according to the formula:
1219 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1221 * (See brw_blorp_blit_program).
1224 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1225 intel_msaa_layout layout
)
1228 case INTEL_MSAA_LAYOUT_NONE
:
1229 /* No translation necessary, and S should already be zero. */
1232 case INTEL_MSAA_LAYOUT_CMS
:
1233 /* We can't compensate for compressed layout since at this point in the
1234 * program we haven't read from the MCS buffer.
1236 assert(!"Bad layout in encode_msaa");
1238 case INTEL_MSAA_LAYOUT_UMS
:
1239 /* No translation necessary. */
1241 case INTEL_MSAA_LAYOUT_IMS
:
1242 switch (num_samples
) {
1244 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1245 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1246 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1248 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1250 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1251 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1253 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1255 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1256 brw_OR(&func
, Xp
, t1
, t2
);
1257 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1258 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1260 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1261 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1263 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1264 brw_OR(&func
, Yp
, t1
, t2
);
1267 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1268 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1270 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1272 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1273 brw_SHL(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1275 brw_AND(&func
, t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1276 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1277 brw_AND(&func
, t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1278 brw_SHL(&func
, t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1279 brw_OR(&func
, t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1282 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1283 brw_OR(&func
, Xp
, t1
, t2
);
1284 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1285 brw_SHL(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1287 brw_AND(&func
, t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1288 brw_OR(&func
, t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1290 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1291 brw_OR(&func
, Yp
, t1
, t2
);
1301 * Emit code to compensate for the difference between MSAA and non-MSAA
1304 * This code modifies the X and Y coordinates according to the formula:
1306 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1308 * (See brw_blorp_blit_program).
1311 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1312 intel_msaa_layout layout
)
1315 case INTEL_MSAA_LAYOUT_NONE
:
1316 /* No translation necessary, and S should already be zero. */
1319 case INTEL_MSAA_LAYOUT_CMS
:
1320 /* We can't compensate for compressed layout since at this point in the
1321 * program we don't have access to the MCS buffer.
1323 assert(!"Bad layout in encode_msaa");
1325 case INTEL_MSAA_LAYOUT_UMS
:
1326 /* No translation necessary. */
1328 case INTEL_MSAA_LAYOUT_IMS
:
1330 switch (num_samples
) {
1332 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1333 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1334 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1335 * S = (Y & 0b10) | (X & 0b10) >> 1
1337 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1338 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1339 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1340 brw_OR(&func
, Xp
, t1
, t2
);
1341 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1342 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1343 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1344 brw_OR(&func
, Yp
, t1
, t2
);
1345 brw_AND(&func
, t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1346 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1347 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1348 brw_OR(&func
, S
, t1
, t2
);
1351 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1352 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1353 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1354 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1356 brw_AND(&func
, t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1357 brw_SHR(&func
, t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1358 brw_AND(&func
, t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1359 brw_OR(&func
, Xp
, t1
, t2
);
1360 brw_AND(&func
, t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1361 brw_SHR(&func
, t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1362 brw_AND(&func
, t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1363 brw_OR(&func
, Yp
, t1
, t2
);
1364 brw_AND(&func
, t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1365 brw_AND(&func
, t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1366 brw_OR(&func
, t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1367 brw_AND(&func
, t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1368 brw_SHR(&func
, t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1369 brw_OR(&func
, S
, t1
, t2
);
1379 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1383 brw_blorp_blit_program::translate_dst_to_src()
1385 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1386 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1387 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1388 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1390 /* Move the UD coordinates to float registers. */
1391 brw_MOV(&func
, Xp_f
, X
);
1392 brw_MOV(&func
, Yp_f
, Y
);
1393 /* Scale and offset */
1394 brw_MUL(&func
, X_f
, Xp_f
, x_transform
.multiplier
);
1395 brw_MUL(&func
, Y_f
, Yp_f
, y_transform
.multiplier
);
1396 brw_ADD(&func
, X_f
, X_f
, x_transform
.offset
);
1397 brw_ADD(&func
, Y_f
, Y_f
, y_transform
.offset
);
1398 if (key
->blit_scaled
&& key
->blend
) {
1399 /* Translate coordinates to lay out the samples in a rectangular grid
1400 * roughly corresponding to sample locations.
1402 brw_MUL(&func
, X_f
, X_f
, brw_imm_f(key
->x_scale
));
1403 brw_MUL(&func
, Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1404 /* Adjust coordinates so that integers represent pixel centers rather
1407 brw_ADD(&func
, X_f
, X_f
, brw_imm_f(-0.5));
1408 brw_ADD(&func
, Y_f
, Y_f
, brw_imm_f(-0.5));
1410 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1411 * texels on texture edges.
1413 clamp_tex_coords(X_f
, Y_f
,
1414 brw_imm_f(0.0), brw_imm_f(0.0),
1415 rect_grid_x1
, rect_grid_y1
);
1417 /* Store the fractional parts to be used as bilinear interpolation
1420 brw_FRC(&func
, x_frac
, X_f
);
1421 brw_FRC(&func
, y_frac
, Y_f
);
1423 /* Round the float coordinates down to nearest integer */
1424 brw_RNDD(&func
, Xp_f
, X_f
);
1425 brw_RNDD(&func
, Yp_f
, Y_f
);
1426 brw_MUL(&func
, X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1427 brw_MUL(&func
, Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1429 } else if (!key
->bilinear_filter
) {
1430 /* Round the float coordinates down to nearest integer by moving to
1433 brw_MOV(&func
, Xp
, X_f
);
1434 brw_MOV(&func
, Yp
, Y_f
);
1440 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1441 struct brw_reg regY
,
1442 struct brw_reg clampX0
,
1443 struct brw_reg clampY0
,
1444 struct brw_reg clampX1
,
1445 struct brw_reg clampY1
)
1447 emit_cond_mov(regX
, clampX0
, BRW_CONDITIONAL_L
, regX
, clampX0
);
1448 emit_cond_mov(regX
, clampX1
, BRW_CONDITIONAL_G
, regX
, clampX1
);
1449 emit_cond_mov(regY
, clampY0
, BRW_CONDITIONAL_L
, regY
, clampY0
);
1450 emit_cond_mov(regY
, clampY1
, BRW_CONDITIONAL_G
, regY
, clampY1
);
1454 * Emit code to transform the X and Y coordinates as needed for blending
1455 * together the different samples in an MSAA texture.
1458 brw_blorp_blit_program::single_to_blend()
1460 /* When looking up samples in an MSAA texture using the SAMPLE message,
1461 * Gen6 requires the texture coordinates to be odd integers (so that they
1462 * correspond to the center of a 2x2 block representing the four samples
1463 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1464 * each by 2 and then add 1.
1466 brw_SHL(&func
, t1
, X
, brw_imm_w(1));
1467 brw_SHL(&func
, t2
, Y
, brw_imm_w(1));
1468 brw_ADD(&func
, Xp
, t1
, brw_imm_w(1));
1469 brw_ADD(&func
, Yp
, t2
, brw_imm_w(1));
1475 * Count the number of trailing 1 bits in the given value. For example:
1477 * count_trailing_one_bits(0) == 0
1478 * count_trailing_one_bits(7) == 3
1479 * count_trailing_one_bits(11) == 2
1481 inline int count_trailing_one_bits(unsigned value
)
1483 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1484 return __builtin_ctz(~value
);
1486 return _mesa_bitcount(value
& ~(value
+ 1));
1492 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1494 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1497 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1499 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1501 * This ensures that when all samples have the same value, no numerical
1502 * precision is lost, since each addition operation always adds two equal
1503 * values, and summing two equal floating point values does not lose
1506 * We perform this computation by treating the texture_data array as a
1507 * stack and performing the following operations:
1509 * - push sample 0 onto stack
1510 * - push sample 1 onto stack
1511 * - add top two stack entries
1512 * - push sample 2 onto stack
1513 * - push sample 3 onto stack
1514 * - add top two stack entries
1515 * - add top two stack entries
1516 * - divide top stack entry by 4
1518 * Note that after pushing sample i onto the stack, the number of add
1519 * operations we do is equal to the number of trailing 1 bits in i. This
1520 * works provided the total number of samples is a power of two, which it
1521 * always is for i965.
1523 * For integer formats, we replace the add operations with average
1524 * operations and skip the final division.
1526 unsigned stack_depth
= 0;
1527 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1528 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1530 /* Push sample i onto the stack */
1531 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1536 brw_MOV(&func
, vec16(S
), brw_imm_ud(i
));
1538 texel_fetch(texture_data
[stack_depth
++]);
1540 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1541 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1542 * suggests an optimization:
1544 * "A simple optimization with probable large return in
1545 * performance is to compare the MCS value to zero (indicating
1546 * all samples are on sample slice 0), and sample only from
1547 * sample slice 0 using ld2dss if MCS is zero."
1549 * Note that in the case where the MCS value is zero, sampling from
1550 * sample slice 0 using ld2dss and sampling from sample 0 using
1551 * ld2dms are equivalent (since all samples are on sample slice 0).
1552 * Since we have already sampled from sample 0, all we need to do is
1553 * skip the remaining fetches and averaging if MCS is zero.
1555 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_NZ
,
1556 mcs_data
, brw_imm_ud(0));
1557 brw_IF(&func
, BRW_EXECUTE_16
);
1560 /* Do count_trailing_one_bits(i) times */
1561 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1562 assert(stack_depth
>= 2);
1565 /* TODO: should use a smaller loop bound for non_RGBA formats */
1566 for (int k
= 0; k
< 4; ++k
) {
1567 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1568 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1569 offset(texture_data
[stack_depth
- 1], 2*k
),
1570 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1571 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1576 /* We should have just 1 sample on the stack now. */
1577 assert(stack_depth
== 1);
1579 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1580 /* Scale the result down by a factor of num_samples */
1581 /* TODO: should use a smaller loop bound for non-RGBA formats */
1582 for (int j
= 0; j
< 4; ++j
) {
1583 brw_MUL(&func
, offset(texture_data
[0], 2*j
),
1584 offset(vec8(texture_data
[0]), 2*j
),
1585 brw_imm_f(1.0/num_samples
));
1589 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1594 brw_blorp_blit_program::emit_lrp(const struct brw_reg
&dst
,
1595 const struct brw_reg
&src1
,
1596 const struct brw_reg
&src2
,
1597 const struct brw_reg
&src3
)
1599 brw_set_access_mode(&func
, BRW_ALIGN_16
);
1600 brw_set_compression_control(&func
, BRW_COMPRESSION_NONE
);
1601 brw_LRP(&func
, dst
, src1
, src2
, src3
);
1602 brw_set_compression_control(&func
, BRW_COMPRESSION_2NDHALF
);
1603 brw_LRP(&func
, sechalf(dst
), sechalf(src1
), sechalf(src2
), sechalf(src3
));
1604 brw_set_compression_control(&func
, BRW_COMPRESSION_COMPRESSED
);
1605 brw_set_access_mode(&func
, BRW_ALIGN_1
);
1609 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1611 /* We do this computation by performing the following operations:
1613 * In case of 4x, 8x MSAA:
1614 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1615 * which are later used for interpolation
1616 * - linearly interpolate samples a and b in X
1617 * - linearly interpolate samples c and d in X
1618 * - linearly interpolate the results of last two operations in Y
1620 * result = lrp(lrp(a + b) + lrp(c + d))
1622 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1623 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1624 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1625 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1627 for (unsigned i
= 0; i
< 4; ++i
) {
1628 assert(i
< ARRAY_SIZE(texture_data
));
1631 /* Compute pixel coordinates */
1632 brw_ADD(&func
, vec16(x_sample_coords
), Xp_f
,
1633 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1634 brw_ADD(&func
, vec16(y_sample_coords
), Yp_f
,
1635 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1636 brw_MOV(&func
, vec16(X
), x_sample_coords
);
1637 brw_MOV(&func
, vec16(Y
), y_sample_coords
);
1639 /* The MCS value we fetch has to match up with the pixel that we're
1640 * sampling from. Since we sample from different pixels in each
1641 * iteration of this "for" loop, the call to mcs_fetch() should be
1642 * here inside the loop after computing the pixel coordinates.
1644 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1647 /* Compute sample index and map the sample index to a sample number.
1648 * Sample index layout shows the numbering of slots in a rectangular
1649 * grid of samples with in a pixel. Sample number layout shows the
1650 * rectangular grid of samples roughly corresponding to the real sample
1651 * locations with in a pixel.
1652 * In case of 4x MSAA, layout of sample indices matches the layout of
1660 * In case of 8x MSAA the two layouts don't match.
1661 * sample index layout : --------- sample number layout : ---------
1662 * | 0 | 1 | | 5 | 2 |
1663 * --------- ---------
1664 * | 2 | 3 | | 4 | 6 |
1665 * --------- ---------
1666 * | 4 | 5 | | 0 | 3 |
1667 * --------- ---------
1668 * | 6 | 7 | | 7 | 1 |
1669 * --------- ---------
1671 brw_FRC(&func
, vec16(t1_f
), x_sample_coords
);
1672 brw_FRC(&func
, vec16(t2_f
), y_sample_coords
);
1673 brw_MUL(&func
, vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1674 brw_MUL(&func
, vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1675 brw_ADD(&func
, vec16(t1_f
), t1_f
, t2_f
);
1676 brw_MOV(&func
, vec16(S
), t1_f
);
1678 if (num_samples
== 8) {
1679 /* Map the sample index to a sample number */
1680 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_L
,
1682 brw_IF(&func
, BRW_EXECUTE_16
);
1684 brw_MOV(&func
, vec16(t2
), brw_imm_d(5));
1685 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1687 brw_MOV(&func
, vec16(t2
), brw_imm_d(2));
1688 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1689 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1691 brw_MOV(&func
, vec16(t2
), brw_imm_d(4));
1692 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1693 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1695 brw_MOV(&func
, vec16(t2
), brw_imm_d(6));
1696 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1700 brw_MOV(&func
, vec16(t2
), brw_imm_d(0));
1701 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1703 brw_MOV(&func
, vec16(t2
), brw_imm_d(3));
1704 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1705 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1707 brw_MOV(&func
, vec16(t2
), brw_imm_d(7));
1708 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1709 brw_CMP(&func
, vec16(brw_null_reg()), BRW_CONDITIONAL_EQ
,
1711 brw_MOV(&func
, vec16(t2
), brw_imm_d(1));
1712 brw_set_predicate_control(&func
, BRW_PREDICATE_NONE
);
1715 brw_MOV(&func
, vec16(S
), t2
);
1717 texel_fetch(texture_data
[i
]);
1720 #define SAMPLE(x, y) offset(texture_data[x], y)
1721 for (int index
= 3; index
> 0; ) {
1722 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1723 * Counter value of 8 in 'for' loop below is used to interpolate all
1724 * the color components.
1726 for (int k
= 0; k
< 8; k
+= 2)
1727 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1729 vec8(SAMPLE(index
, k
)),
1730 vec8(SAMPLE(index
- 1, k
)));
1733 for (int k
= 0; k
< 8; k
+= 2)
1734 emit_lrp(vec8(SAMPLE(0, k
)),
1737 vec8(SAMPLE(0, k
)));
1742 * Emit code to look up a value in the texture using the SAMPLE message (which
1743 * does blending of MSAA surfaces).
1746 brw_blorp_blit_program::sample(struct brw_reg dst
)
1748 static const sampler_message_arg args
[2] = {
1749 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1750 SAMPLER_MESSAGE_ARG_V_FLOAT
1753 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1757 * Emit code to look up a value in the texture using the SAMPLE_LD message
1758 * (which does a simple texel fetch).
1761 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1763 static const sampler_message_arg gen6_args
[5] = {
1764 SAMPLER_MESSAGE_ARG_U_INT
,
1765 SAMPLER_MESSAGE_ARG_V_INT
,
1766 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1767 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1768 SAMPLER_MESSAGE_ARG_SI_INT
1770 static const sampler_message_arg gen7_ld_args
[3] = {
1771 SAMPLER_MESSAGE_ARG_U_INT
,
1772 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1773 SAMPLER_MESSAGE_ARG_V_INT
1775 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1776 SAMPLER_MESSAGE_ARG_SI_INT
,
1777 SAMPLER_MESSAGE_ARG_U_INT
,
1778 SAMPLER_MESSAGE_ARG_V_INT
1780 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1781 SAMPLER_MESSAGE_ARG_SI_INT
,
1782 SAMPLER_MESSAGE_ARG_MCS_INT
,
1783 SAMPLER_MESSAGE_ARG_U_INT
,
1784 SAMPLER_MESSAGE_ARG_V_INT
1789 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1792 switch (key
->tex_layout
) {
1793 case INTEL_MSAA_LAYOUT_IMS
:
1794 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1797 * If this field is MSFMT_DEPTH_STENCIL
1798 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1799 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1801 * So fall through to emit the same message as we use for
1802 * INTEL_MSAA_LAYOUT_CMS.
1804 case INTEL_MSAA_LAYOUT_CMS
:
1805 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1806 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1808 case INTEL_MSAA_LAYOUT_UMS
:
1809 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1810 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1812 case INTEL_MSAA_LAYOUT_NONE
:
1814 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1815 ARRAY_SIZE(gen7_ld_args
));
1820 assert(!"Should not get here.");
1826 brw_blorp_blit_program::mcs_fetch()
1828 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1829 SAMPLER_MESSAGE_ARG_U_INT
,
1830 SAMPLER_MESSAGE_ARG_V_INT
1832 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1833 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1837 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1839 const sampler_message_arg
*args
,
1842 struct brw_reg mrf
=
1843 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1844 for (int arg
= 0; arg
< num_args
; ++arg
) {
1845 switch (args
[arg
]) {
1846 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1847 if (key
->bilinear_filter
)
1848 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1849 retype(X
, BRW_REGISTER_TYPE_F
));
1851 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1853 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1854 if (key
->bilinear_filter
)
1855 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
),
1856 retype(Y
, BRW_REGISTER_TYPE_F
));
1858 brw_MOV(&func
, retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1860 case SAMPLER_MESSAGE_ARG_U_INT
:
1861 brw_MOV(&func
, mrf
, X
);
1863 case SAMPLER_MESSAGE_ARG_V_INT
:
1864 brw_MOV(&func
, mrf
, Y
);
1866 case SAMPLER_MESSAGE_ARG_SI_INT
:
1867 /* Note: on Gen7, this code may be reached with s_is_zero==true
1868 * because in Gen7's ld2dss message, the sample index is the first
1869 * argument. When this happens, we need to move a 0 into the
1870 * appropriate message register.
1873 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1875 brw_MOV(&func
, mrf
, S
);
1877 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1878 switch (key
->tex_layout
) {
1879 case INTEL_MSAA_LAYOUT_CMS
:
1880 brw_MOV(&func
, mrf
, mcs_data
);
1882 case INTEL_MSAA_LAYOUT_IMS
:
1883 /* When sampling from an IMS surface, MCS data is not relevant,
1884 * and the hardware ignores it. So don't bother populating it.
1888 /* We shouldn't be trying to send MCS data with any other
1891 assert (!"Unsupported layout for MCS data");
1895 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1896 brw_MOV(&func
, mrf
, brw_imm_ud(0));
1902 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1905 mrf
.nr
- base_mrf
/* msg_length */);
1913 #undef SWAP_XY_AND_XPYP
1916 brw_blorp_blit_program::render_target_write()
1918 struct brw_reg mrf_rt_write
=
1919 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1922 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1923 * so that the render target knows which pixels we killed.
1925 bool use_header
= key
->use_kill
;
1927 /* Copy R0/1 to MRF */
1928 brw_MOV(&func
, retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1929 retype(R0
, BRW_REGISTER_TYPE_UD
));
1933 /* Copy texture data to MRFs */
1934 for (int i
= 0; i
< 4; ++i
) {
1935 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1936 brw_MOV(&func
, offset(mrf_rt_write
, mrf_offset
),
1937 offset(vec8(texture_data
[0]), 2*i
));
1941 /* Now write to the render target and terminate the thread */
1942 emit_render_target_write(
1945 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1951 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1952 GLfloat dst0
, GLfloat dst1
,
1955 float scale
= (src1
- src0
) / (dst1
- dst0
);
1957 /* When not mirroring a coordinate (say, X), we need:
1958 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1960 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1962 * blorp program uses "round toward zero" to convert the
1963 * transformed floating point coordinates to integer coordinates,
1964 * whereas the behaviour we actually want is "round to nearest",
1965 * so 0.5 provides the necessary correction.
1968 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1970 /* When mirroring X we need:
1971 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1973 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1975 multiplier
= -scale
;
1976 offset
= src0
+ (dst1
- 0.5) * scale
;
1982 * Determine which MSAA layout the GPU pipeline should be configured for,
1983 * based on the chip generation, the number of samples, and the true layout of
1984 * the image in memory.
1986 inline intel_msaa_layout
1987 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1988 intel_msaa_layout true_layout
)
1990 if (num_samples
<= 1) {
1991 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1992 * format buffers, by transforming coordinates appropriately.
1994 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1995 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1996 return INTEL_MSAA_LAYOUT_NONE
;
1998 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2001 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2002 if (brw
->gen
== 6) {
2003 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2010 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
2011 struct intel_mipmap_tree
*src_mt
,
2012 unsigned src_level
, unsigned src_layer
,
2013 struct intel_mipmap_tree
*dst_mt
,
2014 unsigned dst_level
, unsigned dst_layer
,
2015 GLfloat src_x0
, GLfloat src_y0
,
2016 GLfloat src_x1
, GLfloat src_y1
,
2017 GLfloat dst_x0
, GLfloat dst_y0
,
2018 GLfloat dst_x1
, GLfloat dst_y1
,
2020 bool mirror_x
, bool mirror_y
)
2022 struct gl_context
*ctx
= &brw
->ctx
;
2023 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
2025 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
2026 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
2028 /* Even though we do multisample resolves at the time of the blit, OpenGL
2029 * specification defines them as if they happen at the time of rendering,
2030 * which means that the type of averaging we do during the resolve should
2031 * only depend on the source format; the destination format should be
2032 * ignored. But, specification doesn't seem to be strict about it.
2034 * It has been observed that mulitisample resolves produce slightly better
2035 * looking images when averaging is done using destination format. NVIDIA's
2036 * proprietary OpenGL driver also follow this approach. So, we choose to
2037 * follow it in our driver.
2039 * When multisampling, if the source and destination formats are equal
2040 * (aside from the color space), we choose to blit in sRGB space to get
2041 * this higher quality image.
2043 if (src
.num_samples
> 1 &&
2044 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
2045 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2046 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2047 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2048 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2051 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
2052 * texture, the above code configures the source format for L32_FLOAT or
2053 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
2054 * the SAMPLE message appears to handle multisampled L32_FLOAT and
2055 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
2056 * around the problem by using a source format of R32_FLOAT. This
2057 * shouldn't affect rendering correctness, since the destination format is
2058 * R32_FLOAT, so only the contents of the red channel matters.
2060 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
2061 src_mt
->format
== dst_mt
->format
&&
2062 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
2063 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2067 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2069 /* texture_data_type indicates the register type that should be used to
2070 * manipulate texture data.
2072 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2073 case GL_UNSIGNED_NORMALIZED
:
2074 case GL_SIGNED_NORMALIZED
:
2076 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2078 case GL_UNSIGNED_INT
:
2079 if (src_mt
->format
== MESA_FORMAT_S8
) {
2080 /* We process stencil as though it's an unsigned normalized color */
2081 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2083 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2087 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2090 assert(!"Unrecognized blorp format");
2095 /* Gen7's rendering hardware only supports the IMS layout for depth and
2096 * stencil render targets. Blorp always maps its destination surface as
2097 * a color render target (even if it's actually a depth or stencil
2098 * buffer). So if the destination is IMS, we'll have to map it as a
2099 * single-sampled texture and interleave the samples ourselves.
2101 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2102 dst
.num_samples
= 0;
2105 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2106 /* If the destination surface is a W-tiled multisampled stencil buffer
2107 * that we're mapping as Y tiled, then we need to arrange for the WM
2108 * program to run once per sample rather than once per pixel, because
2109 * the memory layout of related samples doesn't match between W and Y
2112 wm_prog_key
.persample_msaa_dispatch
= true;
2115 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2116 /* We are blitting from a multisample buffer to a multisample buffer, so
2117 * we must preserve samples within a pixel. This means we have to
2118 * arrange for the WM program to run once per sample rather than once
2121 wm_prog_key
.persample_msaa_dispatch
= true;
2124 /* Scaled blitting or not. */
2125 wm_prog_key
.blit_scaled
=
2126 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2127 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2129 /* Scaling factors used for bilinear filtering in multisample scaled
2132 wm_prog_key
.x_scale
= 2.0;
2133 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2135 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2136 wm_prog_key
.bilinear_filter
= true;
2138 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2139 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2140 base_format
!= GL_STENCIL_INDEX
&&
2141 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2142 /* We are downsampling a color buffer, so blend. */
2143 wm_prog_key
.blend
= true;
2146 /* src_samples and dst_samples are the true sample counts */
2147 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2148 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2150 /* tex_samples and rt_samples are the sample counts that are set up in
2153 wm_prog_key
.tex_samples
= src
.num_samples
;
2154 wm_prog_key
.rt_samples
= dst
.num_samples
;
2156 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2157 * use to access the source and destination surfaces.
2159 wm_prog_key
.tex_layout
=
2160 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2161 wm_prog_key
.rt_layout
=
2162 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2164 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2167 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2168 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2170 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2171 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2172 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2173 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2174 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2175 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2176 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2177 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2179 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2180 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2182 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2183 /* We must expand the rectangle we send through the rendering pipeline,
2184 * to account for the fact that we are mapping the destination region as
2185 * single-sampled when it is in fact multisampled. We must also align
2186 * it to a multiple of the multisampling pattern, because the
2187 * differences between multisampled and single-sampled surface formats
2188 * will mean that pixels are scrambled within the multisampling pattern.
2189 * TODO: what if this makes the coordinates too large?
2191 * Note: this only works if the destination surface uses the IMS layout.
2192 * If it's UMS, then we have no choice but to set up the rendering
2193 * pipeline as multisampled.
2195 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2196 switch (dst_mt
->num_samples
) {
2198 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2199 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2200 x1
= ALIGN(x1
* 2, 4);
2201 y1
= ALIGN(y1
* 2, 4);
2204 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2205 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2206 x1
= ALIGN(x1
* 4, 8);
2207 y1
= ALIGN(y1
* 2, 4);
2210 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2213 wm_prog_key
.use_kill
= true;
2216 if (dst
.map_stencil_as_y_tiled
) {
2217 /* We must modify the rectangle we send through the rendering pipeline
2218 * (and the size and x/y offset of the destination surface), to account
2219 * for the fact that we are mapping it as Y-tiled when it is in fact
2222 * Both Y tiling and W tiling can be understood as organizations of
2223 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2224 * is different, but the layout of the 32-byte sub-tiles within the 4k
2225 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2226 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2227 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2229 * Therefore, to account for the layout differences within the 32-byte
2230 * sub-tiles, we must expand the rectangle so the X coordinates of its
2231 * edges are multiples of 8 (the W sub-tile width), and its Y
2232 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2233 * Then we need to scale the X and Y coordinates of the rectangle to
2234 * account for the differences in aspect ratio between the Y and W
2235 * sub-tiles. We need to modify the layer width and height similarly.
2237 * A correction needs to be applied when MSAA is in use: since
2238 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2239 * we need to align the Y coordinates to multiples of 8, so that when
2240 * they are divided by two they are still multiples of 4.
2242 * Note: Since the x/y offset of the surface will be applied using the
2243 * SURFACE_STATE command packet, it will be invisible to the swizzling
2244 * code in the shader; therefore it needs to be in a multiple of the
2245 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2246 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2247 * buffer), and the miplevel alignment used for stencil buffers is 8
2248 * pixels horizontally and either 4 or 8 pixels vertically (see
2249 * intel_horizontal_texture_alignment_unit() and
2250 * intel_vertical_texture_alignment_unit()).
2252 * Note: Also, since the SURFACE_STATE command packet can only apply
2253 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2254 * vertically, it is important that the offsets will be multiples of
2255 * these sizes after they are converted into Y-tiled coordinates.
2256 * Fortunately they will be, since we know from above that the offsets
2257 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2258 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2260 * TODO: what if this makes the coordinates (or the texture size) too
2263 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2264 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2265 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2266 x1
= ALIGN(x1
, x_align
) * 2;
2267 y1
= ALIGN(y1
, y_align
) / 2;
2268 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2269 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2272 wm_prog_key
.use_kill
= true;
2275 if (src
.map_stencil_as_y_tiled
) {
2276 /* We must modify the size and x/y offset of the source surface to
2277 * account for the fact that we are mapping it as Y-tiled when it is in
2280 * See the comments above concerning x/y offset alignment for the
2281 * destination surface.
2283 * TODO: what if this makes the texture size too large?
2285 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2286 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2287 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2294 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2295 brw_blorp_prog_data
**prog_data
) const
2297 uint32_t prog_offset
= 0;
2298 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2299 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2300 &prog_offset
, prog_data
)) {
2301 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2302 GLuint program_size
;
2303 const GLuint
*program
= prog
.compile(brw
, &program_size
, stdout
);
2304 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2305 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2306 program
, program_size
,
2307 &prog
.prog_data
, sizeof(prog
.prog_data
),
2308 &prog_offset
, prog_data
);
2314 brw_blorp_blit_test_compile(struct brw_context
*brw
,
2315 const brw_blorp_blit_prog_key
*key
,
2318 GLuint program_size
;
2319 brw_blorp_blit_program
prog(brw
, key
);
2320 INTEL_DEBUG
|= DEBUG_BLORP
;
2321 prog
.compile(brw
, &program_size
, out
);