2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/teximage.h"
25 #include "main/fbobject.h"
26 #include "main/renderbuffer.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
35 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 * Helper function for handling mirror image blits.
40 * If coord0 > coord1, swap them and invert the "mirror" boolean.
43 fixup_mirroring(bool &mirror
, GLfloat
&coord0
, GLfloat
&coord1
)
45 if (coord0
> coord1
) {
55 * Adjust {src,dst}_x{0,1} to account for clipping and scissoring of
56 * destination coordinates.
58 * Return true if there is still blitting to do, false if all pixels got
59 * rejected by the clip and/or scissor.
61 * For clarity, the nomenclature of this function assumes we are clipping and
62 * scissoring the X coordinate; the exact same logic applies for Y
65 * Note: this function may also be used to account for clipping of source
66 * coordinates, by swapping the roles of src and dst.
69 clip_or_scissor(bool mirror
, GLfloat
&src_x0
, GLfloat
&src_x1
, GLfloat
&dst_x0
,
70 GLfloat
&dst_x1
, GLfloat fb_xmin
, GLfloat fb_xmax
)
72 float scale
= (float) (src_x1
- src_x0
) / (dst_x1
- dst_x0
);
73 /* If we are going to scissor everything away, stop. */
74 if (!(fb_xmin
< fb_xmax
&&
81 /* Clip the destination rectangle, and keep track of how many pixels we
82 * clipped off of the left and right sides of it.
84 GLint pixels_clipped_left
= 0;
85 GLint pixels_clipped_right
= 0;
86 if (dst_x0
< fb_xmin
) {
87 pixels_clipped_left
= fb_xmin
- dst_x0
;
90 if (fb_xmax
< dst_x1
) {
91 pixels_clipped_right
= dst_x1
- fb_xmax
;
95 /* If we are mirrored, then before applying pixels_clipped_{left,right} to
96 * the source coordinates, we need to flip them to account for the
100 GLint tmp
= pixels_clipped_left
;
101 pixels_clipped_left
= pixels_clipped_right
;
102 pixels_clipped_right
= tmp
;
105 /* Adjust the source rectangle to remove the pixels corresponding to those
106 * that were clipped/scissored out of the destination rectangle.
108 src_x0
+= pixels_clipped_left
* scale
;
109 src_x1
-= pixels_clipped_right
* scale
;
115 static struct intel_mipmap_tree
*
116 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
118 struct intel_mipmap_tree
*mt
= irb
->mt
;
119 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
126 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
127 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
128 * the physical layer holding sample 0. So, for example, if
129 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
133 brw_blorp_blit_miptrees(struct brw_context
*brw
,
134 struct intel_mipmap_tree
*src_mt
,
135 unsigned src_level
, unsigned src_layer
,
136 struct intel_mipmap_tree
*dst_mt
,
137 unsigned dst_level
, unsigned dst_layer
,
138 float src_x0
, float src_y0
,
139 float src_x1
, float src_y1
,
140 float dst_x0
, float dst_y0
,
141 float dst_x1
, float dst_y1
,
142 GLenum filter
, bool mirror_x
, bool mirror_y
)
144 /* Get ready to blit. This includes depth resolving the src and dst
145 * buffers if necessary. Note: it's not necessary to do a color resolve on
146 * the destination buffer because we use the standard render path to render
147 * to destination color buffers, and the standard render path is
150 intel_miptree_resolve_color(brw
, src_mt
);
151 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
152 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
154 DBG("%s from %s mt %p %d %d (%f,%f) (%f,%f)"
155 "to %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
157 _mesa_get_format_name(src_mt
->format
), src_mt
,
158 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
159 _mesa_get_format_name(dst_mt
->format
), dst_mt
,
160 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
163 brw_blorp_blit_params
params(brw
,
164 src_mt
, src_level
, src_layer
,
165 dst_mt
, dst_level
, dst_layer
,
170 filter
, mirror_x
, mirror_y
);
171 brw_blorp_exec(brw
, ¶ms
);
173 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
177 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
178 struct intel_renderbuffer
*src_irb
,
179 struct intel_renderbuffer
*dst_irb
,
180 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
181 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
182 GLenum filter
, bool mirror_x
, bool mirror_y
)
184 /* Find source/dst miptrees */
185 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
186 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
189 brw_blorp_blit_miptrees(brw
,
190 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
191 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
192 srcX0
, srcY0
, srcX1
, srcY1
,
193 dstX0
, dstY0
, dstX1
, dstY1
,
194 filter
, mirror_x
, mirror_y
);
196 intel_renderbuffer_set_needs_downsample(dst_irb
);
200 color_formats_match(gl_format src_format
, gl_format dst_format
)
202 gl_format linear_src_format
= _mesa_get_srgb_format_linear(src_format
);
203 gl_format linear_dst_format
= _mesa_get_srgb_format_linear(dst_format
);
205 /* Normally, we require the formats to be equal. However, we also support
206 * blitting from ARGB to XRGB (discarding alpha), and from XRGB to ARGB
207 * (overriding alpha to 1.0 via blending).
209 return linear_src_format
== linear_dst_format
||
210 (linear_src_format
== MESA_FORMAT_XRGB8888
&&
211 linear_dst_format
== MESA_FORMAT_ARGB8888
) ||
212 (linear_src_format
== MESA_FORMAT_ARGB8888
&&
213 linear_dst_format
== MESA_FORMAT_XRGB8888
);
217 formats_match(GLbitfield buffer_bit
, struct intel_renderbuffer
*src_irb
,
218 struct intel_renderbuffer
*dst_irb
)
220 /* Note: don't just check gl_renderbuffer::Format, because in some cases
221 * multiple gl_formats resolve to the same native type in the miptree (for
222 * example MESA_FORMAT_X8_Z24 and MESA_FORMAT_S8_Z24), and we can blit
223 * between those formats.
225 gl_format src_format
= find_miptree(buffer_bit
, src_irb
)->format
;
226 gl_format dst_format
= find_miptree(buffer_bit
, dst_irb
)->format
;
228 return color_formats_match(src_format
, dst_format
);
232 try_blorp_blit(struct brw_context
*brw
,
233 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
234 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
235 GLenum filter
, GLbitfield buffer_bit
)
237 struct gl_context
*ctx
= &brw
->ctx
;
239 /* Sync up the state of window system buffers. We need to do this before
240 * we go looking for the buffers.
242 intel_prepare_render(brw
);
244 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
245 const struct gl_framebuffer
*draw_fb
= ctx
->DrawBuffer
;
247 /* Detect if the blit needs to be mirrored */
248 bool mirror_x
= false, mirror_y
= false;
249 fixup_mirroring(mirror_x
, srcX0
, srcX1
);
250 fixup_mirroring(mirror_x
, dstX0
, dstX1
);
251 fixup_mirroring(mirror_y
, srcY0
, srcY1
);
252 fixup_mirroring(mirror_y
, dstY0
, dstY1
);
254 /* If the destination rectangle needs to be clipped or scissored, do so.
256 if (!(clip_or_scissor(mirror_x
, srcX0
, srcX1
, dstX0
, dstX1
,
257 draw_fb
->_Xmin
, draw_fb
->_Xmax
) &&
258 clip_or_scissor(mirror_y
, srcY0
, srcY1
, dstY0
, dstY1
,
259 draw_fb
->_Ymin
, draw_fb
->_Ymax
))) {
260 /* Everything got clipped/scissored away, so the blit was successful. */
264 /* If the source rectangle needs to be clipped or scissored, do so. */
265 if (!(clip_or_scissor(mirror_x
, dstX0
, dstX1
, srcX0
, srcX1
,
266 0, read_fb
->Width
) &&
267 clip_or_scissor(mirror_y
, dstY0
, dstY1
, srcY0
, srcY1
,
268 0, read_fb
->Height
))) {
269 /* Everything got clipped/scissored away, so the blit was successful. */
273 /* Account for the fact that in the system framebuffer, the origin is at
276 if (_mesa_is_winsys_fbo(read_fb
)) {
277 GLint tmp
= read_fb
->Height
- srcY0
;
278 srcY0
= read_fb
->Height
- srcY1
;
280 mirror_y
= !mirror_y
;
282 if (_mesa_is_winsys_fbo(draw_fb
)) {
283 GLint tmp
= draw_fb
->Height
- dstY0
;
284 dstY0
= draw_fb
->Height
- dstY1
;
286 mirror_y
= !mirror_y
;
290 struct intel_renderbuffer
*src_irb
;
291 struct intel_renderbuffer
*dst_irb
;
292 switch (buffer_bit
) {
293 case GL_COLOR_BUFFER_BIT
:
294 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
295 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
296 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
297 if (dst_irb
&& !formats_match(buffer_bit
, src_irb
, dst_irb
))
300 for (unsigned i
= 0; i
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; ++i
) {
301 dst_irb
= intel_renderbuffer(ctx
->DrawBuffer
->_ColorDrawBuffers
[i
]);
303 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
304 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
305 filter
, mirror_x
, mirror_y
);
308 case GL_DEPTH_BUFFER_BIT
:
310 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
312 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
313 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
315 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
316 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
317 filter
, mirror_x
, mirror_y
);
319 case GL_STENCIL_BUFFER_BIT
:
321 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
323 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
324 if (!formats_match(buffer_bit
, src_irb
, dst_irb
))
326 do_blorp_blit(brw
, buffer_bit
, src_irb
, dst_irb
, srcX0
, srcY0
,
327 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
328 filter
, mirror_x
, mirror_y
);
338 brw_blorp_copytexsubimage(struct brw_context
*brw
,
339 struct gl_renderbuffer
*src_rb
,
340 struct gl_texture_image
*dst_image
,
342 int srcX0
, int srcY0
,
343 int dstX0
, int dstY0
,
344 int width
, int height
)
346 struct gl_context
*ctx
= &brw
->ctx
;
347 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
348 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
350 /* Sync up the state of window system buffers. We need to do this before
351 * we go looking at the src renderbuffer's miptree.
353 intel_prepare_render(brw
);
355 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
356 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
358 /* BLORP is not supported before Gen6. */
359 if (brw
->gen
< 6 || brw
->gen
>= 8)
362 if (_mesa_get_format_base_format(src_mt
->format
) !=
363 _mesa_get_format_base_format(dst_mt
->format
)) {
367 /* We can't handle format conversions between Z24 and other formats since
368 * we have to lie about the surface format. See the comments in
369 * brw_blorp_surface_info::set().
371 if ((src_mt
->format
== MESA_FORMAT_X8_Z24
) !=
372 (dst_mt
->format
== MESA_FORMAT_X8_Z24
)) {
376 if (!brw
->format_supported_as_render_target
[dst_mt
->format
])
379 /* Source clipping shouldn't be necessary, since copytexsubimage (in
380 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
383 * Destination clipping shouldn't be necessary since the restrictions on
384 * glCopyTexSubImage prevent the user from specifying a destination rectangle
385 * that falls outside the bounds of the destination texture.
386 * See error_check_subtexture_dimensions().
389 int srcY1
= srcY0
+ height
;
390 int srcX1
= srcX0
+ width
;
391 int dstX1
= dstX0
+ width
;
392 int dstY1
= dstY0
+ height
;
394 /* Account for the fact that in the system framebuffer, the origin is at
397 bool mirror_y
= false;
398 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
399 GLint tmp
= src_rb
->Height
- srcY0
;
400 srcY0
= src_rb
->Height
- srcY1
;
405 brw_blorp_blit_miptrees(brw
,
406 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
407 dst_mt
, dst_image
->Level
, dst_image
->Face
+ slice
,
408 srcX0
, srcY0
, srcX1
, srcY1
,
409 dstX0
, dstY0
, dstX1
, dstY1
,
410 GL_NEAREST
, false, mirror_y
);
412 /* If we're copying to a packed depth stencil texture and the source
413 * framebuffer has separate stencil, we need to also copy the stencil data
416 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
417 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
419 src_irb
= intel_renderbuffer(src_rb
);
420 src_mt
= src_irb
->mt
;
422 if (src_mt
->stencil_mt
)
423 src_mt
= src_mt
->stencil_mt
;
424 if (dst_mt
->stencil_mt
)
425 dst_mt
= dst_mt
->stencil_mt
;
427 if (src_mt
!= dst_mt
) {
428 brw_blorp_blit_miptrees(brw
,
429 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
430 dst_mt
, dst_image
->Level
,
431 dst_image
->Face
+ slice
,
432 srcX0
, srcY0
, srcX1
, srcY1
,
433 dstX0
, dstY0
, dstX1
, dstY1
,
434 GL_NEAREST
, false, mirror_y
);
443 brw_blorp_framebuffer(struct brw_context
*brw
,
444 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
445 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
446 GLbitfield mask
, GLenum filter
)
448 /* BLORP is not supported before Gen6. */
449 if (brw
->gen
< 6 || brw
->gen
>= 8)
452 static GLbitfield buffer_bits
[] = {
455 GL_STENCIL_BUFFER_BIT
,
458 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
459 if ((mask
& buffer_bits
[i
]) &&
461 srcX0
, srcY0
, srcX1
, srcY1
,
462 dstX0
, dstY0
, dstX1
, dstY1
,
463 filter
, buffer_bits
[i
])) {
464 mask
&= ~buffer_bits
[i
];
473 * Enum to specify the order of arguments in a sampler message
475 enum sampler_message_arg
477 SAMPLER_MESSAGE_ARG_U_FLOAT
,
478 SAMPLER_MESSAGE_ARG_V_FLOAT
,
479 SAMPLER_MESSAGE_ARG_U_INT
,
480 SAMPLER_MESSAGE_ARG_V_INT
,
481 SAMPLER_MESSAGE_ARG_SI_INT
,
482 SAMPLER_MESSAGE_ARG_MCS_INT
,
483 SAMPLER_MESSAGE_ARG_ZERO_INT
,
487 * Generator for WM programs used in BLORP blits.
489 * The bulk of the work done by the WM program is to wrap and unwrap the
490 * coordinate transformations used by the hardware to store surfaces in
491 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
492 * sample index for a multisampled surface) to a memory offset by the
493 * following formulas:
495 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
496 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
498 * For a single-sampled surface, or for a multisampled surface using
499 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
502 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
503 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
504 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
505 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
507 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
508 * embeds the sample number into bit 1 of the X and Y coordinates:
510 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
511 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
512 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
513 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
514 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
515 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
516 * S = (Y & 0b10) | (X & 0b10) >> 1
518 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
519 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
522 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
523 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
524 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
525 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
526 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
527 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
528 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
530 * For X tiling, tile() combines together the low-order bits of the X and Y
531 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
532 * bytes wide and 8 rows high:
534 * tile(x_tiled, X, Y, S) = A
535 * where A = tile_num << 12 | offset
536 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
537 * offset = (Y' & 0b111) << 9
538 * | (X & 0b111111111)
540 * Y' = Y + S * qpitch
541 * detile(x_tiled, A) = (X, Y, S)
545 * Y' = (tile_num / tile_pitch) << 3
546 * | (A & 0b111000000000) >> 9
547 * X' = (tile_num % tile_pitch) << 9
548 * | (A & 0b111111111)
550 * (In all tiling formulas, cpp is the number of bytes occupied by a single
551 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
552 * to fill the width of the surface, and qpitch is the spacing (in rows)
553 * between array slices).
555 * For Y tiling, tile() combines together the low-order bits of the X and Y
556 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
557 * bytes wide and 32 rows high:
559 * tile(y_tiled, X, Y, S) = A
560 * where A = tile_num << 12 | offset
561 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
562 * offset = (X' & 0b1110000) << 5
563 * | (Y' & 0b11111) << 4
566 * Y' = Y + S * qpitch
567 * detile(y_tiled, A) = (X, Y, S)
571 * Y' = (tile_num / tile_pitch) << 5
572 * | (A & 0b111110000) >> 4
573 * X' = (tile_num % tile_pitch) << 7
574 * | (A & 0b111000000000) >> 5
577 * For W tiling, tile() combines together the low-order bits of the X and Y
578 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
579 * bytes wide and 64 rows high (note that W tiling is only used for stencil
580 * buffers, which always have cpp = 1 and S=0):
582 * tile(w_tiled, X, Y, S) = A
583 * where A = tile_num << 12 | offset
584 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
585 * offset = (X' & 0b111000) << 6
586 * | (Y' & 0b111100) << 3
587 * | (X' & 0b100) << 2
593 * Y' = Y + S * qpitch
594 * detile(w_tiled, A) = (X, Y, S)
595 * where X = X' / cpp = X'
596 * Y = Y' % qpitch = Y'
598 * Y' = (tile_num / tile_pitch) << 6
599 * | (A & 0b111100000) >> 3
600 * | (A & 0b1000) >> 2
602 * X' = (tile_num % tile_pitch) << 6
603 * | (A & 0b111000000000) >> 6
604 * | (A & 0b10000) >> 2
608 * Finally, for a non-tiled surface, tile() simply combines together the X and
609 * Y coordinates in the natural way:
611 * tile(untiled, X, Y, S) = A
612 * where A = Y * pitch + X'
614 * Y' = Y + S * qpitch
615 * detile(untiled, A) = (X, Y, S)
622 * (In these formulas, pitch is the number of bytes occupied by a single row
625 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
628 brw_blorp_blit_program(struct brw_context
*brw
,
629 const brw_blorp_blit_prog_key
*key
);
631 const GLuint
*compile(struct brw_context
*brw
, GLuint
*program_size
,
632 FILE *dump_file
= stdout
);
634 brw_blorp_prog_data prog_data
;
638 void alloc_push_const_regs(int base_reg
);
639 void compute_frag_coords();
640 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
641 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
642 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
643 void translate_dst_to_src();
644 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
645 struct brw_reg clampX0
, struct brw_reg clampY0
,
646 struct brw_reg clampX1
, struct brw_reg clampY1
);
647 void single_to_blend();
648 void manual_blend_average(unsigned num_samples
);
649 void manual_blend_bilinear(unsigned num_samples
);
650 void sample(struct brw_reg dst
);
651 void texel_fetch(struct brw_reg dst
);
653 void texture_lookup(struct brw_reg dst
, enum opcode op
,
654 const sampler_message_arg
*args
, int num_args
);
655 void render_target_write();
658 * Base-2 logarithm of the maximum number of samples that can be blended.
660 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
662 struct brw_context
*brw
;
663 const brw_blorp_blit_prog_key
*key
;
665 /* Thread dispatch header */
668 /* Pixel X/Y coordinates (always in R1). */
672 struct brw_reg dst_x0
;
673 struct brw_reg dst_x1
;
674 struct brw_reg dst_y0
;
675 struct brw_reg dst_y1
;
676 /* Top right coordinates of the rectangular grid used for scaled blitting */
677 struct brw_reg rect_grid_x1
;
678 struct brw_reg rect_grid_y1
;
680 struct brw_reg multiplier
;
681 struct brw_reg offset
;
682 } x_transform
, y_transform
;
684 /* Data read from texture (4 vec16's per array element) */
685 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
687 /* Auxiliary storage for the contents of the MCS surface.
689 * Since the sampler always returns 8 registers worth of data, this is 8
690 * registers wide, even though we only use the first 2 registers of it.
692 struct brw_reg mcs_data
;
694 /* X coordinates. We have two of them so that we can perform coordinate
695 * transformations easily.
697 struct brw_reg x_coords
[2];
699 /* Y coordinates. We have two of them so that we can perform coordinate
700 * transformations easily.
702 struct brw_reg y_coords
[2];
704 /* X, Y coordinates of the pixel from which we need to fetch the specific
705 * sample. These are used for multisample scaled blitting.
707 struct brw_reg x_sample_coords
;
708 struct brw_reg y_sample_coords
;
710 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
711 struct brw_reg x_frac
;
712 struct brw_reg y_frac
;
714 /* Which element of x_coords and y_coords is currently in use.
718 /* True if, at the point in the program currently being compiled, the
719 * sample index is known to be zero.
723 /* Register storing the sample index when s_is_zero is false. */
724 struct brw_reg sample_index
;
730 /* MRF used for sampling and render target writes */
734 brw_blorp_blit_program::brw_blorp_blit_program(
735 struct brw_context
*brw
,
736 const brw_blorp_blit_prog_key
*key
)
737 : brw_blorp_eu_emitter(brw
),
744 brw_blorp_blit_program::compile(struct brw_context
*brw
,
745 GLuint
*program_size
,
749 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
750 /* If the destination image is W tiled and multisampled, then the thread
751 * must be dispatched once per sample, not once per pixel. This is
752 * necessary because after conversion between W and Y tiling, there's no
753 * guarantee that all samples corresponding to a single pixel will still
756 assert(key
->persample_msaa_dispatch
);
760 /* We are blending, which means we won't have an opportunity to
761 * translate the tiling and sample count for the texture surface. So
762 * the surface state for the texture must be configured with the correct
763 * tiling and sample count.
765 assert(!key
->src_tiled_w
);
766 assert(key
->tex_samples
== key
->src_samples
);
767 assert(key
->tex_layout
== key
->src_layout
);
768 assert(key
->tex_samples
> 0);
771 if (key
->persample_msaa_dispatch
) {
772 /* It only makes sense to do persample dispatch if the render target is
773 * configured as multisampled.
775 assert(key
->rt_samples
> 0);
778 /* Make sure layout is consistent with sample count */
779 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
780 (key
->tex_samples
== 0));
781 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
782 (key
->rt_samples
== 0));
783 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
784 (key
->src_samples
== 0));
785 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
786 (key
->dst_samples
== 0));
788 /* Set up prog_data */
789 memset(&prog_data
, 0, sizeof(prog_data
));
790 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
793 compute_frag_coords();
795 /* Render target and texture hardware don't support W tiling. */
796 const bool rt_tiled_w
= false;
797 const bool tex_tiled_w
= false;
799 /* The address that data will be written to is determined by the
800 * coordinates supplied to the WM thread and the tiling and sample count of
801 * the render target, according to the formula:
803 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
805 * If the actual tiling and sample count of the destination surface are not
806 * the same as the configuration of the render target, then these
807 * coordinates are wrong and we have to adjust them to compensate for the
810 if (rt_tiled_w
!= key
->dst_tiled_w
||
811 key
->rt_samples
!= key
->dst_samples
||
812 key
->rt_layout
!= key
->dst_layout
) {
813 encode_msaa(key
->rt_samples
, key
->rt_layout
);
814 /* Now (X, Y, S) = detile(rt_tiling, offset) */
815 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
816 /* Now (X, Y, S) = detile(dst_tiling, offset) */
817 decode_msaa(key
->dst_samples
, key
->dst_layout
);
820 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
822 * That is: X, Y and S now contain the true coordinates and sample index of
823 * the data that the WM thread should output.
825 * If we need to kill pixels that are outside the destination rectangle,
826 * now is the time to do it.
830 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
831 y_coords
[xy_coord_index
],
832 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
834 /* Next, apply a translation to obtain coordinates in the source image. */
835 translate_dst_to_src();
837 /* If the source image is not multisampled, then we want to fetch sample
838 * number 0, because that's the only sample there is.
840 if (key
->src_samples
== 0)
843 /* X, Y, and S are now the coordinates of the pixel in the source image
844 * that we want to texture from. Exception: if we are blending, then S is
845 * irrelevant, because we are going to fetch all samples.
847 if (key
->blend
&& !key
->blit_scaled
) {
849 /* Gen6 hardware an automatically blend using the SAMPLE message */
851 sample(texture_data
[0]);
853 /* Gen7+ hardware doesn't automaticaly blend. */
854 manual_blend_average(key
->src_samples
);
856 } else if(key
->blend
&& key
->blit_scaled
) {
857 manual_blend_bilinear(key
->src_samples
);
859 /* We aren't blending, which means we just want to fetch a single sample
860 * from the source surface. The address that we want to fetch from is
861 * related to the X, Y and S values according to the formula:
863 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
865 * If the actual tiling and sample count of the source surface are not
866 * the same as the configuration of the texture, then we need to adjust
867 * the coordinates to compensate for the difference.
869 if ((tex_tiled_w
!= key
->src_tiled_w
||
870 key
->tex_samples
!= key
->src_samples
||
871 key
->tex_layout
!= key
->src_layout
) &&
872 !key
->bilinear_filter
) {
873 encode_msaa(key
->src_samples
, key
->src_layout
);
874 /* Now (X, Y, S) = detile(src_tiling, offset) */
875 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
876 /* Now (X, Y, S) = detile(tex_tiling, offset) */
877 decode_msaa(key
->tex_samples
, key
->tex_layout
);
880 if (key
->bilinear_filter
) {
881 sample(texture_data
[0]);
884 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
886 * In other words: X, Y, and S now contain values which, when passed to
887 * the texturing unit, will cause data to be read from the correct
888 * memory location. So we can fetch the texel now.
890 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
892 texel_fetch(texture_data
[0]);
896 /* Finally, write the fetched (or blended) value to the render target and
897 * terminate the thread.
899 render_target_write();
901 return get_program(program_size
, dump_file
);
905 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
907 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
908 #define ALLOC_REG(name, type) \
910 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
911 base_reg + CONST_LOC(name) / 32, \
912 (CONST_LOC(name) % 32) / 4), type)
914 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
915 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
916 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
917 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
918 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
919 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
920 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
921 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
922 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
923 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
929 brw_blorp_blit_program::alloc_regs()
932 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
933 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
934 prog_data
.first_curbe_grf
= reg
;
935 alloc_push_const_regs(reg
);
936 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
937 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
938 this->texture_data
[i
] =
939 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
943 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
945 for (int i
= 0; i
< 2; ++i
) {
947 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
950 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
954 if (key
->blit_scaled
&& key
->blend
) {
955 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
957 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
959 this->x_frac
= brw_vec8_grf(reg
, 0);
961 this->y_frac
= brw_vec8_grf(reg
, 0);
965 this->xy_coord_index
= 0;
967 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
969 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
971 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
974 /* Make sure we didn't run out of registers */
975 assert(reg
<= GEN7_MRF_HACK_START
);
978 this->base_mrf
= mrf
;
981 /* In the code that follows, X and Y can be used to quickly refer to the
982 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
983 * prime") to the inactive elements.
985 * S can be used to quickly refer to sample_index.
987 #define X x_coords[xy_coord_index]
988 #define Y y_coords[xy_coord_index]
989 #define Xp x_coords[!xy_coord_index]
990 #define Yp y_coords[!xy_coord_index]
991 #define S sample_index
993 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
994 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
996 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
999 * Emit code to compute the X and Y coordinates of the pixels being rendered
1000 * by this WM invocation.
1002 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1003 * related to the address offset where outputs will be written by the formula:
1005 * (X, Y, S) = decode_msaa(detile(offset)).
1007 * (See brw_blorp_blit_program).
1010 brw_blorp_blit_program::compute_frag_coords()
1012 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1013 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1014 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1015 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1017 * Pixels within a subspan are laid out in this arrangement:
1021 * So, to compute the coordinates of each pixel, we need to read every 2nd
1022 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1023 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1024 * In other words, the data we want to access is R1.4<2;4,0>UW.
1026 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1027 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1029 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1030 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1032 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1033 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1034 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1037 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1038 * pixels n+2 and n+3 are in the bottom half of the subspan.
1040 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1041 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1043 /* Move the coordinates to UD registers. */
1044 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1045 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1048 if (key
->persample_msaa_dispatch
) {
1049 switch (key
->rt_samples
) {
1051 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1052 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1053 * represent sample 1, and so on.
1055 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1056 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1057 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1058 * then copy from it using vstride=1, width=4, hstride=0.
1060 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1061 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
1062 /* Move to UD sample_index register. */
1063 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
1064 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1068 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1069 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1070 * subspan 1 will represent sample 1, and so on. We can find the
1071 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1072 * Index") and multiplying by two (since samples are always delivered
1073 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1076 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1077 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1078 * variable with the sequence (0, 1, 2, 3), and then reading from it
1079 * using vstride=1, width=4, hstride=0.
1081 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1082 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1083 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1084 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1085 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
1086 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
1087 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1088 stride(t2_uw1
, 1, 4, 0));
1089 emit_add_8(offset(S
, 1),
1090 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1091 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1095 assert(!"Unrecognized sample count in "
1096 "brw_blorp_blit_program::compute_frag_coords()");
1101 /* Either the destination surface is single-sampled, or the WM will be
1102 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1103 * per pixel). In either case, it's not meaningful to compute a sample
1104 * value. Just set it to 0.
1111 * Emit code to compensate for the difference between Y and W tiling.
1113 * This code modifies the X and Y coordinates according to the formula:
1115 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1117 * (See brw_blorp_blit_program).
1119 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1120 * are booleans where true represents W tiling and false represents Y tiling.
1123 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1125 if (old_tiled_w
== new_tiled_w
)
1128 /* In the code that follows, we can safely assume that S = 0, because W
1129 * tiling formats always use IMS layout.
1134 /* Given X and Y coordinates that describe an address using Y tiling,
1135 * translate to the X and Y coordinates that describe the same address
1138 * If we break down the low order bits of X and Y, using a
1139 * single letter to represent each low-order bit:
1141 * X = A << 7 | 0bBCDEFGH
1142 * Y = J << 5 | 0bKLMNP (1)
1144 * Then we can apply the Y tiling formula to see the memory offset being
1147 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1149 * If we apply the W detiling formula to this memory location, that the
1150 * corresponding X' and Y' coordinates are:
1152 * X' = A << 6 | 0bBCDPFH (3)
1153 * Y' = J << 6 | 0bKLMNEG
1155 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1156 * we need to make the following computation:
1158 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1159 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1161 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1162 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1163 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1164 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1165 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1166 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1167 emit_or(Xp
, t1
, t2
);
1168 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1169 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1170 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1171 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1172 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1173 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1174 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1175 emit_or(Yp
, t1
, t2
);
1178 /* Applying the same logic as above, but in reverse, we obtain the
1181 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1182 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1184 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1185 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1186 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1187 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1188 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1189 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1190 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1191 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1193 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1194 emit_or(Xp
, t1
, t2
);
1195 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1196 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1197 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1198 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1199 emit_or(Yp
, t1
, t2
);
1205 * Emit code to compensate for the difference between MSAA and non-MSAA
1208 * This code modifies the X and Y coordinates according to the formula:
1210 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1212 * (See brw_blorp_blit_program).
1215 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1216 intel_msaa_layout layout
)
1219 case INTEL_MSAA_LAYOUT_NONE
:
1220 /* No translation necessary, and S should already be zero. */
1223 case INTEL_MSAA_LAYOUT_CMS
:
1224 /* We can't compensate for compressed layout since at this point in the
1225 * program we haven't read from the MCS buffer.
1227 assert(!"Bad layout in encode_msaa");
1229 case INTEL_MSAA_LAYOUT_UMS
:
1230 /* No translation necessary. */
1232 case INTEL_MSAA_LAYOUT_IMS
:
1233 switch (num_samples
) {
1235 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1236 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1237 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1239 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1241 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1242 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1244 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1246 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1247 emit_or(Xp
, t1
, t2
);
1248 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1249 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1251 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1252 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1254 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1255 emit_or(Yp
, t1
, t2
);
1258 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1259 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1261 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1263 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1264 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1266 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1267 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1268 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1269 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1270 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1273 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1274 emit_or(Xp
, t1
, t2
);
1275 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1276 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1278 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1279 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1281 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1282 emit_or(Yp
, t1
, t2
);
1292 * Emit code to compensate for the difference between MSAA and non-MSAA
1295 * This code modifies the X and Y coordinates according to the formula:
1297 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1299 * (See brw_blorp_blit_program).
1302 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1303 intel_msaa_layout layout
)
1306 case INTEL_MSAA_LAYOUT_NONE
:
1307 /* No translation necessary, and S should already be zero. */
1310 case INTEL_MSAA_LAYOUT_CMS
:
1311 /* We can't compensate for compressed layout since at this point in the
1312 * program we don't have access to the MCS buffer.
1314 assert(!"Bad layout in encode_msaa");
1316 case INTEL_MSAA_LAYOUT_UMS
:
1317 /* No translation necessary. */
1319 case INTEL_MSAA_LAYOUT_IMS
:
1321 switch (num_samples
) {
1323 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1324 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1325 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1326 * S = (Y & 0b10) | (X & 0b10) >> 1
1328 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1329 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1330 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1331 emit_or(Xp
, t1
, t2
);
1332 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1333 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1334 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1335 emit_or(Yp
, t1
, t2
);
1336 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1337 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1338 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1342 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1343 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1344 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1345 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1347 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1348 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1349 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1350 emit_or(Xp
, t1
, t2
);
1351 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1352 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1353 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1354 emit_or(Yp
, t1
, t2
);
1355 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1356 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1357 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1358 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1359 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1370 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1374 brw_blorp_blit_program::translate_dst_to_src()
1376 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1377 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1378 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1379 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1381 /* Move the UD coordinates to float registers. */
1384 /* Scale and offset */
1385 emit_mul(X_f
, Xp_f
, x_transform
.multiplier
);
1386 emit_mul(Y_f
, Yp_f
, y_transform
.multiplier
);
1387 emit_add(X_f
, X_f
, x_transform
.offset
);
1388 emit_add(Y_f
, Y_f
, y_transform
.offset
);
1389 if (key
->blit_scaled
&& key
->blend
) {
1390 /* Translate coordinates to lay out the samples in a rectangular grid
1391 * roughly corresponding to sample locations.
1393 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1394 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1395 /* Adjust coordinates so that integers represent pixel centers rather
1398 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1399 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1401 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1402 * texels on texture edges.
1404 clamp_tex_coords(X_f
, Y_f
,
1405 brw_imm_f(0.0), brw_imm_f(0.0),
1406 rect_grid_x1
, rect_grid_y1
);
1408 /* Store the fractional parts to be used as bilinear interpolation
1411 emit_frc(x_frac
, X_f
);
1412 emit_frc(y_frac
, Y_f
);
1414 /* Round the float coordinates down to nearest integer */
1415 emit_rndd(Xp_f
, X_f
);
1416 emit_rndd(Yp_f
, Y_f
);
1417 emit_mul(X_f
, Xp_f
, brw_imm_f(1 / key
->x_scale
));
1418 emit_mul(Y_f
, Yp_f
, brw_imm_f(1 / key
->y_scale
));
1420 } else if (!key
->bilinear_filter
) {
1421 /* Round the float coordinates down to nearest integer by moving to
1431 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1432 struct brw_reg regY
,
1433 struct brw_reg clampX0
,
1434 struct brw_reg clampY0
,
1435 struct brw_reg clampX1
,
1436 struct brw_reg clampY1
)
1438 emit_cond_mov(regX
, clampX0
, BRW_CONDITIONAL_L
, regX
, clampX0
);
1439 emit_cond_mov(regX
, clampX1
, BRW_CONDITIONAL_G
, regX
, clampX1
);
1440 emit_cond_mov(regY
, clampY0
, BRW_CONDITIONAL_L
, regY
, clampY0
);
1441 emit_cond_mov(regY
, clampY1
, BRW_CONDITIONAL_G
, regY
, clampY1
);
1445 * Emit code to transform the X and Y coordinates as needed for blending
1446 * together the different samples in an MSAA texture.
1449 brw_blorp_blit_program::single_to_blend()
1451 /* When looking up samples in an MSAA texture using the SAMPLE message,
1452 * Gen6 requires the texture coordinates to be odd integers (so that they
1453 * correspond to the center of a 2x2 block representing the four samples
1454 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1455 * each by 2 and then add 1.
1457 emit_shl(t1
, X
, brw_imm_w(1));
1458 emit_shl(t2
, Y
, brw_imm_w(1));
1459 emit_add(Xp
, t1
, brw_imm_w(1));
1460 emit_add(Yp
, t2
, brw_imm_w(1));
1466 * Count the number of trailing 1 bits in the given value. For example:
1468 * count_trailing_one_bits(0) == 0
1469 * count_trailing_one_bits(7) == 3
1470 * count_trailing_one_bits(11) == 2
1472 inline int count_trailing_one_bits(unsigned value
)
1474 #if defined(__GNUC__) && ((__GNUC__ * 100 + __GNUC_MINOR__) >= 304) /* gcc 3.4 or later */
1475 return __builtin_ctz(~value
);
1477 return _mesa_bitcount(value
& ~(value
+ 1));
1483 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1485 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1488 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1490 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1492 * This ensures that when all samples have the same value, no numerical
1493 * precision is lost, since each addition operation always adds two equal
1494 * values, and summing two equal floating point values does not lose
1497 * We perform this computation by treating the texture_data array as a
1498 * stack and performing the following operations:
1500 * - push sample 0 onto stack
1501 * - push sample 1 onto stack
1502 * - add top two stack entries
1503 * - push sample 2 onto stack
1504 * - push sample 3 onto stack
1505 * - add top two stack entries
1506 * - add top two stack entries
1507 * - divide top stack entry by 4
1509 * Note that after pushing sample i onto the stack, the number of add
1510 * operations we do is equal to the number of trailing 1 bits in i. This
1511 * works provided the total number of samples is a power of two, which it
1512 * always is for i965.
1514 * For integer formats, we replace the add operations with average
1515 * operations and skip the final division.
1517 unsigned stack_depth
= 0;
1518 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1519 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1521 /* Push sample i onto the stack */
1522 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1527 emit_mov(vec16(S
), brw_imm_ud(i
));
1529 texel_fetch(texture_data
[stack_depth
++]);
1531 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1532 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1533 * suggests an optimization:
1535 * "A simple optimization with probable large return in
1536 * performance is to compare the MCS value to zero (indicating
1537 * all samples are on sample slice 0), and sample only from
1538 * sample slice 0 using ld2dss if MCS is zero."
1540 * Note that in the case where the MCS value is zero, sampling from
1541 * sample slice 0 using ld2dss and sampling from sample 0 using
1542 * ld2dms are equivalent (since all samples are on sample slice 0).
1543 * Since we have already sampled from sample 0, all we need to do is
1544 * skip the remaining fetches and averaging if MCS is zero.
1546 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1549 /* Do count_trailing_one_bits(i) times */
1550 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1551 assert(stack_depth
>= 2);
1554 /* TODO: should use a smaller loop bound for non_RGBA formats */
1555 for (int k
= 0; k
< 4; ++k
) {
1556 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1557 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1558 offset(texture_data
[stack_depth
- 1], 2*k
),
1559 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1560 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1565 /* We should have just 1 sample on the stack now. */
1566 assert(stack_depth
== 1);
1568 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1569 /* Scale the result down by a factor of num_samples */
1570 /* TODO: should use a smaller loop bound for non-RGBA formats */
1571 for (int j
= 0; j
< 4; ++j
) {
1572 emit_mul(offset(texture_data
[0], 2*j
),
1573 offset(vec8(texture_data
[0]), 2*j
),
1574 brw_imm_f(1.0/num_samples
));
1578 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1583 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1585 /* We do this computation by performing the following operations:
1587 * In case of 4x, 8x MSAA:
1588 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1589 * which are later used for interpolation
1590 * - linearly interpolate samples a and b in X
1591 * - linearly interpolate samples c and d in X
1592 * - linearly interpolate the results of last two operations in Y
1594 * result = lrp(lrp(a + b) + lrp(c + d))
1596 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1597 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1598 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1599 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1601 for (unsigned i
= 0; i
< 4; ++i
) {
1602 assert(i
< ARRAY_SIZE(texture_data
));
1605 /* Compute pixel coordinates */
1606 emit_add(vec16(x_sample_coords
), Xp_f
,
1607 brw_imm_f((float)(i
& 0x1) * (1.0 / key
->x_scale
)));
1608 emit_add(vec16(y_sample_coords
), Yp_f
,
1609 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0 / key
->y_scale
)));
1610 emit_mov(vec16(X
), x_sample_coords
);
1611 emit_mov(vec16(Y
), y_sample_coords
);
1613 /* The MCS value we fetch has to match up with the pixel that we're
1614 * sampling from. Since we sample from different pixels in each
1615 * iteration of this "for" loop, the call to mcs_fetch() should be
1616 * here inside the loop after computing the pixel coordinates.
1618 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1621 /* Compute sample index and map the sample index to a sample number.
1622 * Sample index layout shows the numbering of slots in a rectangular
1623 * grid of samples with in a pixel. Sample number layout shows the
1624 * rectangular grid of samples roughly corresponding to the real sample
1625 * locations with in a pixel.
1626 * In case of 4x MSAA, layout of sample indices matches the layout of
1634 * In case of 8x MSAA the two layouts don't match.
1635 * sample index layout : --------- sample number layout : ---------
1636 * | 0 | 1 | | 5 | 2 |
1637 * --------- ---------
1638 * | 2 | 3 | | 4 | 6 |
1639 * --------- ---------
1640 * | 4 | 5 | | 0 | 3 |
1641 * --------- ---------
1642 * | 6 | 7 | | 7 | 1 |
1643 * --------- ---------
1645 emit_frc(vec16(t1_f
), x_sample_coords
);
1646 emit_frc(vec16(t2_f
), y_sample_coords
);
1647 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1648 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1649 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1650 emit_mov(vec16(S
), t1_f
);
1652 if (num_samples
== 8) {
1653 /* Map the sample index to a sample number */
1654 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1656 emit_mov(vec16(t2
), brw_imm_d(5));
1657 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1658 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1659 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1663 emit_mov(vec16(t2
), brw_imm_d(0));
1664 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1665 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1666 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1669 emit_mov(vec16(S
), t2
);
1671 texel_fetch(texture_data
[i
]);
1674 #define SAMPLE(x, y) offset(texture_data[x], y)
1675 for (int index
= 3; index
> 0; ) {
1676 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1677 * Counter value of 8 in 'for' loop below is used to interpolate all
1678 * the color components.
1680 for (int k
= 0; k
< 8; k
+= 2)
1681 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1683 vec8(SAMPLE(index
, k
)),
1684 vec8(SAMPLE(index
- 1, k
)));
1687 for (int k
= 0; k
< 8; k
+= 2)
1688 emit_lrp(vec8(SAMPLE(0, k
)),
1691 vec8(SAMPLE(0, k
)));
1696 * Emit code to look up a value in the texture using the SAMPLE message (which
1697 * does blending of MSAA surfaces).
1700 brw_blorp_blit_program::sample(struct brw_reg dst
)
1702 static const sampler_message_arg args
[2] = {
1703 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1704 SAMPLER_MESSAGE_ARG_V_FLOAT
1707 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1711 * Emit code to look up a value in the texture using the SAMPLE_LD message
1712 * (which does a simple texel fetch).
1715 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1717 static const sampler_message_arg gen6_args
[5] = {
1718 SAMPLER_MESSAGE_ARG_U_INT
,
1719 SAMPLER_MESSAGE_ARG_V_INT
,
1720 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1721 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1722 SAMPLER_MESSAGE_ARG_SI_INT
1724 static const sampler_message_arg gen7_ld_args
[3] = {
1725 SAMPLER_MESSAGE_ARG_U_INT
,
1726 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1727 SAMPLER_MESSAGE_ARG_V_INT
1729 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1730 SAMPLER_MESSAGE_ARG_SI_INT
,
1731 SAMPLER_MESSAGE_ARG_U_INT
,
1732 SAMPLER_MESSAGE_ARG_V_INT
1734 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1735 SAMPLER_MESSAGE_ARG_SI_INT
,
1736 SAMPLER_MESSAGE_ARG_MCS_INT
,
1737 SAMPLER_MESSAGE_ARG_U_INT
,
1738 SAMPLER_MESSAGE_ARG_V_INT
1743 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1746 switch (key
->tex_layout
) {
1747 case INTEL_MSAA_LAYOUT_IMS
:
1748 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1751 * If this field is MSFMT_DEPTH_STENCIL
1752 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1753 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1755 * So fall through to emit the same message as we use for
1756 * INTEL_MSAA_LAYOUT_CMS.
1758 case INTEL_MSAA_LAYOUT_CMS
:
1759 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1760 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1762 case INTEL_MSAA_LAYOUT_UMS
:
1763 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1764 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1766 case INTEL_MSAA_LAYOUT_NONE
:
1768 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1769 ARRAY_SIZE(gen7_ld_args
));
1774 assert(!"Should not get here.");
1780 brw_blorp_blit_program::mcs_fetch()
1782 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1783 SAMPLER_MESSAGE_ARG_U_INT
,
1784 SAMPLER_MESSAGE_ARG_V_INT
1786 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1787 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1791 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1793 const sampler_message_arg
*args
,
1796 struct brw_reg mrf
=
1797 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1798 for (int arg
= 0; arg
< num_args
; ++arg
) {
1799 switch (args
[arg
]) {
1800 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1801 if (key
->bilinear_filter
)
1802 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1803 retype(X
, BRW_REGISTER_TYPE_F
));
1805 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1807 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1808 if (key
->bilinear_filter
)
1809 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1810 retype(Y
, BRW_REGISTER_TYPE_F
));
1812 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1814 case SAMPLER_MESSAGE_ARG_U_INT
:
1817 case SAMPLER_MESSAGE_ARG_V_INT
:
1820 case SAMPLER_MESSAGE_ARG_SI_INT
:
1821 /* Note: on Gen7, this code may be reached with s_is_zero==true
1822 * because in Gen7's ld2dss message, the sample index is the first
1823 * argument. When this happens, we need to move a 0 into the
1824 * appropriate message register.
1827 emit_mov(mrf
, brw_imm_ud(0));
1831 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1832 switch (key
->tex_layout
) {
1833 case INTEL_MSAA_LAYOUT_CMS
:
1834 emit_mov(mrf
, mcs_data
);
1836 case INTEL_MSAA_LAYOUT_IMS
:
1837 /* When sampling from an IMS surface, MCS data is not relevant,
1838 * and the hardware ignores it. So don't bother populating it.
1842 /* We shouldn't be trying to send MCS data with any other
1845 assert (!"Unsupported layout for MCS data");
1849 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1850 emit_mov(mrf
, brw_imm_ud(0));
1856 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1859 mrf
.nr
- base_mrf
/* msg_length */);
1867 #undef SWAP_XY_AND_XPYP
1870 brw_blorp_blit_program::render_target_write()
1872 struct brw_reg mrf_rt_write
=
1873 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1876 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1877 * so that the render target knows which pixels we killed.
1879 bool use_header
= key
->use_kill
;
1881 /* Copy R0/1 to MRF */
1882 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1883 retype(R0
, BRW_REGISTER_TYPE_UD
));
1887 /* Copy texture data to MRFs */
1888 for (int i
= 0; i
< 4; ++i
) {
1889 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1890 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1891 offset(vec8(texture_data
[0]), 2*i
));
1895 /* Now write to the render target and terminate the thread */
1896 emit_render_target_write(
1899 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1905 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1906 GLfloat dst0
, GLfloat dst1
,
1909 float scale
= (src1
- src0
) / (dst1
- dst0
);
1911 /* When not mirroring a coordinate (say, X), we need:
1912 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1914 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1916 * blorp program uses "round toward zero" to convert the
1917 * transformed floating point coordinates to integer coordinates,
1918 * whereas the behaviour we actually want is "round to nearest",
1919 * so 0.5 provides the necessary correction.
1922 offset
= src0
+ (-dst0
+ 0.5) * scale
;
1924 /* When mirroring X we need:
1925 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1927 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1929 multiplier
= -scale
;
1930 offset
= src0
+ (dst1
- 0.5) * scale
;
1936 * Determine which MSAA layout the GPU pipeline should be configured for,
1937 * based on the chip generation, the number of samples, and the true layout of
1938 * the image in memory.
1940 inline intel_msaa_layout
1941 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1942 intel_msaa_layout true_layout
)
1944 if (num_samples
<= 1) {
1945 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1946 * format buffers, by transforming coordinates appropriately.
1948 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1949 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1950 return INTEL_MSAA_LAYOUT_NONE
;
1952 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1955 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1956 if (brw
->gen
== 6) {
1957 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1964 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1965 struct intel_mipmap_tree
*src_mt
,
1966 unsigned src_level
, unsigned src_layer
,
1967 struct intel_mipmap_tree
*dst_mt
,
1968 unsigned dst_level
, unsigned dst_layer
,
1969 GLfloat src_x0
, GLfloat src_y0
,
1970 GLfloat src_x1
, GLfloat src_y1
,
1971 GLfloat dst_x0
, GLfloat dst_y0
,
1972 GLfloat dst_x1
, GLfloat dst_y1
,
1974 bool mirror_x
, bool mirror_y
)
1976 struct gl_context
*ctx
= &brw
->ctx
;
1977 const struct gl_framebuffer
*read_fb
= ctx
->ReadBuffer
;
1979 src
.set(brw
, src_mt
, src_level
, src_layer
, false);
1980 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, true);
1982 /* Even though we do multisample resolves at the time of the blit, OpenGL
1983 * specification defines them as if they happen at the time of rendering,
1984 * which means that the type of averaging we do during the resolve should
1985 * only depend on the source format; the destination format should be
1986 * ignored. But, specification doesn't seem to be strict about it.
1988 * It has been observed that mulitisample resolves produce slightly better
1989 * looking images when averaging is done using destination format. NVIDIA's
1990 * proprietary OpenGL driver also follow this approach. So, we choose to
1991 * follow it in our driver.
1993 * When multisampling, if the source and destination formats are equal
1994 * (aside from the color space), we choose to blit in sRGB space to get
1995 * this higher quality image.
1997 if (src
.num_samples
> 1 &&
1998 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1999 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2000 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2001 dst
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2002 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2005 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
2006 * texture, the above code configures the source format for L32_FLOAT or
2007 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
2008 * the SAMPLE message appears to handle multisampled L32_FLOAT and
2009 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
2010 * around the problem by using a source format of R32_FLOAT. This
2011 * shouldn't affect rendering correctness, since the destination format is
2012 * R32_FLOAT, so only the contents of the red channel matters.
2014 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
2015 src_mt
->format
== dst_mt
->format
&&
2016 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
2017 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
2021 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2023 /* texture_data_type indicates the register type that should be used to
2024 * manipulate texture data.
2026 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2027 case GL_UNSIGNED_NORMALIZED
:
2028 case GL_SIGNED_NORMALIZED
:
2030 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2032 case GL_UNSIGNED_INT
:
2033 if (src_mt
->format
== MESA_FORMAT_S8
) {
2034 /* We process stencil as though it's an unsigned normalized color */
2035 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2037 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2041 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2044 assert(!"Unrecognized blorp format");
2049 /* Gen7's rendering hardware only supports the IMS layout for depth and
2050 * stencil render targets. Blorp always maps its destination surface as
2051 * a color render target (even if it's actually a depth or stencil
2052 * buffer). So if the destination is IMS, we'll have to map it as a
2053 * single-sampled texture and interleave the samples ourselves.
2055 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2056 dst
.num_samples
= 0;
2059 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
2060 /* If the destination surface is a W-tiled multisampled stencil buffer
2061 * that we're mapping as Y tiled, then we need to arrange for the WM
2062 * program to run once per sample rather than once per pixel, because
2063 * the memory layout of related samples doesn't match between W and Y
2066 wm_prog_key
.persample_msaa_dispatch
= true;
2069 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
2070 /* We are blitting from a multisample buffer to a multisample buffer, so
2071 * we must preserve samples within a pixel. This means we have to
2072 * arrange for the WM program to run once per sample rather than once
2075 wm_prog_key
.persample_msaa_dispatch
= true;
2078 /* Scaled blitting or not. */
2079 wm_prog_key
.blit_scaled
=
2080 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2081 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2083 /* Scaling factors used for bilinear filtering in multisample scaled
2086 wm_prog_key
.x_scale
= 2.0;
2087 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0;
2089 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2090 wm_prog_key
.bilinear_filter
= true;
2092 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2093 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2094 base_format
!= GL_STENCIL_INDEX
&&
2095 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2096 /* We are downsampling a color buffer, so blend. */
2097 wm_prog_key
.blend
= true;
2100 /* src_samples and dst_samples are the true sample counts */
2101 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2102 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2104 /* tex_samples and rt_samples are the sample counts that are set up in
2107 wm_prog_key
.tex_samples
= src
.num_samples
;
2108 wm_prog_key
.rt_samples
= dst
.num_samples
;
2110 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2111 * use to access the source and destination surfaces.
2113 wm_prog_key
.tex_layout
=
2114 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2115 wm_prog_key
.rt_layout
=
2116 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2118 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2121 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2122 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2124 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2125 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2126 x0
= wm_push_consts
.dst_x0
= dst_x0
;
2127 y0
= wm_push_consts
.dst_y0
= dst_y0
;
2128 x1
= wm_push_consts
.dst_x1
= dst_x1
;
2129 y1
= wm_push_consts
.dst_y1
= dst_y1
;
2130 wm_push_consts
.rect_grid_x1
= read_fb
->Width
* wm_prog_key
.x_scale
- 1.0;
2131 wm_push_consts
.rect_grid_y1
= read_fb
->Height
* wm_prog_key
.y_scale
- 1.0;
2133 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2134 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2136 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2137 /* We must expand the rectangle we send through the rendering pipeline,
2138 * to account for the fact that we are mapping the destination region as
2139 * single-sampled when it is in fact multisampled. We must also align
2140 * it to a multiple of the multisampling pattern, because the
2141 * differences between multisampled and single-sampled surface formats
2142 * will mean that pixels are scrambled within the multisampling pattern.
2143 * TODO: what if this makes the coordinates too large?
2145 * Note: this only works if the destination surface uses the IMS layout.
2146 * If it's UMS, then we have no choice but to set up the rendering
2147 * pipeline as multisampled.
2149 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2150 switch (dst_mt
->num_samples
) {
2152 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2153 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2154 x1
= ALIGN(x1
* 2, 4);
2155 y1
= ALIGN(y1
* 2, 4);
2158 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2159 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2160 x1
= ALIGN(x1
* 4, 8);
2161 y1
= ALIGN(y1
* 2, 4);
2164 assert(!"Unrecognized sample count in brw_blorp_blit_params ctor");
2167 wm_prog_key
.use_kill
= true;
2170 if (dst
.map_stencil_as_y_tiled
) {
2171 /* We must modify the rectangle we send through the rendering pipeline
2172 * (and the size and x/y offset of the destination surface), to account
2173 * for the fact that we are mapping it as Y-tiled when it is in fact
2176 * Both Y tiling and W tiling can be understood as organizations of
2177 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2178 * is different, but the layout of the 32-byte sub-tiles within the 4k
2179 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2180 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2181 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2183 * Therefore, to account for the layout differences within the 32-byte
2184 * sub-tiles, we must expand the rectangle so the X coordinates of its
2185 * edges are multiples of 8 (the W sub-tile width), and its Y
2186 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2187 * Then we need to scale the X and Y coordinates of the rectangle to
2188 * account for the differences in aspect ratio between the Y and W
2189 * sub-tiles. We need to modify the layer width and height similarly.
2191 * A correction needs to be applied when MSAA is in use: since
2192 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2193 * we need to align the Y coordinates to multiples of 8, so that when
2194 * they are divided by two they are still multiples of 4.
2196 * Note: Since the x/y offset of the surface will be applied using the
2197 * SURFACE_STATE command packet, it will be invisible to the swizzling
2198 * code in the shader; therefore it needs to be in a multiple of the
2199 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2200 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2201 * buffer), and the miplevel alignment used for stencil buffers is 8
2202 * pixels horizontally and either 4 or 8 pixels vertically (see
2203 * intel_horizontal_texture_alignment_unit() and
2204 * intel_vertical_texture_alignment_unit()).
2206 * Note: Also, since the SURFACE_STATE command packet can only apply
2207 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2208 * vertically, it is important that the offsets will be multiples of
2209 * these sizes after they are converted into Y-tiled coordinates.
2210 * Fortunately they will be, since we know from above that the offsets
2211 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2212 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2214 * TODO: what if this makes the coordinates (or the texture size) too
2217 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2218 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2219 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2220 x1
= ALIGN(x1
, x_align
) * 2;
2221 y1
= ALIGN(y1
, y_align
) / 2;
2222 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2223 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2226 wm_prog_key
.use_kill
= true;
2229 if (src
.map_stencil_as_y_tiled
) {
2230 /* We must modify the size and x/y offset of the source surface to
2231 * account for the fact that we are mapping it as Y-tiled when it is in
2234 * See the comments above concerning x/y offset alignment for the
2235 * destination surface.
2237 * TODO: what if this makes the texture size too large?
2239 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2240 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2241 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2248 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2249 brw_blorp_prog_data
**prog_data
) const
2251 uint32_t prog_offset
= 0;
2252 if (!brw_search_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2253 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2254 &prog_offset
, prog_data
)) {
2255 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2256 GLuint program_size
;
2257 const GLuint
*program
= prog
.compile(brw
, &program_size
, stdout
);
2258 brw_upload_cache(&brw
->cache
, BRW_BLORP_BLIT_PROG
,
2259 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2260 program
, program_size
,
2261 &prog
.prog_data
, sizeof(prog
.prog_data
),
2262 &prog_offset
, prog_data
);
2268 brw_blorp_blit_test_compile(struct brw_context
*brw
,
2269 const brw_blorp_blit_prog_key
*key
,
2272 GLuint program_size
;
2273 brw_blorp_blit_program
prog(brw
, key
);
2274 INTEL_DEBUG
|= DEBUG_BLORP
;
2275 prog
.compile(brw
, &program_size
, out
);