2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/fbobject.h"
28 #include "compiler/nir/nir_builder.h"
30 #include "intel_fbo.h"
32 #include "brw_blorp.h"
33 #include "brw_context.h"
34 #include "brw_blorp_blit_eu.h"
35 #include "brw_state.h"
36 #include "brw_meta_util.h"
38 #define FILE_DEBUG_FLAG DEBUG_BLORP
40 static struct intel_mipmap_tree
*
41 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
43 struct intel_mipmap_tree
*mt
= irb
->mt
;
44 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
50 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
52 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
53 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
58 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
59 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
60 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
61 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
62 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
63 GLenum filter
, bool mirror_x
, bool mirror_y
)
65 /* Find source/dst miptrees */
66 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
67 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
69 const bool es3
= _mesa_is_gles3(&brw
->ctx
);
71 brw_blorp_blit_miptrees(brw
,
72 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
73 src_format
, blorp_get_texture_swizzle(src_irb
),
74 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
76 srcX0
, srcY0
, srcX1
, srcY1
,
77 dstX0
, dstY0
, dstX1
, dstY1
,
78 filter
, mirror_x
, mirror_y
,
81 dst_irb
->need_downsample
= true;
85 try_blorp_blit(struct brw_context
*brw
,
86 const struct gl_framebuffer
*read_fb
,
87 const struct gl_framebuffer
*draw_fb
,
88 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
89 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
90 GLenum filter
, GLbitfield buffer_bit
)
92 struct gl_context
*ctx
= &brw
->ctx
;
94 /* Sync up the state of window system buffers. We need to do this before
95 * we go looking for the buffers.
97 intel_prepare_render(brw
);
99 bool mirror_x
, mirror_y
;
100 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
101 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
102 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
103 &mirror_x
, &mirror_y
))
107 struct intel_renderbuffer
*src_irb
;
108 struct intel_renderbuffer
*dst_irb
;
109 struct intel_mipmap_tree
*src_mt
;
110 struct intel_mipmap_tree
*dst_mt
;
111 switch (buffer_bit
) {
112 case GL_COLOR_BUFFER_BIT
:
113 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
114 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
115 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
117 do_blorp_blit(brw
, buffer_bit
,
118 src_irb
, src_irb
->Base
.Base
.Format
,
119 dst_irb
, dst_irb
->Base
.Base
.Format
,
120 srcX0
, srcY0
, srcX1
, srcY1
,
121 dstX0
, dstY0
, dstX1
, dstY1
,
122 filter
, mirror_x
, mirror_y
);
125 case GL_DEPTH_BUFFER_BIT
:
127 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
129 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
130 src_mt
= find_miptree(buffer_bit
, src_irb
);
131 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
133 /* We can't handle format conversions between Z24 and other formats
134 * since we have to lie about the surface format. See the comments in
135 * brw_blorp_surface_info::set().
137 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
138 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
141 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
142 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
143 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
144 filter
, mirror_x
, mirror_y
);
146 case GL_STENCIL_BUFFER_BIT
:
148 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
150 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
151 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
152 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
153 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
154 filter
, mirror_x
, mirror_y
);
157 unreachable("not reached");
164 brw_blorp_copytexsubimage(struct brw_context
*brw
,
165 struct gl_renderbuffer
*src_rb
,
166 struct gl_texture_image
*dst_image
,
168 int srcX0
, int srcY0
,
169 int dstX0
, int dstY0
,
170 int width
, int height
)
172 struct gl_context
*ctx
= &brw
->ctx
;
173 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
174 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
176 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
177 if (brw
->ctx
._ImageTransferState
)
180 /* Sync up the state of window system buffers. We need to do this before
181 * we go looking at the src renderbuffer's miptree.
183 intel_prepare_render(brw
);
185 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
186 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
188 /* There is support for only up to eight samples. */
189 if (src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
192 /* BLORP is only supported from Gen6 onwards. */
196 if (_mesa_get_format_base_format(src_rb
->Format
) !=
197 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
201 /* We can't handle format conversions between Z24 and other formats since
202 * we have to lie about the surface format. See the comments in
203 * brw_blorp_surface_info::set().
205 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
206 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
210 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
213 /* Source clipping shouldn't be necessary, since copytexsubimage (in
214 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
217 * Destination clipping shouldn't be necessary since the restrictions on
218 * glCopyTexSubImage prevent the user from specifying a destination rectangle
219 * that falls outside the bounds of the destination texture.
220 * See error_check_subtexture_dimensions().
223 int srcY1
= srcY0
+ height
;
224 int srcX1
= srcX0
+ width
;
225 int dstX1
= dstX0
+ width
;
226 int dstY1
= dstY0
+ height
;
228 /* Account for the fact that in the system framebuffer, the origin is at
231 bool mirror_y
= false;
232 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
233 GLint tmp
= src_rb
->Height
- srcY0
;
234 srcY0
= src_rb
->Height
- srcY1
;
239 /* Account for face selection and texture view MinLayer */
240 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
241 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
243 brw_blorp_blit_miptrees(brw
,
244 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
245 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
246 dst_mt
, dst_level
, dst_slice
,
247 dst_image
->TexFormat
,
248 srcX0
, srcY0
, srcX1
, srcY1
,
249 dstX0
, dstY0
, dstX1
, dstY1
,
250 GL_NEAREST
, false, mirror_y
,
253 /* If we're copying to a packed depth stencil texture and the source
254 * framebuffer has separate stencil, we need to also copy the stencil data
257 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
258 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
260 src_irb
= intel_renderbuffer(src_rb
);
261 src_mt
= src_irb
->mt
;
263 if (src_mt
->stencil_mt
)
264 src_mt
= src_mt
->stencil_mt
;
265 if (dst_mt
->stencil_mt
)
266 dst_mt
= dst_mt
->stencil_mt
;
268 if (src_mt
!= dst_mt
) {
269 brw_blorp_blit_miptrees(brw
,
270 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
272 blorp_get_texture_swizzle(src_irb
),
273 dst_mt
, dst_level
, dst_slice
,
275 srcX0
, srcY0
, srcX1
, srcY1
,
276 dstX0
, dstY0
, dstX1
, dstY1
,
277 GL_NEAREST
, false, mirror_y
,
287 brw_blorp_framebuffer(struct brw_context
*brw
,
288 struct gl_framebuffer
*readFb
,
289 struct gl_framebuffer
*drawFb
,
290 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
291 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
292 GLbitfield mask
, GLenum filter
)
294 /* BLORP is not supported before Gen6. */
298 /* There is support for only up to eight samples. */
299 if (readFb
->Visual
.samples
> 8 || drawFb
->Visual
.samples
> 8)
302 static GLbitfield buffer_bits
[] = {
305 GL_STENCIL_BUFFER_BIT
,
308 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
309 if ((mask
& buffer_bits
[i
]) &&
310 try_blorp_blit(brw
, readFb
, drawFb
,
311 srcX0
, srcY0
, srcX1
, srcY1
,
312 dstX0
, dstY0
, dstX1
, dstY1
,
313 filter
, buffer_bits
[i
])) {
314 mask
&= ~buffer_bits
[i
];
323 * Enum to specify the order of arguments in a sampler message
325 enum sampler_message_arg
327 SAMPLER_MESSAGE_ARG_U_FLOAT
,
328 SAMPLER_MESSAGE_ARG_V_FLOAT
,
329 SAMPLER_MESSAGE_ARG_U_INT
,
330 SAMPLER_MESSAGE_ARG_V_INT
,
331 SAMPLER_MESSAGE_ARG_R_INT
,
332 SAMPLER_MESSAGE_ARG_SI_INT
,
333 SAMPLER_MESSAGE_ARG_MCS_INT
,
334 SAMPLER_MESSAGE_ARG_ZERO_INT
,
337 struct brw_blorp_blit_vars
{
338 /* Uniforms values from brw_blorp_wm_push_constants */
339 nir_variable
*u_dst_x0
;
340 nir_variable
*u_dst_x1
;
341 nir_variable
*u_dst_y0
;
342 nir_variable
*u_dst_y1
;
343 nir_variable
*u_rect_grid_x1
;
344 nir_variable
*u_rect_grid_y1
;
346 nir_variable
*multiplier
;
347 nir_variable
*offset
;
348 } u_x_transform
, u_y_transform
;
349 nir_variable
*u_src_z
;
352 nir_variable
*frag_coord
;
355 nir_variable
*color_out
;
359 brw_blorp_blit_vars_init(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
360 const struct brw_blorp_blit_prog_key
*key
)
362 #define LOAD_UNIFORM(name, type)\
363 v->u_##name = nir_variable_create(b->shader, nir_var_uniform, type, #name); \
364 v->u_##name->data.location = \
365 offsetof(struct brw_blorp_wm_push_constants, name);
367 LOAD_UNIFORM(dst_x0
, glsl_uint_type())
368 LOAD_UNIFORM(dst_x1
, glsl_uint_type())
369 LOAD_UNIFORM(dst_y0
, glsl_uint_type())
370 LOAD_UNIFORM(dst_y1
, glsl_uint_type())
371 LOAD_UNIFORM(rect_grid_x1
, glsl_float_type())
372 LOAD_UNIFORM(rect_grid_y1
, glsl_float_type())
373 LOAD_UNIFORM(x_transform
.multiplier
, glsl_float_type())
374 LOAD_UNIFORM(x_transform
.offset
, glsl_float_type())
375 LOAD_UNIFORM(y_transform
.multiplier
, glsl_float_type())
376 LOAD_UNIFORM(y_transform
.offset
, glsl_float_type())
377 LOAD_UNIFORM(src_z
, glsl_uint_type())
381 v
->frag_coord
= nir_variable_create(b
->shader
, nir_var_shader_in
,
382 glsl_vec4_type(), "gl_FragCoord");
383 v
->frag_coord
->data
.location
= VARYING_SLOT_POS
;
384 v
->frag_coord
->data
.origin_upper_left
= true;
386 v
->color_out
= nir_variable_create(b
->shader
, nir_var_shader_out
,
387 glsl_vec4_type(), "gl_FragColor");
388 v
->color_out
->data
.location
= FRAG_RESULT_COLOR
;
392 blorp_blit_get_frag_coords(nir_builder
*b
,
393 const struct brw_blorp_blit_prog_key
*key
,
394 struct brw_blorp_blit_vars
*v
)
396 nir_ssa_def
*coord
= nir_f2i(b
, nir_load_var(b
, v
->frag_coord
));
398 if (key
->persample_msaa_dispatch
) {
399 return nir_vec3(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1),
400 nir_load_system_value(b
, nir_intrinsic_load_sample_id
, 0));
402 return nir_vec2(b
, nir_channel(b
, coord
, 0), nir_channel(b
, coord
, 1));
407 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
411 blorp_blit_apply_transform(nir_builder
*b
, nir_ssa_def
*src_pos
,
412 struct brw_blorp_blit_vars
*v
)
414 nir_ssa_def
*offset
= nir_vec2(b
, nir_load_var(b
, v
->u_x_transform
.offset
),
415 nir_load_var(b
, v
->u_y_transform
.offset
));
416 nir_ssa_def
*mul
= nir_vec2(b
, nir_load_var(b
, v
->u_x_transform
.multiplier
),
417 nir_load_var(b
, v
->u_y_transform
.multiplier
));
419 nir_ssa_def
*pos
= nir_ffma(b
, src_pos
, mul
, offset
);
421 if (src_pos
->num_components
== 3) {
422 /* Leave the sample id alone */
423 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
424 nir_channel(b
, src_pos
, 2));
431 blorp_nir_discard_if_outside_rect(nir_builder
*b
, nir_ssa_def
*pos
,
432 struct brw_blorp_blit_vars
*v
)
434 nir_ssa_def
*c0
, *c1
, *c2
, *c3
;
435 c0
= nir_ult(b
, nir_channel(b
, pos
, 0), nir_load_var(b
, v
->u_dst_x0
));
436 c1
= nir_uge(b
, nir_channel(b
, pos
, 0), nir_load_var(b
, v
->u_dst_x1
));
437 c2
= nir_ult(b
, nir_channel(b
, pos
, 1), nir_load_var(b
, v
->u_dst_y0
));
438 c3
= nir_uge(b
, nir_channel(b
, pos
, 1), nir_load_var(b
, v
->u_dst_y1
));
439 nir_ssa_def
*oob
= nir_ior(b
, nir_ior(b
, c0
, c1
), nir_ior(b
, c2
, c3
));
441 nir_intrinsic_instr
*discard
=
442 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_discard_if
);
443 discard
->src
[0] = nir_src_for_ssa(oob
);
444 nir_builder_instr_insert(b
, &discard
->instr
);
447 static nir_tex_instr
*
448 blorp_create_nir_tex_instr(nir_shader
*shader
, nir_texop op
,
449 nir_ssa_def
*pos
, unsigned num_srcs
,
450 enum brw_reg_type dst_type
)
452 nir_tex_instr
*tex
= nir_tex_instr_create(shader
, num_srcs
);
457 case BRW_REGISTER_TYPE_F
:
458 tex
->dest_type
= nir_type_float
;
460 case BRW_REGISTER_TYPE_D
:
461 tex
->dest_type
= nir_type_int
;
463 case BRW_REGISTER_TYPE_UD
:
464 tex
->dest_type
= nir_type_uint
;
467 unreachable("Invalid texture return type");
470 tex
->is_array
= false;
471 tex
->is_shadow
= false;
473 /* Blorp only has one texture and it's bound at unit 0 */
476 tex
->texture_index
= 0;
477 tex
->sampler_index
= 0;
479 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, NULL
);
485 blorp_nir_tex(nir_builder
*b
, nir_ssa_def
*pos
, enum brw_reg_type dst_type
)
488 blorp_create_nir_tex_instr(b
->shader
, nir_texop_tex
, pos
, 2, dst_type
);
490 assert(pos
->num_components
== 2);
491 tex
->sampler_dim
= GLSL_SAMPLER_DIM_2D
;
492 tex
->coord_components
= 2;
493 tex
->src
[0].src_type
= nir_tex_src_coord
;
494 tex
->src
[0].src
= nir_src_for_ssa(pos
);
495 tex
->src
[1].src_type
= nir_tex_src_lod
;
496 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
498 nir_builder_instr_insert(b
, &tex
->instr
);
500 return &tex
->dest
.ssa
;
504 blorp_nir_txf(nir_builder
*b
, struct brw_blorp_blit_vars
*v
,
505 nir_ssa_def
*pos
, enum brw_reg_type dst_type
)
508 blorp_create_nir_tex_instr(b
->shader
, nir_texop_txf
, pos
, 2, dst_type
);
510 /* In order to properly handle 3-D textures, we pull the Z component from
511 * a uniform. TODO: This is a bit magic; we should probably make this
512 * more explicit in the future.
514 assert(pos
->num_components
== 2);
515 pos
= nir_vec3(b
, nir_channel(b
, pos
, 0), nir_channel(b
, pos
, 1),
516 nir_load_var(b
, v
->u_src_z
));
518 tex
->sampler_dim
= GLSL_SAMPLER_DIM_3D
;
519 tex
->coord_components
= 3;
520 tex
->src
[0].src_type
= nir_tex_src_coord
;
521 tex
->src
[0].src
= nir_src_for_ssa(pos
);
522 tex
->src
[1].src_type
= nir_tex_src_lod
;
523 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
525 nir_builder_instr_insert(b
, &tex
->instr
);
527 return &tex
->dest
.ssa
;
531 blorp_nir_txf_ms(nir_builder
*b
, nir_ssa_def
*pos
, nir_ssa_def
*mcs
,
532 enum brw_reg_type dst_type
)
535 blorp_create_nir_tex_instr(b
->shader
, nir_texop_txf_ms
, pos
,
536 mcs
!= NULL
? 3 : 2, dst_type
);
538 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
539 tex
->coord_components
= 2;
540 tex
->src
[0].src_type
= nir_tex_src_coord
;
541 tex
->src
[0].src
= nir_src_for_ssa(pos
);
543 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
544 if (pos
->num_components
== 2) {
545 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
547 assert(pos
->num_components
== 3);
548 tex
->src
[1].src
= nir_src_for_ssa(nir_channel(b
, pos
, 2));
552 tex
->src
[2].src_type
= nir_tex_src_ms_mcs
;
553 tex
->src
[2].src
= nir_src_for_ssa(mcs
);
556 nir_builder_instr_insert(b
, &tex
->instr
);
558 return &tex
->dest
.ssa
;
562 blorp_nir_txf_ms_mcs(nir_builder
*b
, nir_ssa_def
*pos
)
565 blorp_create_nir_tex_instr(b
->shader
, nir_texop_txf_ms_mcs
,
566 pos
, 1, BRW_REGISTER_TYPE_D
);
568 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
569 tex
->coord_components
= 2;
570 tex
->src
[0].src_type
= nir_tex_src_coord
;
571 tex
->src
[0].src
= nir_src_for_ssa(pos
);
573 nir_builder_instr_insert(b
, &tex
->instr
);
575 return &tex
->dest
.ssa
;
579 nir_mask_shift_or(struct nir_builder
*b
, nir_ssa_def
*dst
, nir_ssa_def
*src
,
580 uint32_t src_mask
, int src_left_shift
)
582 nir_ssa_def
*masked
= nir_iand(b
, src
, nir_imm_int(b
, src_mask
));
584 nir_ssa_def
*shifted
;
585 if (src_left_shift
> 0) {
586 shifted
= nir_ishl(b
, masked
, nir_imm_int(b
, src_left_shift
));
587 } else if (src_left_shift
< 0) {
588 shifted
= nir_ushr(b
, masked
, nir_imm_int(b
, -src_left_shift
));
590 assert(src_left_shift
== 0);
594 return nir_ior(b
, dst
, shifted
);
598 * Emit code to compensate for the difference between Y and W tiling.
600 * This code modifies the X and Y coordinates according to the formula:
602 * (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
604 * (See brw_blorp_build_nir_shader).
606 static inline nir_ssa_def
*
607 blorp_nir_retile_y_to_w(nir_builder
*b
, nir_ssa_def
*pos
)
609 assert(pos
->num_components
== 2);
610 nir_ssa_def
*x_Y
= nir_channel(b
, pos
, 0);
611 nir_ssa_def
*y_Y
= nir_channel(b
, pos
, 1);
613 /* Given X and Y coordinates that describe an address using Y tiling,
614 * translate to the X and Y coordinates that describe the same address
617 * If we break down the low order bits of X and Y, using a
618 * single letter to represent each low-order bit:
620 * X = A << 7 | 0bBCDEFGH
621 * Y = J << 5 | 0bKLMNP (1)
623 * Then we can apply the Y tiling formula to see the memory offset being
626 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
628 * If we apply the W detiling formula to this memory location, that the
629 * corresponding X' and Y' coordinates are:
631 * X' = A << 6 | 0bBCDPFH (3)
632 * Y' = J << 6 | 0bKLMNEG
634 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
635 * we need to make the following computation:
637 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
638 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
640 nir_ssa_def
*x_W
= nir_imm_int(b
, 0);
641 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0xfffffff4, -1);
642 x_W
= nir_mask_shift_or(b
, x_W
, y_Y
, 0x1, 2);
643 x_W
= nir_mask_shift_or(b
, x_W
, x_Y
, 0x1, 0);
645 nir_ssa_def
*y_W
= nir_imm_int(b
, 0);
646 y_W
= nir_mask_shift_or(b
, y_W
, y_Y
, 0xfffffffe, 1);
647 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x8, -2);
648 y_W
= nir_mask_shift_or(b
, y_W
, x_Y
, 0x2, -1);
650 return nir_vec2(b
, x_W
, y_W
);
654 * Emit code to compensate for the difference between Y and W tiling.
656 * This code modifies the X and Y coordinates according to the formula:
658 * (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
660 * (See brw_blorp_build_nir_shader).
662 static inline nir_ssa_def
*
663 blorp_nir_retile_w_to_y(nir_builder
*b
, nir_ssa_def
*pos
)
665 assert(pos
->num_components
== 2);
666 nir_ssa_def
*x_W
= nir_channel(b
, pos
, 0);
667 nir_ssa_def
*y_W
= nir_channel(b
, pos
, 1);
669 /* Applying the same logic as above, but in reverse, we obtain the
672 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
673 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
675 nir_ssa_def
*x_Y
= nir_imm_int(b
, 0);
676 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0xfffffffa, 1);
677 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x2, 2);
678 x_Y
= nir_mask_shift_or(b
, x_Y
, y_W
, 0x1, 1);
679 x_Y
= nir_mask_shift_or(b
, x_Y
, x_W
, 0x1, 0);
681 nir_ssa_def
*y_Y
= nir_imm_int(b
, 0);
682 y_Y
= nir_mask_shift_or(b
, y_Y
, y_W
, 0xfffffffc, -1);
683 y_Y
= nir_mask_shift_or(b
, y_Y
, x_W
, 0x4, -2);
685 return nir_vec2(b
, x_Y
, y_Y
);
689 * Emit code to compensate for the difference between MSAA and non-MSAA
692 * This code modifies the X and Y coordinates according to the formula:
694 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
696 * (See brw_blorp_blit_program).
698 static inline nir_ssa_def
*
699 blorp_nir_encode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
700 unsigned num_samples
, enum intel_msaa_layout layout
)
702 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
705 case INTEL_MSAA_LAYOUT_NONE
:
706 assert(pos
->num_components
== 2);
708 case INTEL_MSAA_LAYOUT_CMS
:
709 /* We can't compensate for compressed layout since at this point in the
710 * program we haven't read from the MCS buffer.
712 unreachable("Bad layout in encode_msaa");
713 case INTEL_MSAA_LAYOUT_UMS
:
714 /* No translation needed */
716 case INTEL_MSAA_LAYOUT_IMS
: {
717 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
718 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
719 nir_ssa_def
*s_in
= pos
->num_components
== 2 ? nir_imm_int(b
, 0) :
720 nir_channel(b
, pos
, 2);
722 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
723 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
724 switch (num_samples
) {
727 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
728 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
731 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
732 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
733 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
735 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 1);
736 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
737 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
738 if (num_samples
== 2) {
741 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
742 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
743 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
748 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
749 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
751 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
753 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffe, 2);
754 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x4, 0);
755 x_out
= nir_mask_shift_or(b
, x_out
, s_in
, 0x1, 1);
756 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
757 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffe, 1);
758 y_out
= nir_mask_shift_or(b
, y_out
, s_in
, 0x2, 0);
759 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
763 unreachable("Invalid number of samples for IMS layout");
766 return nir_vec2(b
, x_out
, y_out
);
770 unreachable("Invalid MSAA layout");
775 * Emit code to compensate for the difference between MSAA and non-MSAA
778 * This code modifies the X and Y coordinates according to the formula:
780 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
782 * (See brw_blorp_blit_program).
784 static inline nir_ssa_def
*
785 blorp_nir_decode_msaa(nir_builder
*b
, nir_ssa_def
*pos
,
786 unsigned num_samples
, enum intel_msaa_layout layout
)
788 assert(pos
->num_components
== 2 || pos
->num_components
== 3);
791 case INTEL_MSAA_LAYOUT_NONE
:
792 /* No translation necessary, and S should already be zero. */
793 assert(pos
->num_components
== 2);
795 case INTEL_MSAA_LAYOUT_CMS
:
796 /* We can't compensate for compressed layout since at this point in the
797 * program we don't have access to the MCS buffer.
799 unreachable("Bad layout in encode_msaa");
800 case INTEL_MSAA_LAYOUT_UMS
:
801 /* No translation necessary. */
803 case INTEL_MSAA_LAYOUT_IMS
: {
804 assert(pos
->num_components
== 2);
806 nir_ssa_def
*x_in
= nir_channel(b
, pos
, 0);
807 nir_ssa_def
*y_in
= nir_channel(b
, pos
, 1);
809 nir_ssa_def
*x_out
= nir_imm_int(b
, 0);
810 nir_ssa_def
*y_out
= nir_imm_int(b
, 0);
811 nir_ssa_def
*s_out
= nir_imm_int(b
, 0);
812 switch (num_samples
) {
815 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
816 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
817 * S = (X & 0b10) >> 1
819 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
820 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
821 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
822 * S = (Y & 0b10) | (X & 0b10) >> 1
824 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffffc, -1);
825 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
826 if (num_samples
== 2) {
828 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
830 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
831 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
832 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
833 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
838 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
839 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
840 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
841 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
843 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0xfffffff8, -2);
844 x_out
= nir_mask_shift_or(b
, x_out
, x_in
, 0x1, 0);
845 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0xfffffffc, -1);
846 y_out
= nir_mask_shift_or(b
, y_out
, y_in
, 0x1, 0);
847 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x4, 0);
848 s_out
= nir_mask_shift_or(b
, s_out
, y_in
, 0x2, 0);
849 s_out
= nir_mask_shift_or(b
, s_out
, x_in
, 0x2, -1);
853 unreachable("Invalid number of samples for IMS layout");
856 return nir_vec3(b
, x_out
, y_out
, s_out
);
860 unreachable("Invalid MSAA layout");
865 * Generator for WM programs used in BLORP blits.
867 * The bulk of the work done by the WM program is to wrap and unwrap the
868 * coordinate transformations used by the hardware to store surfaces in
869 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
870 * sample index for a multisampled surface) to a memory offset by the
871 * following formulas:
873 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
874 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
876 * For a single-sampled surface, or for a multisampled surface using
877 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
880 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
881 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
882 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
883 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
885 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
886 * embeds the sample number into bit 1 of the X and Y coordinates:
888 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
889 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
890 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
891 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
892 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
893 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
894 * S = (Y & 0b10) | (X & 0b10) >> 1
896 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
897 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
900 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
901 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
902 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
903 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
904 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
905 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
906 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
908 * For X tiling, tile() combines together the low-order bits of the X and Y
909 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
910 * bytes wide and 8 rows high:
912 * tile(x_tiled, X, Y, S) = A
913 * where A = tile_num << 12 | offset
914 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
915 * offset = (Y' & 0b111) << 9
916 * | (X & 0b111111111)
918 * Y' = Y + S * qpitch
919 * detile(x_tiled, A) = (X, Y, S)
923 * Y' = (tile_num / tile_pitch) << 3
924 * | (A & 0b111000000000) >> 9
925 * X' = (tile_num % tile_pitch) << 9
926 * | (A & 0b111111111)
928 * (In all tiling formulas, cpp is the number of bytes occupied by a single
929 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
930 * to fill the width of the surface, and qpitch is the spacing (in rows)
931 * between array slices).
933 * For Y tiling, tile() combines together the low-order bits of the X and Y
934 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
935 * bytes wide and 32 rows high:
937 * tile(y_tiled, X, Y, S) = A
938 * where A = tile_num << 12 | offset
939 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
940 * offset = (X' & 0b1110000) << 5
941 * | (Y' & 0b11111) << 4
944 * Y' = Y + S * qpitch
945 * detile(y_tiled, A) = (X, Y, S)
949 * Y' = (tile_num / tile_pitch) << 5
950 * | (A & 0b111110000) >> 4
951 * X' = (tile_num % tile_pitch) << 7
952 * | (A & 0b111000000000) >> 5
955 * For W tiling, tile() combines together the low-order bits of the X and Y
956 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
957 * bytes wide and 64 rows high (note that W tiling is only used for stencil
958 * buffers, which always have cpp = 1 and S=0):
960 * tile(w_tiled, X, Y, S) = A
961 * where A = tile_num << 12 | offset
962 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
963 * offset = (X' & 0b111000) << 6
964 * | (Y' & 0b111100) << 3
965 * | (X' & 0b100) << 2
971 * Y' = Y + S * qpitch
972 * detile(w_tiled, A) = (X, Y, S)
973 * where X = X' / cpp = X'
974 * Y = Y' % qpitch = Y'
976 * Y' = (tile_num / tile_pitch) << 6
977 * | (A & 0b111100000) >> 3
978 * | (A & 0b1000) >> 2
980 * X' = (tile_num % tile_pitch) << 6
981 * | (A & 0b111000000000) >> 6
982 * | (A & 0b10000) >> 2
986 * Finally, for a non-tiled surface, tile() simply combines together the X and
987 * Y coordinates in the natural way:
989 * tile(untiled, X, Y, S) = A
990 * where A = Y * pitch + X'
992 * Y' = Y + S * qpitch
993 * detile(untiled, A) = (X, Y, S)
1000 * (In these formulas, pitch is the number of bytes occupied by a single row
1004 brw_blorp_build_nir_shader(struct brw_context
*brw
,
1005 const brw_blorp_blit_prog_key
*key
,
1006 struct brw_blorp_prog_data
*prog_data
)
1008 nir_ssa_def
*src_pos
, *dst_pos
, *color
;
1011 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
1012 /* If the destination image is W tiled and multisampled, then the thread
1013 * must be dispatched once per sample, not once per pixel. This is
1014 * necessary because after conversion between W and Y tiling, there's no
1015 * guarantee that all samples corresponding to a single pixel will still
1018 assert(key
->persample_msaa_dispatch
);
1022 /* We are blending, which means we won't have an opportunity to
1023 * translate the tiling and sample count for the texture surface. So
1024 * the surface state for the texture must be configured with the correct
1025 * tiling and sample count.
1027 assert(!key
->src_tiled_w
);
1028 assert(key
->tex_samples
== key
->src_samples
);
1029 assert(key
->tex_layout
== key
->src_layout
);
1030 assert(key
->tex_samples
> 0);
1033 if (key
->persample_msaa_dispatch
) {
1034 /* It only makes sense to do persample dispatch if the render target is
1035 * configured as multisampled.
1037 assert(key
->rt_samples
> 0);
1040 /* Make sure layout is consistent with sample count */
1041 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1042 (key
->tex_samples
== 0));
1043 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1044 (key
->rt_samples
== 0));
1045 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1046 (key
->src_samples
== 0));
1047 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1048 (key
->dst_samples
== 0));
1050 /* Set up prog_data */
1051 brw_blorp_prog_data_init(prog_data
);
1054 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
1056 struct brw_blorp_blit_vars v
;
1057 brw_blorp_blit_vars_init(&b
, &v
, key
);
1059 dst_pos
= blorp_blit_get_frag_coords(&b
, key
, &v
);
1061 /* Render target and texture hardware don't support W tiling until Gen8. */
1062 const bool rt_tiled_w
= false;
1063 const bool tex_tiled_w
= brw
->gen
>= 8 && key
->src_tiled_w
;
1065 /* The address that data will be written to is determined by the
1066 * coordinates supplied to the WM thread and the tiling and sample count of
1067 * the render target, according to the formula:
1069 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1071 * If the actual tiling and sample count of the destination surface are not
1072 * the same as the configuration of the render target, then these
1073 * coordinates are wrong and we have to adjust them to compensate for the
1076 if (rt_tiled_w
!= key
->dst_tiled_w
||
1077 key
->rt_samples
!= key
->dst_samples
||
1078 key
->rt_layout
!= key
->dst_layout
) {
1079 dst_pos
= blorp_nir_encode_msaa(&b
, dst_pos
, key
->rt_samples
,
1081 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1082 if (rt_tiled_w
!= key
->dst_tiled_w
)
1083 dst_pos
= blorp_nir_retile_y_to_w(&b
, dst_pos
);
1084 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1085 dst_pos
= blorp_nir_decode_msaa(&b
, dst_pos
, key
->dst_samples
,
1089 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1091 * That is: X, Y and S now contain the true coordinates and sample index of
1092 * the data that the WM thread should output.
1094 * If we need to kill pixels that are outside the destination rectangle,
1095 * now is the time to do it.
1098 blorp_nir_discard_if_outside_rect(&b
, dst_pos
, &v
);
1100 src_pos
= blorp_blit_apply_transform(&b
, nir_i2f(&b
, dst_pos
), &v
);
1102 if (key
->blit_scaled
&& key
->blend
) {
1104 } else if (!key
->bilinear_filter
) {
1105 /* We're going to use a texelFetch, so we need integers */
1106 src_pos
= nir_f2i(&b
, src_pos
);
1109 /* If the source image is not multisampled, then we want to fetch sample
1110 * number 0, because that's the only sample there is.
1112 if (key
->src_samples
== 0)
1113 src_pos
= nir_channels(&b
, src_pos
, 0x3);
1115 /* X, Y, and S are now the coordinates of the pixel in the source image
1116 * that we want to texture from. Exception: if we are blending, then S is
1117 * irrelevant, because we are going to fetch all samples.
1119 if (key
->blend
&& !key
->blit_scaled
) {
1121 } else if (key
->blend
&& key
->blit_scaled
) {
1124 /* We aren't blending, which means we just want to fetch a single sample
1125 * from the source surface. The address that we want to fetch from is
1126 * related to the X, Y and S values according to the formula:
1128 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1130 * If the actual tiling and sample count of the source surface are not
1131 * the same as the configuration of the texture, then we need to adjust
1132 * the coordinates to compensate for the difference.
1134 if ((tex_tiled_w
!= key
->src_tiled_w
||
1135 key
->tex_samples
!= key
->src_samples
||
1136 key
->tex_layout
!= key
->src_layout
) &&
1137 !key
->bilinear_filter
) {
1138 src_pos
= blorp_nir_encode_msaa(&b
, src_pos
, key
->src_samples
,
1140 /* Now (X, Y, S) = detile(src_tiling, offset) */
1141 if (tex_tiled_w
!= key
->src_tiled_w
)
1142 src_pos
= blorp_nir_retile_w_to_y(&b
, src_pos
);
1143 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1144 src_pos
= blorp_nir_decode_msaa(&b
, src_pos
, key
->tex_samples
,
1148 if (key
->bilinear_filter
) {
1149 color
= blorp_nir_tex(&b
, src_pos
, key
->texture_data_type
);
1151 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1153 * In other words: X, Y, and S now contain values which, when passed to
1154 * the texturing unit, will cause data to be read from the correct
1155 * memory location. So we can fetch the texel now.
1157 if (key
->src_samples
== 0) {
1158 color
= blorp_nir_txf(&b
, &v
, src_pos
, key
->texture_data_type
);
1160 nir_ssa_def
*mcs
= NULL
;
1161 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1162 mcs
= blorp_nir_txf_ms_mcs(&b
, src_pos
);
1164 color
= blorp_nir_txf_ms(&b
, src_pos
, mcs
, key
->texture_data_type
);
1169 nir_store_var(&b
, v
.color_out
, color
, 0xf);
1174 ralloc_free(b
.shader
);
1178 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
1181 brw_blorp_blit_program(struct brw_context
*brw
,
1182 const brw_blorp_blit_prog_key
*key
);
1184 const GLuint
*compile(struct brw_context
*brw
, bool debug_flag
,
1185 GLuint
*program_size
);
1187 brw_blorp_prog_data prog_data
;
1191 void alloc_push_const_regs(int base_reg
);
1192 void compute_frag_coords();
1193 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
1194 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
1195 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
1196 void translate_dst_to_src();
1197 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
1198 struct brw_reg clampX0
, struct brw_reg clampY0
,
1199 struct brw_reg clampX1
, struct brw_reg clampY1
);
1200 void single_to_blend();
1201 void manual_blend_average(unsigned num_samples
);
1202 void manual_blend_bilinear(unsigned num_samples
);
1203 void sample(struct brw_reg dst
);
1204 void texel_fetch(struct brw_reg dst
);
1206 void texture_lookup(struct brw_reg dst
, enum opcode op
,
1207 const sampler_message_arg
*args
, int num_args
);
1208 void render_target_write();
1211 * Base-2 logarithm of the maximum number of samples that can be blended.
1213 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
1215 struct brw_context
*brw
;
1216 const brw_blorp_blit_prog_key
*key
;
1218 /* Thread dispatch header */
1221 /* Pixel X/Y coordinates (always in R1). */
1224 /* Push constants */
1225 struct brw_reg dst_x0
;
1226 struct brw_reg dst_x1
;
1227 struct brw_reg dst_y0
;
1228 struct brw_reg dst_y1
;
1229 /* Top right coordinates of the rectangular grid used for scaled blitting */
1230 struct brw_reg rect_grid_x1
;
1231 struct brw_reg rect_grid_y1
;
1233 struct brw_reg multiplier
;
1234 struct brw_reg offset
;
1235 } x_transform
, y_transform
;
1236 struct brw_reg src_z
;
1238 /* Data read from texture (4 vec16's per array element) */
1239 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
1241 /* Auxiliary storage for the contents of the MCS surface.
1243 * Since the sampler always returns 8 registers worth of data, this is 8
1244 * registers wide, even though we only use the first 2 registers of it.
1246 struct brw_reg mcs_data
;
1248 /* X coordinates. We have two of them so that we can perform coordinate
1249 * transformations easily.
1251 struct brw_reg x_coords
[2];
1253 /* Y coordinates. We have two of them so that we can perform coordinate
1254 * transformations easily.
1256 struct brw_reg y_coords
[2];
1258 /* X, Y coordinates of the pixel from which we need to fetch the specific
1259 * sample. These are used for multisample scaled blitting.
1261 struct brw_reg x_sample_coords
;
1262 struct brw_reg y_sample_coords
;
1264 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
1265 struct brw_reg x_frac
;
1266 struct brw_reg y_frac
;
1268 /* Which element of x_coords and y_coords is currently in use.
1272 /* True if, at the point in the program currently being compiled, the
1273 * sample index is known to be zero.
1277 /* Register storing the sample index when s_is_zero is false. */
1278 struct brw_reg sample_index
;
1284 /* MRF used for sampling and render target writes */
1288 brw_blorp_blit_program::brw_blorp_blit_program(
1289 struct brw_context
*brw
, const brw_blorp_blit_prog_key
*key
)
1290 : brw_blorp_eu_emitter(), brw(brw
), key(key
)
1295 brw_blorp_blit_program::compile(struct brw_context
*brw
, bool debug_flag
,
1296 GLuint
*program_size
)
1299 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
1300 /* If the destination image is W tiled and multisampled, then the thread
1301 * must be dispatched once per sample, not once per pixel. This is
1302 * necessary because after conversion between W and Y tiling, there's no
1303 * guarantee that all samples corresponding to a single pixel will still
1306 assert(key
->persample_msaa_dispatch
);
1310 /* We are blending, which means we won't have an opportunity to
1311 * translate the tiling and sample count for the texture surface. So
1312 * the surface state for the texture must be configured with the correct
1313 * tiling and sample count.
1315 assert(!key
->src_tiled_w
);
1316 assert(key
->tex_samples
== key
->src_samples
);
1317 assert(key
->tex_layout
== key
->src_layout
);
1318 assert(key
->tex_samples
> 0);
1321 if (key
->persample_msaa_dispatch
) {
1322 /* It only makes sense to do persample dispatch if the render target is
1323 * configured as multisampled.
1325 assert(key
->rt_samples
> 0);
1328 /* Make sure layout is consistent with sample count */
1329 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1330 (key
->tex_samples
== 0));
1331 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1332 (key
->rt_samples
== 0));
1333 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1334 (key
->src_samples
== 0));
1335 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
1336 (key
->dst_samples
== 0));
1338 /* Set up prog_data */
1339 brw_blorp_prog_data_init(&prog_data
);
1340 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
1343 compute_frag_coords();
1345 /* Render target and texture hardware don't support W tiling until Gen8. */
1346 const bool rt_tiled_w
= false;
1347 const bool tex_tiled_w
= brw
->gen
>= 8 && key
->src_tiled_w
;
1349 /* The address that data will be written to is determined by the
1350 * coordinates supplied to the WM thread and the tiling and sample count of
1351 * the render target, according to the formula:
1353 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
1355 * If the actual tiling and sample count of the destination surface are not
1356 * the same as the configuration of the render target, then these
1357 * coordinates are wrong and we have to adjust them to compensate for the
1360 if (rt_tiled_w
!= key
->dst_tiled_w
||
1361 key
->rt_samples
!= key
->dst_samples
||
1362 key
->rt_layout
!= key
->dst_layout
) {
1363 encode_msaa(key
->rt_samples
, key
->rt_layout
);
1364 /* Now (X, Y, S) = detile(rt_tiling, offset) */
1365 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
1366 /* Now (X, Y, S) = detile(dst_tiling, offset) */
1367 decode_msaa(key
->dst_samples
, key
->dst_layout
);
1370 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
1372 * That is: X, Y and S now contain the true coordinates and sample index of
1373 * the data that the WM thread should output.
1375 * If we need to kill pixels that are outside the destination rectangle,
1376 * now is the time to do it.
1380 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
1381 y_coords
[xy_coord_index
],
1382 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
1384 /* Next, apply a translation to obtain coordinates in the source image. */
1385 translate_dst_to_src();
1387 /* If the source image is not multisampled, then we want to fetch sample
1388 * number 0, because that's the only sample there is.
1390 if (key
->src_samples
== 0)
1393 /* X, Y, and S are now the coordinates of the pixel in the source image
1394 * that we want to texture from. Exception: if we are blending, then S is
1395 * irrelevant, because we are going to fetch all samples.
1397 if (key
->blend
&& !key
->blit_scaled
) {
1398 if (brw
->gen
== 6) {
1399 /* Gen6 hardware an automatically blend using the SAMPLE message */
1401 sample(texture_data
[0]);
1403 /* Gen7+ hardware doesn't automaticaly blend. */
1404 manual_blend_average(key
->src_samples
);
1406 } else if(key
->blend
&& key
->blit_scaled
) {
1407 manual_blend_bilinear(key
->src_samples
);
1409 /* We aren't blending, which means we just want to fetch a single sample
1410 * from the source surface. The address that we want to fetch from is
1411 * related to the X, Y and S values according to the formula:
1413 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
1415 * If the actual tiling and sample count of the source surface are not
1416 * the same as the configuration of the texture, then we need to adjust
1417 * the coordinates to compensate for the difference.
1419 if ((tex_tiled_w
!= key
->src_tiled_w
||
1420 key
->tex_samples
!= key
->src_samples
||
1421 key
->tex_layout
!= key
->src_layout
) &&
1422 !key
->bilinear_filter
) {
1423 encode_msaa(key
->src_samples
, key
->src_layout
);
1424 /* Now (X, Y, S) = detile(src_tiling, offset) */
1425 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
1426 /* Now (X, Y, S) = detile(tex_tiling, offset) */
1427 decode_msaa(key
->tex_samples
, key
->tex_layout
);
1430 if (key
->bilinear_filter
) {
1431 sample(texture_data
[0]);
1434 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
1436 * In other words: X, Y, and S now contain values which, when passed to
1437 * the texturing unit, will cause data to be read from the correct
1438 * memory location. So we can fetch the texel now.
1440 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1442 texel_fetch(texture_data
[0]);
1446 /* Finally, write the fetched (or blended) value to the render target and
1447 * terminate the thread.
1449 render_target_write();
1451 return get_program(brw
, debug_flag
, program_size
);
1455 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
1457 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
1458 #define ALLOC_REG(name, type) \
1460 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
1461 base_reg + CONST_LOC(name) / 32, \
1462 (CONST_LOC(name) % 32) / 4), type)
1464 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
1465 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
1466 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
1467 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
1468 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
1469 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
1470 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
1471 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
1472 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
1473 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
1474 ALLOC_REG(src_z
, BRW_REGISTER_TYPE_UD
);
1480 brw_blorp_blit_program::alloc_regs()
1483 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
1484 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
1485 prog_data
.first_curbe_grf_0
= reg
;
1486 alloc_push_const_regs(reg
);
1487 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
1488 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
1489 this->texture_data
[i
] =
1490 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
1494 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
1496 for (int i
= 0; i
< 2; ++i
) {
1498 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1501 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1505 if (key
->blit_scaled
&& key
->blend
) {
1506 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
1508 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
1510 this->x_frac
= brw_vec8_grf(reg
, 0);
1512 this->y_frac
= brw_vec8_grf(reg
, 0);
1516 this->xy_coord_index
= 0;
1518 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1520 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1522 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
1525 /* Make sure we didn't run out of registers */
1526 assert(reg
<= GEN7_MRF_HACK_START
);
1529 this->base_mrf
= mrf
;
1532 /* In the code that follows, X and Y can be used to quickly refer to the
1533 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
1534 * prime") to the inactive elements.
1536 * S can be used to quickly refer to sample_index.
1538 #define X x_coords[xy_coord_index]
1539 #define Y y_coords[xy_coord_index]
1540 #define Xp x_coords[!xy_coord_index]
1541 #define Yp y_coords[!xy_coord_index]
1542 #define S sample_index
1544 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
1545 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
1547 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
1550 * Emit code to compute the X and Y coordinates of the pixels being rendered
1551 * by this WM invocation.
1553 * Assuming the render target is set up for Y tiling, these (X, Y) values are
1554 * related to the address offset where outputs will be written by the formula:
1556 * (X, Y, S) = decode_msaa(detile(offset)).
1558 * (See brw_blorp_blit_program).
1561 brw_blorp_blit_program::compute_frag_coords()
1563 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
1564 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
1565 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
1566 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
1568 * Pixels within a subspan are laid out in this arrangement:
1572 * So, to compute the coordinates of each pixel, we need to read every 2nd
1573 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
1574 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
1575 * In other words, the data we want to access is R1.4<2;4,0>UW.
1577 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
1578 * result, since pixels n+1 and n+3 are in the right half of the subspan.
1580 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
1581 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
1583 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
1584 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
1585 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
1588 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
1589 * pixels n+2 and n+3 are in the bottom half of the subspan.
1591 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
1592 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
1594 /* Move the coordinates to UD registers. */
1595 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
1596 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
1599 if (key
->persample_msaa_dispatch
) {
1600 switch (key
->rt_samples
) {
1603 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
1604 * Therefore, subspan 0 will represent sample 0, subspan 1 will
1605 * represent sample 1, and so on.
1607 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
1608 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
1609 * populate a temporary variable with the sequence (0, 1, 2, 3), and
1610 * then copy from it using vstride=1, width=4, hstride=0.
1612 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
1613 emit_mov(vec16(t1_uw1
), key
->rt_samples
== 4 ?
1614 brw_imm_v(0x3210) : brw_imm_v(0x1010));
1615 /* Move to UD sample_index register. */
1616 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
1617 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
1621 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
1622 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
1623 * subspan 1 will represent sample 1, and so on. We can find the
1624 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
1625 * Index") and multiplying by two (since samples are always delivered
1626 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
1629 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
1630 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
1631 * variable with the sequence (0, 1, 2, 3), and then reading from it
1632 * using vstride=1, width=4, hstride=0.
1634 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
1635 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1636 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1637 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1638 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
1639 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
1640 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1641 stride(t2_uw1
, 1, 4, 0));
1642 emit_add_8(offset(S
, 1),
1643 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1644 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1648 unreachable("Unrecognized sample count in "
1649 "brw_blorp_blit_program::compute_frag_coords()");
1653 /* Either the destination surface is single-sampled, or the WM will be
1654 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1655 * per pixel). In either case, it's not meaningful to compute a sample
1656 * value. Just set it to 0.
1663 * Emit code to compensate for the difference between Y and W tiling.
1665 * This code modifies the X and Y coordinates according to the formula:
1667 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1669 * (See brw_blorp_blit_program).
1671 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1672 * are booleans where true represents W tiling and false represents Y tiling.
1675 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1677 if (old_tiled_w
== new_tiled_w
)
1680 /* In the code that follows, we can safely assume that S = 0, because W
1681 * tiling formats always use IMS layout.
1686 /* Given X and Y coordinates that describe an address using Y tiling,
1687 * translate to the X and Y coordinates that describe the same address
1690 * If we break down the low order bits of X and Y, using a
1691 * single letter to represent each low-order bit:
1693 * X = A << 7 | 0bBCDEFGH
1694 * Y = J << 5 | 0bKLMNP (1)
1696 * Then we can apply the Y tiling formula to see the memory offset being
1699 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1701 * If we apply the W detiling formula to this memory location, that the
1702 * corresponding X' and Y' coordinates are:
1704 * X' = A << 6 | 0bBCDPFH (3)
1705 * Y' = J << 6 | 0bKLMNEG
1707 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1708 * we need to make the following computation:
1710 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1711 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1713 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1714 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1715 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1716 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1717 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1718 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1719 emit_or(Xp
, t1
, t2
);
1720 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1721 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1722 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1723 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1724 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1725 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1726 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1727 emit_or(Yp
, t1
, t2
);
1730 /* Applying the same logic as above, but in reverse, we obtain the
1733 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1734 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1736 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1737 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1738 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1739 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1740 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1741 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1742 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1743 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1745 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1746 emit_or(Xp
, t1
, t2
);
1747 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1748 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1749 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1750 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1751 emit_or(Yp
, t1
, t2
);
1757 * Emit code to compensate for the difference between MSAA and non-MSAA
1760 * This code modifies the X and Y coordinates according to the formula:
1762 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1764 * (See brw_blorp_blit_program).
1767 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1768 intel_msaa_layout layout
)
1771 case INTEL_MSAA_LAYOUT_NONE
:
1772 /* No translation necessary, and S should already be zero. */
1775 case INTEL_MSAA_LAYOUT_CMS
:
1776 /* We can't compensate for compressed layout since at this point in the
1777 * program we haven't read from the MCS buffer.
1779 unreachable("Bad layout in encode_msaa");
1780 case INTEL_MSAA_LAYOUT_UMS
:
1781 /* No translation necessary. */
1783 case INTEL_MSAA_LAYOUT_IMS
:
1784 switch (num_samples
) {
1786 /* encode_msaa(2, IMS, X, Y, S) = (X', Y', 0)
1787 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1791 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1792 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1793 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1795 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1797 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1798 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1800 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1802 if (num_samples
== 2) {
1807 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1808 emit_or(Xp
, t1
, t2
);
1809 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1810 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1812 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1813 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1815 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1816 emit_or(Yp
, t1
, t2
);
1819 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1820 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1822 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1824 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1825 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1827 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1828 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1829 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1830 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1831 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1834 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1835 emit_or(Xp
, t1
, t2
);
1836 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1837 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1839 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1840 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1842 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1843 emit_or(Yp
, t1
, t2
);
1853 * Emit code to compensate for the difference between MSAA and non-MSAA
1856 * This code modifies the X and Y coordinates according to the formula:
1858 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1860 * (See brw_blorp_blit_program).
1863 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1864 intel_msaa_layout layout
)
1867 case INTEL_MSAA_LAYOUT_NONE
:
1868 /* No translation necessary, and S should already be zero. */
1871 case INTEL_MSAA_LAYOUT_CMS
:
1872 /* We can't compensate for compressed layout since at this point in the
1873 * program we don't have access to the MCS buffer.
1875 unreachable("Bad layout in encode_msaa");
1876 case INTEL_MSAA_LAYOUT_UMS
:
1877 /* No translation necessary. */
1879 case INTEL_MSAA_LAYOUT_IMS
:
1881 switch (num_samples
) {
1883 /* decode_msaa(2, IMS, X, Y, 0) = (X', Y', S)
1884 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1885 * S = (X & 0b10) >> 1
1888 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1889 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1890 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1891 * S = (Y & 0b10) | (X & 0b10) >> 1
1893 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1894 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1895 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1896 emit_or(Xp
, t1
, t2
);
1898 if (num_samples
== 2) {
1900 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1901 emit_shr(S
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1903 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1904 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1905 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1906 emit_or(Yp
, t1
, t2
);
1907 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1908 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1909 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1914 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1915 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1916 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1917 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1919 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1920 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1921 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1922 emit_or(Xp
, t1
, t2
);
1923 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1924 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1925 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1926 emit_or(Yp
, t1
, t2
);
1927 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1928 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1929 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1930 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1931 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1942 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1946 brw_blorp_blit_program::translate_dst_to_src()
1948 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1949 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1950 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1951 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1953 /* Move the UD coordinates to float registers. */
1956 /* Scale and offset */
1957 emit_mad(X_f
, x_transform
.offset
, Xp_f
, x_transform
.multiplier
);
1958 emit_mad(Y_f
, y_transform
.offset
, Yp_f
, y_transform
.multiplier
);
1959 if (key
->blit_scaled
&& key
->blend
) {
1960 /* Translate coordinates to lay out the samples in a rectangular grid
1961 * roughly corresponding to sample locations.
1963 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1964 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1965 /* Adjust coordinates so that integers represent pixel centers rather
1968 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1969 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1971 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1972 * texels on texture edges.
1974 clamp_tex_coords(X_f
, Y_f
,
1975 brw_imm_f(0.0), brw_imm_f(0.0),
1976 rect_grid_x1
, rect_grid_y1
);
1978 /* Store the fractional parts to be used as bilinear interpolation
1981 emit_frc(x_frac
, X_f
);
1982 emit_frc(y_frac
, Y_f
);
1984 /* Round the float coordinates down to nearest integer */
1985 emit_rndd(Xp_f
, X_f
);
1986 emit_rndd(Yp_f
, Y_f
);
1987 emit_mul(X_f
, Xp_f
, brw_imm_f(1.0f
/ key
->x_scale
));
1988 emit_mul(Y_f
, Yp_f
, brw_imm_f(1.0f
/ key
->y_scale
));
1990 } else if (!key
->bilinear_filter
) {
1991 /* Round the float coordinates down to nearest integer by moving to
2001 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
2002 struct brw_reg regY
,
2003 struct brw_reg clampX0
,
2004 struct brw_reg clampY0
,
2005 struct brw_reg clampX1
,
2006 struct brw_reg clampY1
)
2008 emit_max(regX
, regX
, clampX0
);
2009 emit_max(regY
, regY
, clampY0
);
2010 emit_min(regX
, regX
, clampX1
);
2011 emit_min(regY
, regY
, clampY1
);
2017 * Count the number of trailing 1 bits in the given value. For example:
2019 * count_trailing_one_bits(0) == 0
2020 * count_trailing_one_bits(7) == 3
2021 * count_trailing_one_bits(11) == 2
2023 static inline int count_trailing_one_bits(unsigned value
)
2025 #ifdef HAVE___BUILTIN_CTZ
2026 return __builtin_ctz(~value
);
2028 return _mesa_bitcount(value
& ~(value
+ 1));
2034 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
2036 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
2039 assert(key
->texture_data_type
== BRW_REGISTER_TYPE_F
);
2041 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
2043 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
2045 * This ensures that when all samples have the same value, no numerical
2046 * precision is lost, since each addition operation always adds two equal
2047 * values, and summing two equal floating point values does not lose
2050 * We perform this computation by treating the texture_data array as a
2051 * stack and performing the following operations:
2053 * - push sample 0 onto stack
2054 * - push sample 1 onto stack
2055 * - add top two stack entries
2056 * - push sample 2 onto stack
2057 * - push sample 3 onto stack
2058 * - add top two stack entries
2059 * - add top two stack entries
2060 * - divide top stack entry by 4
2062 * Note that after pushing sample i onto the stack, the number of add
2063 * operations we do is equal to the number of trailing 1 bits in i. This
2064 * works provided the total number of samples is a power of two, which it
2065 * always is for i965.
2067 * For integer formats, we replace the add operations with average
2068 * operations and skip the final division.
2070 unsigned stack_depth
= 0;
2071 for (unsigned i
= 0; i
< num_samples
; ++i
) {
2072 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
2074 /* Push sample i onto the stack */
2075 assert(stack_depth
< ARRAY_SIZE(texture_data
));
2080 emit_mov(vec16(S
), brw_imm_ud(i
));
2082 texel_fetch(texture_data
[stack_depth
++]);
2084 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
2085 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
2086 * suggests an optimization:
2088 * "A simple optimization with probable large return in
2089 * performance is to compare the MCS value to zero (indicating
2090 * all samples are on sample slice 0), and sample only from
2091 * sample slice 0 using ld2dss if MCS is zero."
2093 * Note that in the case where the MCS value is zero, sampling from
2094 * sample slice 0 using ld2dss and sampling from sample 0 using
2095 * ld2dms are equivalent (since all samples are on sample slice 0).
2096 * Since we have already sampled from sample 0, all we need to do is
2097 * skip the remaining fetches and averaging if MCS is zero.
2099 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
2102 /* Do count_trailing_one_bits(i) times */
2103 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
2104 assert(stack_depth
>= 2);
2107 /* TODO: should use a smaller loop bound for non_RGBA formats */
2108 for (int k
= 0; k
< 4; ++k
) {
2109 emit_combine(BRW_OPCODE_ADD
,
2110 offset(texture_data
[stack_depth
- 1], 2*k
),
2111 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
2112 offset(vec8(texture_data
[stack_depth
]), 2*k
));
2117 /* We should have just 1 sample on the stack now. */
2118 assert(stack_depth
== 1);
2120 /* Scale the result down by a factor of num_samples */
2121 /* TODO: should use a smaller loop bound for non-RGBA formats */
2122 for (int j
= 0; j
< 4; ++j
) {
2123 emit_mul(offset(texture_data
[0], 2*j
),
2124 offset(vec8(texture_data
[0]), 2*j
),
2125 brw_imm_f(1.0f
/ num_samples
));
2128 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
2133 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
2135 /* We do this computation by performing the following operations:
2137 * In case of 4x, 8x MSAA:
2138 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
2139 * which are later used for interpolation
2140 * - linearly interpolate samples a and b in X
2141 * - linearly interpolate samples c and d in X
2142 * - linearly interpolate the results of last two operations in Y
2144 * result = lrp(lrp(a + b) + lrp(c + d))
2146 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
2147 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
2148 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
2149 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
2151 for (unsigned i
= 0; i
< 4; ++i
) {
2152 assert(i
< ARRAY_SIZE(texture_data
));
2155 /* Compute pixel coordinates */
2156 emit_add(vec16(x_sample_coords
), Xp_f
,
2157 brw_imm_f((float)(i
& 0x1) * (1.0f
/ key
->x_scale
)));
2158 emit_add(vec16(y_sample_coords
), Yp_f
,
2159 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0f
/ key
->y_scale
)));
2160 emit_mov(vec16(X
), x_sample_coords
);
2161 emit_mov(vec16(Y
), y_sample_coords
);
2163 /* The MCS value we fetch has to match up with the pixel that we're
2164 * sampling from. Since we sample from different pixels in each
2165 * iteration of this "for" loop, the call to mcs_fetch() should be
2166 * here inside the loop after computing the pixel coordinates.
2168 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
2171 /* Compute sample index and map the sample index to a sample number.
2172 * Sample index layout shows the numbering of slots in a rectangular
2173 * grid of samples with in a pixel. Sample number layout shows the
2174 * rectangular grid of samples roughly corresponding to the real sample
2175 * locations with in a pixel.
2176 * In case of 4x MSAA, layout of sample indices matches the layout of
2184 * In case of 8x MSAA the two layouts don't match.
2185 * sample index layout : --------- sample number layout : ---------
2186 * | 0 | 1 | | 5 | 2 |
2187 * --------- ---------
2188 * | 2 | 3 | | 4 | 6 |
2189 * --------- ---------
2190 * | 4 | 5 | | 0 | 3 |
2191 * --------- ---------
2192 * | 6 | 7 | | 7 | 1 |
2193 * --------- ---------
2195 * Fortunately, this can be done fairly easily as:
2196 * S' = (0x17306425 >> (S * 4)) & 0xf
2198 emit_frc(vec16(t1_f
), x_sample_coords
);
2199 emit_frc(vec16(t2_f
), y_sample_coords
);
2200 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
2201 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
2202 emit_add(vec16(t1_f
), t1_f
, t2_f
);
2203 emit_mov(vec16(S
), t1_f
);
2205 if (num_samples
== 8) {
2206 emit_mov(vec16(t2
), brw_imm_d(0x17306425));
2207 emit_shl(vec16(S
), S
, brw_imm_d(2));
2208 emit_shr(vec16(S
), t2
, S
);
2209 emit_and(vec16(S
), S
, brw_imm_d(0xf));
2211 texel_fetch(texture_data
[i
]);
2214 #define SAMPLE(x, y) offset(texture_data[x], y)
2215 for (int index
= 3; index
> 0; ) {
2216 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
2217 * Counter value of 8 in 'for' loop below is used to interpolate all
2218 * the color components.
2220 for (int k
= 0; k
< 8; k
+= 2)
2221 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
2223 vec8(SAMPLE(index
, k
)),
2224 vec8(SAMPLE(index
- 1, k
)));
2227 for (int k
= 0; k
< 8; k
+= 2)
2228 emit_lrp(vec8(SAMPLE(0, k
)),
2231 vec8(SAMPLE(0, k
)));
2236 * Emit code to look up a value in the texture using the SAMPLE message (which
2237 * does blending of MSAA surfaces).
2240 brw_blorp_blit_program::sample(struct brw_reg dst
)
2242 static const sampler_message_arg args
[2] = {
2243 SAMPLER_MESSAGE_ARG_U_FLOAT
,
2244 SAMPLER_MESSAGE_ARG_V_FLOAT
2247 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
2251 * Emit code to look up a value in the texture using the SAMPLE_LD message
2252 * (which does a simple texel fetch).
2255 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
2257 static const sampler_message_arg gen6_args
[5] = {
2258 SAMPLER_MESSAGE_ARG_U_INT
,
2259 SAMPLER_MESSAGE_ARG_V_INT
,
2260 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
2261 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
2262 SAMPLER_MESSAGE_ARG_SI_INT
2264 static const sampler_message_arg gen7_ld_args
[] = {
2265 SAMPLER_MESSAGE_ARG_U_INT
,
2266 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
2267 SAMPLER_MESSAGE_ARG_V_INT
,
2268 SAMPLER_MESSAGE_ARG_R_INT
2270 static const sampler_message_arg gen7_ld2dss_args
[3] = {
2271 SAMPLER_MESSAGE_ARG_SI_INT
,
2272 SAMPLER_MESSAGE_ARG_U_INT
,
2273 SAMPLER_MESSAGE_ARG_V_INT
2275 static const sampler_message_arg gen7_ld2dms_args
[4] = {
2276 SAMPLER_MESSAGE_ARG_SI_INT
,
2277 SAMPLER_MESSAGE_ARG_MCS_INT
,
2278 SAMPLER_MESSAGE_ARG_U_INT
,
2279 SAMPLER_MESSAGE_ARG_V_INT
2281 static const sampler_message_arg gen9_ld_args
[] = {
2282 SAMPLER_MESSAGE_ARG_U_INT
,
2283 SAMPLER_MESSAGE_ARG_V_INT
,
2284 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
2285 SAMPLER_MESSAGE_ARG_R_INT
2290 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
2295 switch (key
->tex_layout
) {
2296 case INTEL_MSAA_LAYOUT_IMS
:
2297 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
2300 * If this field is MSFMT_DEPTH_STENCIL
2301 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
2302 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
2304 * So fall through to emit the same message as we use for
2305 * INTEL_MSAA_LAYOUT_CMS.
2307 case INTEL_MSAA_LAYOUT_CMS
:
2308 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
2309 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
2311 case INTEL_MSAA_LAYOUT_UMS
:
2312 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
2313 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
2315 case INTEL_MSAA_LAYOUT_NONE
:
2318 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
2319 ARRAY_SIZE(gen7_ld_args
));
2321 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen9_ld_args
,
2322 ARRAY_SIZE(gen9_ld_args
));
2328 unreachable("Should not get here.");
2333 brw_blorp_blit_program::mcs_fetch()
2335 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
2336 SAMPLER_MESSAGE_ARG_U_INT
,
2337 SAMPLER_MESSAGE_ARG_V_INT
2339 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
2340 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
2344 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
2346 const sampler_message_arg
*args
,
2349 struct brw_reg mrf
=
2350 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
2351 for (int arg
= 0; arg
< num_args
; ++arg
) {
2352 switch (args
[arg
]) {
2353 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
2354 if (key
->bilinear_filter
)
2355 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
2356 retype(X
, BRW_REGISTER_TYPE_F
));
2358 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
2360 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
2361 if (key
->bilinear_filter
)
2362 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
2363 retype(Y
, BRW_REGISTER_TYPE_F
));
2365 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
2367 case SAMPLER_MESSAGE_ARG_U_INT
:
2370 case SAMPLER_MESSAGE_ARG_V_INT
:
2373 case SAMPLER_MESSAGE_ARG_R_INT
:
2374 emit_mov(mrf
, src_z
);
2376 case SAMPLER_MESSAGE_ARG_SI_INT
:
2377 /* Note: on Gen7, this code may be reached with s_is_zero==true
2378 * because in Gen7's ld2dss message, the sample index is the first
2379 * argument. When this happens, we need to move a 0 into the
2380 * appropriate message register.
2383 emit_mov(mrf
, brw_imm_ud(0));
2387 case SAMPLER_MESSAGE_ARG_MCS_INT
:
2388 switch (key
->tex_layout
) {
2389 case INTEL_MSAA_LAYOUT_CMS
:
2390 emit_mov(mrf
, mcs_data
);
2392 case INTEL_MSAA_LAYOUT_IMS
:
2393 /* When sampling from an IMS surface, MCS data is not relevant,
2394 * and the hardware ignores it. So don't bother populating it.
2398 /* We shouldn't be trying to send MCS data with any other
2401 assert (!"Unsupported layout for MCS data");
2405 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
2406 emit_mov(mrf
, brw_imm_ud(0));
2412 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
2415 mrf
.nr
- base_mrf
/* msg_length */);
2423 #undef SWAP_XY_AND_XPYP
2426 brw_blorp_get_blit_kernel(struct brw_context
*brw
,
2427 struct brw_blorp_params
*params
,
2428 const struct brw_blorp_blit_prog_key
*prog_key
)
2430 if (brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2431 prog_key
, sizeof(*prog_key
),
2432 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
))
2435 const unsigned *program
;
2436 unsigned program_size
;
2437 struct brw_blorp_prog_data prog_data
;
2439 /* Try and compile with NIR first. If that fails, fall back to the old
2440 * method of building shaders manually.
2442 nir_shader
*nir
= brw_blorp_build_nir_shader(brw
, prog_key
, &prog_data
);
2444 struct brw_wm_prog_key wm_key
;
2445 brw_blorp_init_wm_prog_key(&wm_key
);
2446 wm_key
.tex
.compressed_multisample_layout_mask
=
2447 prog_key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
;
2448 wm_key
.multisample_fbo
= prog_key
->rt_samples
> 1;
2450 program
= brw_blorp_compile_nir_shader(brw
, nir
, &wm_key
, false,
2451 &prog_data
, &program_size
);
2453 brw_blorp_blit_program
prog(brw
, prog_key
);
2454 program
= prog
.compile(brw
, INTEL_DEBUG
& DEBUG_BLORP
, &program_size
);
2455 prog_data
= prog
.prog_data
;
2458 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2459 prog_key
, sizeof(*prog_key
),
2460 program
, program_size
,
2461 &prog_data
, sizeof(prog_data
),
2462 ¶ms
->wm_prog_kernel
, ¶ms
->wm_prog_data
);
2466 brw_blorp_blit_program::render_target_write()
2468 struct brw_reg mrf_rt_write
=
2469 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
2472 /* If we may have killed pixels, then we need to send R0 and R1 in a header
2473 * so that the render target knows which pixels we killed.
2475 bool use_header
= key
->use_kill
;
2477 /* Copy R0/1 to MRF */
2478 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
2479 retype(R0
, BRW_REGISTER_TYPE_UD
));
2483 /* Copy texture data to MRFs */
2484 for (int i
= 0; i
< 4; ++i
) {
2485 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
2486 emit_mov(offset(mrf_rt_write
, mrf_offset
),
2487 offset(vec8(texture_data
[0]), 2*i
));
2491 /* Now write to the render target and terminate the thread */
2492 emit_render_target_write(
2494 brw
->gen
< 8 ? base_mrf
: -1,
2495 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
2501 brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform
*xform
,
2502 GLfloat src0
, GLfloat src1
,
2503 GLfloat dst0
, GLfloat dst1
,
2506 float scale
= (src1
- src0
) / (dst1
- dst0
);
2508 /* When not mirroring a coordinate (say, X), we need:
2509 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
2511 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
2513 * blorp program uses "round toward zero" to convert the
2514 * transformed floating point coordinates to integer coordinates,
2515 * whereas the behaviour we actually want is "round to nearest",
2516 * so 0.5 provides the necessary correction.
2518 xform
->multiplier
= scale
;
2519 xform
->offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
2521 /* When mirroring X we need:
2522 * src_x - src_x0 = dst_x1 - dst_x - 0.5
2524 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
2526 xform
->multiplier
= -scale
;
2527 xform
->offset
= src0
+ (dst1
- 0.5f
) * scale
;
2533 * Determine which MSAA layout the GPU pipeline should be configured for,
2534 * based on the chip generation, the number of samples, and the true layout of
2535 * the image in memory.
2537 inline intel_msaa_layout
2538 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
2539 intel_msaa_layout true_layout
)
2541 if (num_samples
<= 1) {
2542 /* Layout is used to determine if ld2dms is needed for sampling. In
2543 * single sampled case normal ld is enough avoiding also the need to
2544 * fetch mcs. Therefore simply set the layout to none.
2546 if (brw
->gen
>= 9 && true_layout
== INTEL_MSAA_LAYOUT_CMS
) {
2547 return INTEL_MSAA_LAYOUT_NONE
;
2550 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
2551 * format buffers, by transforming coordinates appropriately.
2553 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
2554 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2555 return INTEL_MSAA_LAYOUT_NONE
;
2557 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
2560 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
2561 if (brw
->gen
== 6) {
2562 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
2570 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
2571 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
2572 * the physical layer holding sample 0. So, for example, if
2573 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
2577 brw_blorp_blit_miptrees(struct brw_context
*brw
,
2578 struct intel_mipmap_tree
*src_mt
,
2579 unsigned src_level
, unsigned src_layer
,
2580 mesa_format src_format
, int src_swizzle
,
2581 struct intel_mipmap_tree
*dst_mt
,
2582 unsigned dst_level
, unsigned dst_layer
,
2583 mesa_format dst_format
,
2584 float src_x0
, float src_y0
,
2585 float src_x1
, float src_y1
,
2586 float dst_x0
, float dst_y0
,
2587 float dst_x1
, float dst_y1
,
2588 GLenum filter
, bool mirror_x
, bool mirror_y
,
2589 bool decode_srgb
, bool encode_srgb
)
2591 /* Get ready to blit. This includes depth resolving the src and dst
2592 * buffers if necessary. Note: it's not necessary to do a color resolve on
2593 * the destination buffer because we use the standard render path to render
2594 * to destination color buffers, and the standard render path is
2597 intel_miptree_resolve_color(brw
, src_mt
, INTEL_MIPTREE_IGNORE_CCS_E
);
2598 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
2599 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
2601 intel_miptree_prepare_mcs(brw
, dst_mt
);
2603 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
2604 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
2606 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
2607 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
2608 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
2609 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
2610 mirror_x
, mirror_y
);
2612 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
2613 src_format
= _mesa_get_srgb_format_linear(src_format
);
2615 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
2616 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
2618 struct brw_blorp_params params
;
2619 brw_blorp_params_init(¶ms
);
2621 brw_blorp_surface_info_init(brw
, ¶ms
.src
, src_mt
, src_level
,
2622 src_layer
, src_format
, false);
2623 brw_blorp_surface_info_init(brw
, ¶ms
.dst
, dst_mt
, dst_level
,
2624 dst_layer
, dst_format
, true);
2626 /* Even though we do multisample resolves at the time of the blit, OpenGL
2627 * specification defines them as if they happen at the time of rendering,
2628 * which means that the type of averaging we do during the resolve should
2629 * only depend on the source format; the destination format should be
2630 * ignored. But, specification doesn't seem to be strict about it.
2632 * It has been observed that mulitisample resolves produce slightly better
2633 * looking images when averaging is done using destination format. NVIDIA's
2634 * proprietary OpenGL driver also follow this approach. So, we choose to
2635 * follow it in our driver.
2637 * When multisampling, if the source and destination formats are equal
2638 * (aside from the color space), we choose to blit in sRGB space to get
2639 * this higher quality image.
2641 if (params
.src
.num_samples
> 1 &&
2642 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
2643 _mesa_get_srgb_format_linear(src_mt
->format
) ==
2644 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
2645 assert(brw
->format_supported_as_render_target
[dst_mt
->format
]);
2646 params
.dst
.brw_surfaceformat
= brw
->render_target_format
[dst_mt
->format
];
2647 params
.src
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
2650 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
2651 * texture, the above code configures the source format for L32_FLOAT or
2652 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
2653 * the SAMPLE message appears to handle multisampled L32_FLOAT and
2654 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
2655 * around the problem by using a source format of R32_FLOAT. This
2656 * shouldn't affect rendering correctness, since the destination format is
2657 * R32_FLOAT, so only the contents of the red channel matters.
2659 if (brw
->gen
== 6 &&
2660 params
.src
.num_samples
> 1 && params
.dst
.num_samples
<= 1 &&
2661 src_mt
->format
== dst_mt
->format
&&
2662 params
.dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
2663 params
.src
.brw_surfaceformat
= params
.dst
.brw_surfaceformat
;
2666 struct brw_blorp_blit_prog_key wm_prog_key
;
2667 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
2669 /* texture_data_type indicates the register type that should be used to
2670 * manipulate texture data.
2672 switch (_mesa_get_format_datatype(src_mt
->format
)) {
2673 case GL_UNSIGNED_NORMALIZED
:
2674 case GL_SIGNED_NORMALIZED
:
2676 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2678 case GL_UNSIGNED_INT
:
2679 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
2680 /* We process stencil as though it's an unsigned normalized color */
2681 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
2683 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
2687 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
2690 unreachable("Unrecognized blorp format");
2694 /* Gen7's rendering hardware only supports the IMS layout for depth and
2695 * stencil render targets. Blorp always maps its destination surface as
2696 * a color render target (even if it's actually a depth or stencil
2697 * buffer). So if the destination is IMS, we'll have to map it as a
2698 * single-sampled texture and interleave the samples ourselves.
2700 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
2701 params
.dst
.num_samples
= 0;
2704 if (params
.dst
.map_stencil_as_y_tiled
&& params
.dst
.num_samples
> 1) {
2705 /* If the destination surface is a W-tiled multisampled stencil buffer
2706 * that we're mapping as Y tiled, then we need to arrange for the WM
2707 * program to run once per sample rather than once per pixel, because
2708 * the memory layout of related samples doesn't match between W and Y
2711 wm_prog_key
.persample_msaa_dispatch
= true;
2714 if (params
.src
.num_samples
> 0 && params
.dst
.num_samples
> 1) {
2715 /* We are blitting from a multisample buffer to a multisample buffer, so
2716 * we must preserve samples within a pixel. This means we have to
2717 * arrange for the WM program to run once per sample rather than once
2720 wm_prog_key
.persample_msaa_dispatch
= true;
2723 /* Scaled blitting or not. */
2724 wm_prog_key
.blit_scaled
=
2725 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2726 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2728 /* Scaling factors used for bilinear filtering in multisample scaled
2731 wm_prog_key
.x_scale
= 2.0f
;
2732 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0f
;
2734 if (filter
== GL_LINEAR
&&
2735 params
.src
.num_samples
<= 1 && params
.dst
.num_samples
<= 1)
2736 wm_prog_key
.bilinear_filter
= true;
2738 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2739 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2740 base_format
!= GL_STENCIL_INDEX
&&
2741 !_mesa_is_format_integer(src_mt
->format
) &&
2742 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2743 /* We are downsampling a non-integer color buffer, so blend.
2745 * Regarding integer color buffers, the OpenGL ES 3.2 spec says:
2747 * "If the source formats are integer types or stencil values, a
2748 * single sample's value is selected for each pixel."
2750 * This implies we should not blend in that case.
2752 wm_prog_key
.blend
= true;
2755 /* src_samples and dst_samples are the true sample counts */
2756 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2757 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2759 /* tex_samples and rt_samples are the sample counts that are set up in
2762 wm_prog_key
.tex_samples
= params
.src
.num_samples
;
2763 wm_prog_key
.rt_samples
= params
.dst
.num_samples
;
2765 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2766 * use to access the source and destination surfaces.
2768 wm_prog_key
.tex_layout
=
2769 compute_msaa_layout_for_pipeline(brw
, params
.src
.num_samples
,
2770 params
.src
.msaa_layout
);
2771 wm_prog_key
.rt_layout
=
2772 compute_msaa_layout_for_pipeline(brw
, params
.dst
.num_samples
,
2773 params
.dst
.msaa_layout
);
2775 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2778 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2779 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2781 /* On gen9+ compressed single sampled buffers carry the same layout type as
2782 * multisampled. The difference is that they can be sampled using normal
2783 * ld message and as render target behave just like non-compressed surface
2784 * from compiler point of view. Therefore override the type in the program
2787 if (brw
->gen
>= 9 && params
.src
.num_samples
<= 1 &&
2788 src_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)
2789 wm_prog_key
.src_layout
= INTEL_MSAA_LAYOUT_NONE
;
2790 if (brw
->gen
>= 9 && params
.dst
.num_samples
<= 1 &&
2791 dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
)
2792 wm_prog_key
.dst_layout
= INTEL_MSAA_LAYOUT_NONE
;
2794 wm_prog_key
.src_tiled_w
= params
.src
.map_stencil_as_y_tiled
;
2795 wm_prog_key
.dst_tiled_w
= params
.dst
.map_stencil_as_y_tiled
;
2796 /* Round floating point values to nearest integer to avoid "off by one texel"
2797 * kind of errors when blitting.
2799 params
.x0
= params
.wm_push_consts
.dst_x0
= roundf(dst_x0
);
2800 params
.y0
= params
.wm_push_consts
.dst_y0
= roundf(dst_y0
);
2801 params
.x1
= params
.wm_push_consts
.dst_x1
= roundf(dst_x1
);
2802 params
.y1
= params
.wm_push_consts
.dst_y1
= roundf(dst_y1
);
2803 params
.wm_push_consts
.rect_grid_x1
=
2804 minify(src_mt
->logical_width0
, src_level
) * wm_prog_key
.x_scale
- 1.0f
;
2805 params
.wm_push_consts
.rect_grid_y1
=
2806 minify(src_mt
->logical_height0
, src_level
) * wm_prog_key
.y_scale
- 1.0f
;
2808 brw_blorp_setup_coord_transform(¶ms
.wm_push_consts
.x_transform
,
2809 src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2810 brw_blorp_setup_coord_transform(¶ms
.wm_push_consts
.y_transform
,
2811 src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2813 params
.wm_push_consts
.src_z
=
2814 params
.src
.mt
->target
== GL_TEXTURE_3D
? params
.src
.layer
: 0;
2816 if (params
.dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2817 /* We must expand the rectangle we send through the rendering pipeline,
2818 * to account for the fact that we are mapping the destination region as
2819 * single-sampled when it is in fact multisampled. We must also align
2820 * it to a multiple of the multisampling pattern, because the
2821 * differences between multisampled and single-sampled surface formats
2822 * will mean that pixels are scrambled within the multisampling pattern.
2823 * TODO: what if this makes the coordinates too large?
2825 * Note: this only works if the destination surface uses the IMS layout.
2826 * If it's UMS, then we have no choice but to set up the rendering
2827 * pipeline as multisampled.
2829 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2830 switch (dst_mt
->num_samples
) {
2832 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
2833 params
.y0
= ROUND_DOWN_TO(params
.y0
, 4);
2834 params
.x1
= ALIGN(params
.x1
* 2, 4);
2835 params
.y1
= ALIGN(params
.y1
, 4);
2838 params
.x0
= ROUND_DOWN_TO(params
.x0
* 2, 4);
2839 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
2840 params
.x1
= ALIGN(params
.x1
* 2, 4);
2841 params
.y1
= ALIGN(params
.y1
* 2, 4);
2844 params
.x0
= ROUND_DOWN_TO(params
.x0
* 4, 8);
2845 params
.y0
= ROUND_DOWN_TO(params
.y0
* 2, 4);
2846 params
.x1
= ALIGN(params
.x1
* 4, 8);
2847 params
.y1
= ALIGN(params
.y1
* 2, 4);
2850 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2852 wm_prog_key
.use_kill
= true;
2855 if (params
.dst
.map_stencil_as_y_tiled
) {
2856 /* We must modify the rectangle we send through the rendering pipeline
2857 * (and the size and x/y offset of the destination surface), to account
2858 * for the fact that we are mapping it as Y-tiled when it is in fact
2861 * Both Y tiling and W tiling can be understood as organizations of
2862 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2863 * is different, but the layout of the 32-byte sub-tiles within the 4k
2864 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2865 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2866 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2868 * Therefore, to account for the layout differences within the 32-byte
2869 * sub-tiles, we must expand the rectangle so the X coordinates of its
2870 * edges are multiples of 8 (the W sub-tile width), and its Y
2871 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2872 * Then we need to scale the X and Y coordinates of the rectangle to
2873 * account for the differences in aspect ratio between the Y and W
2874 * sub-tiles. We need to modify the layer width and height similarly.
2876 * A correction needs to be applied when MSAA is in use: since
2877 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2878 * we need to align the Y coordinates to multiples of 8, so that when
2879 * they are divided by two they are still multiples of 4.
2881 * Note: Since the x/y offset of the surface will be applied using the
2882 * SURFACE_STATE command packet, it will be invisible to the swizzling
2883 * code in the shader; therefore it needs to be in a multiple of the
2884 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2885 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2886 * buffer), and the miplevel alignment used for stencil buffers is 8
2887 * pixels horizontally and either 4 or 8 pixels vertically (see
2888 * intel_horizontal_texture_alignment_unit() and
2889 * intel_vertical_texture_alignment_unit()).
2891 * Note: Also, since the SURFACE_STATE command packet can only apply
2892 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2893 * vertically, it is important that the offsets will be multiples of
2894 * these sizes after they are converted into Y-tiled coordinates.
2895 * Fortunately they will be, since we know from above that the offsets
2896 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2897 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2899 * TODO: what if this makes the coordinates (or the texture size) too
2902 const unsigned x_align
= 8, y_align
= params
.dst
.num_samples
!= 0 ? 8 : 4;
2903 params
.x0
= ROUND_DOWN_TO(params
.x0
, x_align
) * 2;
2904 params
.y0
= ROUND_DOWN_TO(params
.y0
, y_align
) / 2;
2905 params
.x1
= ALIGN(params
.x1
, x_align
) * 2;
2906 params
.y1
= ALIGN(params
.y1
, y_align
) / 2;
2907 params
.dst
.width
= ALIGN(params
.dst
.width
, x_align
) * 2;
2908 params
.dst
.height
= ALIGN(params
.dst
.height
, y_align
) / 2;
2909 params
.dst
.x_offset
*= 2;
2910 params
.dst
.y_offset
/= 2;
2911 wm_prog_key
.use_kill
= true;
2914 if (params
.src
.map_stencil_as_y_tiled
) {
2915 /* We must modify the size and x/y offset of the source surface to
2916 * account for the fact that we are mapping it as Y-tiled when it is in
2919 * See the comments above concerning x/y offset alignment for the
2920 * destination surface.
2922 * TODO: what if this makes the texture size too large?
2924 const unsigned x_align
= 8, y_align
= params
.src
.num_samples
!= 0 ? 8 : 4;
2925 params
.src
.width
= ALIGN(params
.src
.width
, x_align
) * 2;
2926 params
.src
.height
= ALIGN(params
.src
.height
, y_align
) / 2;
2927 params
.src
.x_offset
*= 2;
2928 params
.src
.y_offset
/= 2;
2931 brw_blorp_get_blit_kernel(brw
, ¶ms
, &wm_prog_key
);
2933 params
.src
.swizzle
= src_swizzle
;
2935 brw_blorp_exec(brw
, ¶ms
);
2937 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
2939 if (intel_miptree_is_lossless_compressed(brw
, dst_mt
))
2940 dst_mt
->fast_clear_state
= INTEL_FAST_CLEAR_STATE_UNRESOLVED
;