i965/vec4: Init mlen for several send from GRF instructions.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_blorp_blit_eu.cpp
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/ralloc.h"
25 #include "brw_blorp_blit_eu.h"
26 #include "brw_blorp.h"
27 #include "brw_cfg.h"
28
29 brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw,
30 bool debug_flag)
31 : mem_ctx(ralloc_context(NULL)),
32 generator(brw, mem_ctx, (void *) rzalloc(mem_ctx, struct brw_wm_prog_key),
33 (struct brw_stage_prog_data *) rzalloc(mem_ctx, struct brw_wm_prog_data),
34 NULL, false, "BLORP")
35 {
36 if (debug_flag)
37 generator.enable_debug("blorp");
38 }
39
40 brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
41 {
42 ralloc_free(mem_ctx);
43 }
44
45 const unsigned *
46 brw_blorp_eu_emitter::get_program(unsigned *program_size)
47 {
48 cfg_t cfg(&insts);
49 generator.generate_code(&cfg, 16);
50
51 return generator.get_assembly(program_size);
52 }
53
54 /**
55 * Emit code that kills pixels whose X and Y coordinates are outside the
56 * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
57 * dst_x1, dst_y1).
58 */
59 void
60 brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
61 const struct brw_reg &y,
62 const struct brw_reg &dst_x0,
63 const struct brw_reg &dst_x1,
64 const struct brw_reg &dst_y0,
65 const struct brw_reg &dst_y1)
66 {
67 struct brw_reg f0 = brw_flag_reg(0, 0);
68 struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
69
70 emit_cmp(BRW_CONDITIONAL_GE, x, dst_x0);
71 emit_cmp(BRW_CONDITIONAL_GE, y, dst_y0)->predicate = BRW_PREDICATE_NORMAL;
72 emit_cmp(BRW_CONDITIONAL_L, x, dst_x1)->predicate = BRW_PREDICATE_NORMAL;
73 emit_cmp(BRW_CONDITIONAL_L, y, dst_y1)->predicate = BRW_PREDICATE_NORMAL;
74
75 fs_inst *inst = new (mem_ctx) fs_inst(BRW_OPCODE_AND, g1, f0, g1);
76 inst->force_writemask_all = true;
77 insts.push_tail(inst);
78 }
79
80 void
81 brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
82 enum opcode op,
83 unsigned base_mrf,
84 unsigned msg_length)
85 {
86 fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf),
87 fs_reg(0u));
88
89 inst->base_mrf = base_mrf;
90 inst->mlen = msg_length;
91 inst->header_present = false;
92
93 insts.push_tail(inst);
94 }
95
96 void
97 brw_blorp_eu_emitter::emit_render_target_write(const struct brw_reg &src0,
98 unsigned msg_reg_nr,
99 unsigned msg_length,
100 bool use_header)
101 {
102 fs_inst *inst = new (mem_ctx) fs_inst(FS_OPCODE_BLORP_FB_WRITE, 16);
103
104 inst->src[0] = src0;
105 inst->base_mrf = msg_reg_nr;
106 inst->mlen = msg_length;
107 inst->header_present = use_header;
108 inst->target = BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX;
109
110 insts.push_tail(inst);
111 }
112
113 void
114 brw_blorp_eu_emitter::emit_combine(enum opcode combine_opcode,
115 const struct brw_reg &dst,
116 const struct brw_reg &src_1,
117 const struct brw_reg &src_2)
118 {
119 assert(combine_opcode == BRW_OPCODE_ADD || combine_opcode == BRW_OPCODE_AVG);
120
121 insts.push_tail(new (mem_ctx) fs_inst(combine_opcode, dst, src_1, src_2));
122 }
123
124 fs_inst *
125 brw_blorp_eu_emitter::emit_cmp(enum brw_conditional_mod op,
126 const struct brw_reg &x,
127 const struct brw_reg &y)
128 {
129 fs_inst *cmp = new (mem_ctx) fs_inst(BRW_OPCODE_CMP,
130 vec16(brw_null_reg()), x, y);
131 cmp->conditional_mod = op;
132 insts.push_tail(cmp);
133 return cmp;
134 }
135