src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "glsl/ralloc.h"
  25 #include "brw_blorp_blit_eu.h"
  26 #include "brw_blorp.h"
  27
  28 brw_blorp_eu_emitter::brw_blorp_eu_emitter(struct brw_context *brw)
  29    : mem_ctx(ralloc_context(NULL))
  30 {
  31    brw_init_compile(brw, &func, mem_ctx);
  32
  33    /*
  34     * By default everything is emitted as 16-wide with only a few expections
  35     * handled explicitly either here in the compiler or by one of the specific
  36     * code emission calls.
  37     * It should be also noted that here in this file any alterations of the
  38     * compression control settings are only used to affect the execution size
  39     * of the instructions. The instruction template used to initialise all the
  40     * instructions is effectively not altered -- the value stays at zero
  41     * representing either GEN6_COMPRESSION_1Q or GEN6_COMPRESSION_1H depending
  42     * on the context.
  43     * If any other settings are used in the instruction headers, they are set
  44     * elsewhere by the individual code emission calls.
  45     */
  46    brw_set_compression_control(&func, BRW_COMPRESSION_COMPRESSED);
  47 }
  48
  49 brw_blorp_eu_emitter::~brw_blorp_eu_emitter()
  50 {
  51    ralloc_free(mem_ctx);
  52 }
  53
  54 const unsigned *
  55 brw_blorp_eu_emitter::get_program(unsigned *program_size, FILE *dump_file)
  56 {
  57    brw_set_uip_jip(&func);
  58
  59    if (unlikely(INTEL_DEBUG & DEBUG_BLORP)) {
  60       printf("Native code for BLORP blit:\n");
  61       brw_dump_compile(&func, dump_file, 0, func.next_insn_offset);
  62       printf("\n");
  63    }
  64
  65    return brw_get_program(&func, program_size);
  66 }
  67
  68 /**
  69  * Emit code that kills pixels whose X and Y coordinates are outside the
  70  * boundary of the rectangle defined by the push constants (dst_x0, dst_y0,
  71  * dst_x1, dst_y1).
  72  */
  73 void
  74 brw_blorp_eu_emitter::emit_kill_if_outside_rect(const struct brw_reg &x,
  75                                                 const struct brw_reg &y,
  76                                                 const struct brw_reg &dst_x0,
  77                                                 const struct brw_reg &dst_x1,
  78                                                 const struct brw_reg &dst_y0,
  79                                                 const struct brw_reg &dst_y1)
  80 {
  81    struct brw_reg f0 = brw_flag_reg(0, 0);
  82    struct brw_reg g1 = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
  83    struct brw_reg null32 = vec16(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
  84
  85    brw_CMP(&func, null32, BRW_CONDITIONAL_GE, x, dst_x0);
  86    brw_CMP(&func, null32, BRW_CONDITIONAL_GE, y, dst_y0);
  87    brw_CMP(&func, null32, BRW_CONDITIONAL_L, x, dst_x1);
  88    brw_CMP(&func, null32, BRW_CONDITIONAL_L, y, dst_y1);
  89
  90    brw_set_predicate_control(&func, BRW_PREDICATE_NONE);
  91
  92    struct brw_instruction *inst = brw_AND(&func, g1, f0, g1);
  93    inst->header.mask_control = BRW_MASK_DISABLE;
  94 }
  95
  96 void
  97 brw_blorp_eu_emitter::emit_texture_lookup(const struct brw_reg &dst,
  98                                           enum opcode op,
  99                                           unsigned base_mrf,
 100                                           unsigned msg_length)
 101 {
 102    unsigned msg_type;
 103
 104    switch (op) {
 105    case SHADER_OPCODE_TEX:
 106       msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
 107       break;
 108    case SHADER_OPCODE_TXF:
 109       msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 110       break;
 111    case SHADER_OPCODE_TXF_CMS:
 112       msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
 113       break;
 114    case SHADER_OPCODE_TXF_UMS:
 115       msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
 116       break;
 117    case SHADER_OPCODE_TXF_MCS:
 118       msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
 119       break;
 120    default:
 121       assert(!"Unsupported texture lookup operation");
 122    }
 123
 124    brw_SAMPLE(&func,
 125               retype(dst, BRW_REGISTER_TYPE_UW) /* dest */,
 126               base_mrf /* msg_reg_nr */,
 127               brw_message_reg(base_mrf) /* src0 */,
 128               BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
 129               0 /* sampler */,
 130               msg_type,
 131               8 /* response_length.  TODO: should be smaller for non-RGBA formats? */,
 132               msg_length,
 133               0 /* header_present */,
 134               BRW_SAMPLER_SIMD_MODE_SIMD16,
 135               BRW_SAMPLER_RETURN_FORMAT_FLOAT32);
 136 }