src/mesa/drivers/dri/i965/brw_blorp_emit.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_defines.h"
  31 #include "brw_state.h"
  32
  33 #include "blorp_priv.h"
  34 #include "vbo/vbo.h"
  35 #include "brw_draw.h"
  36
  37 static void
  38 gen6_blorp_emit_input_varying_data(struct brw_context *brw,
  39                                    const struct brw_blorp_params *params,
  40                                    unsigned *offset,
  41                                    unsigned *size)
  42 {
  43    const unsigned vec4_size_in_bytes = 4 * sizeof(float);
  44    const unsigned max_num_varyings =
  45       DIV_ROUND_UP(sizeof(params->wm_inputs), vec4_size_in_bytes);
  46    const unsigned num_varyings = params->wm_prog_data->num_varying_inputs;
  47
  48    *size = num_varyings * vec4_size_in_bytes;
  49
  50    const float *const inputs_src = (const float *)&params->wm_inputs;
  51    float *inputs = (float *)brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER,
  52                                             *size, 32, offset);
  53
  54    /* Walk over the attribute slots, determine if the attribute is used by
  55     * the program and when necessary copy the values from the input storage to
  56     * the vertex data buffer.
  57     */
  58    for (unsigned i = 0; i < max_num_varyings; i++) {
  59       const gl_varying_slot attr = VARYING_SLOT_VAR0 + i;
  60
  61       if (!(params->wm_prog_data->inputs_read & BITFIELD64_BIT(attr)))
  62          continue;
  63
  64       memcpy(inputs, inputs_src + i * 4, vec4_size_in_bytes);
  65
  66       inputs += 4;
  67    }
  68 }
  69
  70 static void
  71 gen6_blorp_emit_vertex_data(struct brw_context *brw,
  72                             const struct brw_blorp_params *params)
  73 {
  74    uint32_t vertex_offset;
  75    uint32_t const_data_offset = 0;
  76    unsigned const_data_size = 0;
  77
  78    /* Setup VBO for the rectangle primitive..
  79     *
  80     * A rectangle primitive (3DPRIM_RECTLIST) consists of only three
  81     * vertices. The vertices reside in screen space with DirectX coordinates
  82     * (that is, (0, 0) is the upper left corner).
  83     *
  84     *   v2 ------ implied
  85     *    |        |
  86     *    |        |
  87     *   v0 ----- v1
  88     *
  89     * Since the VS is disabled, the clipper loads each VUE directly from
  90     * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
  91     * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
  92     *   dw0: Reserved, MBZ.
  93     *   dw1: Render Target Array Index. The HiZ op does not use indexed
  94     *        vertices, so set the dword to 0.
  95     *   dw2: Viewport Index. The HiZ op disables viewport mapping and
  96     *        scissoring, so set the dword to 0.
  97     *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so
  98     *        set the dword to 0.
  99     *   dw4: Vertex Position X.
 100     *   dw5: Vertex Position Y.
 101     *   dw6: Vertex Position Z.
 102     *   dw7: Vertex Position W.
 103     *
 104     *   dw8: Flat vertex input 0
 105     *   dw9: Flat vertex input 1
 106     *   ...
 107     *   dwn: Flat vertex input n - 8
 108     *
 109     * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1
 110     * "Vertex URB Entry (VUE) Formats".
 111     *
 112     * Only vertex position X and Y are going to be variable, Z is fixed to
 113     * zero and W to one. Header words dw0-3 are all zero. There is no need to
 114     * include the fixed values in the vertex buffer. Vertex fetcher can be
 115     * instructed to fill vertex elements with constant values of one and zero
 116     * instead of reading them from the buffer.
 117     * Flat inputs are program constants that are not interpolated. Moreover
 118     * their values will be the same between vertices.
 119     *
 120     * See the vertex element setup below.
 121     */
 122    const float vertices[] = {
 123       /* v0 */ (float)params->x0, (float)params->y1,
 124       /* v1 */ (float)params->x1, (float)params->y1,
 125       /* v2 */ (float)params->x0, (float)params->y0,
 126    };
 127
 128    float *const vertex_data = (float *)brw_state_batch(
 129                                           brw, AUB_TRACE_VERTEX_BUFFER,
 130                                           sizeof(vertices), 32,
 131                                           &vertex_offset);
 132    memcpy(vertex_data, vertices, sizeof(vertices));
 133
 134    if (params->wm_prog_data && params->wm_prog_data->num_varying_inputs)
 135       gen6_blorp_emit_input_varying_data(brw, params,
 136                                          &const_data_offset,
 137                                          &const_data_size);
 138
 139    /* 3DSTATE_VERTEX_BUFFERS */
 140    const int num_buffers = 1 + (const_data_size > 0);
 141    const int batch_length = 1 + 4 * num_buffers;
 142
 143    BEGIN_BATCH(batch_length);
 144    OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
 145
 146    const unsigned blorp_num_vue_elems = 2;
 147    const unsigned stride = blorp_num_vue_elems * sizeof(float);
 148    EMIT_VERTEX_BUFFER_STATE(brw, 0 /* buffer_nr */, brw->batch.bo,
 149                             vertex_offset, vertex_offset + sizeof(vertices),
 150                             stride, 0 /* steprate */);
 151
 152    if (const_data_size) {
 153       /* Tell vertex fetcher not to advance the pointer in the buffer when
 154        * moving to the next vertex. This will effectively provide the same
 155        * data for all the vertices. For flat inputs only the data provided
 156        * for the first provoking vertex actually matters.
 157        */
 158       const unsigned stride_zero = 0;
 159       EMIT_VERTEX_BUFFER_STATE(brw, 1 /* buffer_nr */, brw->batch.bo,
 160                                const_data_offset,
 161                                const_data_offset + const_data_size,
 162                                stride_zero, 0 /* step_rate */);
 163    }
 164
 165    ADVANCE_BATCH();
 166 }
 167
 168 void
 169 gen6_blorp_emit_vertices(struct brw_context *brw,
 170                          const struct brw_blorp_params *params)
 171 {
 172    gen6_blorp_emit_vertex_data(brw, params);
 173
 174    const unsigned num_varyings =
 175       params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
 176    const unsigned num_elements = 2 + num_varyings;
 177    const int batch_length = 1 + 2 * num_elements;
 178
 179    BEGIN_BATCH(batch_length);
 180
 181    /* 3DSTATE_VERTEX_ELEMENTS
 182     *
 183     * Fetch dwords 0 - 7 from each VUE. See the comments above where
 184     * the vertex_bo is filled with data. First element contains dwords
 185     * for the VUE header, second the actual position values and the
 186     * remaining contain the flat inputs.
 187     */
 188    {
 189       OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (batch_length - 2));
 190       /* Element 0 */
 191       OUT_BATCH(GEN6_VE0_VALID |
 192                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 193                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
 194       OUT_BATCH(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_0_SHIFT |
 195                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_1_SHIFT |
 196                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT |
 197                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT);
 198       /* Element 1 */
 199       OUT_BATCH(GEN6_VE0_VALID |
 200                 BRW_SURFACEFORMAT_R32G32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 201                 0 << BRW_VE0_SRC_OFFSET_SHIFT);
 202       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 203                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 204                 BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT |
 205                 BRW_VE1_COMPONENT_STORE_1_FLT << BRW_VE1_COMPONENT_3_SHIFT);
 206    }
 207
 208    for (unsigned i = 0; i < num_varyings; ++i) {
 209       /* Element 2 + i */
 210       OUT_BATCH(1 << GEN6_VE0_INDEX_SHIFT |
 211                 GEN6_VE0_VALID |
 212                 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT |
 213                 (i * 4 * sizeof(float)) << BRW_VE0_SRC_OFFSET_SHIFT);
 214       OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT |
 215                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT |
 216                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT |
 217                 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT);
 218    }
 219
 220    ADVANCE_BATCH();
 221 }
 222
 223
 224 /* BLEND_STATE */
 225 uint32_t
 226 gen6_blorp_emit_blend_state(struct brw_context *brw,
 227                             const struct brw_blorp_params *params)
 228 {
 229    uint32_t cc_blend_state_offset;
 230
 231    assume(params->num_draw_buffers);
 232
 233    const unsigned size = params->num_draw_buffers *
 234                          sizeof(struct gen6_blend_state);
 235    struct gen6_blend_state *blend = (struct gen6_blend_state *)
 236       brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
 237                       &cc_blend_state_offset);
 238
 239    memset(blend, 0, size);
 240
 241    for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
 242       blend[i].blend1.pre_blend_clamp_enable = 1;
 243       blend[i].blend1.post_blend_clamp_enable = 1;
 244       blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
 245
 246       blend[i].blend1.write_disable_r = params->color_write_disable[0];
 247       blend[i].blend1.write_disable_g = params->color_write_disable[1];
 248       blend[i].blend1.write_disable_b = params->color_write_disable[2];
 249       blend[i].blend1.write_disable_a = params->color_write_disable[3];
 250    }
 251
 252    return cc_blend_state_offset;
 253 }
 254
 255
 256 /* CC_STATE */
 257 uint32_t
 258 gen6_blorp_emit_cc_state(struct brw_context *brw)
 259 {
 260    uint32_t cc_state_offset;
 261
 262    struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *)
 263       brw_state_batch(brw, AUB_TRACE_CC_STATE,
 264                       sizeof(gen6_color_calc_state), 64,
 265                       &cc_state_offset);
 266    memset(cc, 0, sizeof(*cc));
 267
 268    return cc_state_offset;
 269 }
 270
 271
 272 /**
 273  * \param out_offset is relative to
 274  *        CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 275  */
 276 uint32_t
 277 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 278                                     const struct brw_blorp_params *params)
 279 {
 280    uint32_t depthstencil_offset;
 281
 282    struct gen6_depth_stencil_state *state;
 283    state = (struct gen6_depth_stencil_state *)
 284       brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
 285                       sizeof(*state), 64,
 286                       &depthstencil_offset);
 287    memset(state, 0, sizeof(*state));
 288
 289    /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2:
 290     *   - 7.5.3.1 Depth Buffer Clear
 291     *   - 7.5.3.2 Depth Buffer Resolve
 292     *   - 7.5.3.3 Hierarchical Depth Buffer Resolve
 293     */
 294    state->ds2.depth_write_enable = 1;
 295    if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) {
 296       state->ds2.depth_test_enable = 1;
 297       state->ds2.depth_test_func = BRW_COMPAREFUNCTION_NEVER;
 298    }
 299
 300    return depthstencil_offset;
 301 }
 302
 303
 304 /* BINDING_TABLE.  See brw_wm_binding_table(). */
 305 uint32_t
 306 gen6_blorp_emit_binding_table(struct brw_context *brw,
 307                               uint32_t wm_surf_offset_renderbuffer,
 308                               uint32_t wm_surf_offset_texture)
 309 {
 310    uint32_t wm_bind_bo_offset;
 311    uint32_t *bind = (uint32_t *)
 312       brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
 313                       sizeof(uint32_t) *
 314                       BRW_BLORP_NUM_BINDING_TABLE_ENTRIES,
 315                       32, /* alignment */
 316                       &wm_bind_bo_offset);
 317    bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] =
 318       wm_surf_offset_renderbuffer;
 319    bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture;
 320
 321    return wm_bind_bo_offset;
 322 }
 323
 324
 325 /**
 326  * SAMPLER_STATE.  See brw_update_sampler_state().
 327  */
 328 uint32_t
 329 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 330                               unsigned tex_filter, unsigned max_lod,
 331                               bool non_normalized_coords)
 332 {
 333    uint32_t sampler_offset;
 334    uint32_t *sampler_state = (uint32_t *)
 335       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 16, 32, &sampler_offset);
 336
 337    unsigned address_rounding = BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 338                                BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 339                                BRW_ADDRESS_ROUNDING_ENABLE_R_MIN |
 340                                BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 341                                BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 342                                BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 343
 344    /* XXX: I don't think that using firstLevel, lastLevel works,
 345     * because we always setup the surface state as if firstLevel ==
 346     * level zero.  Probably have to subtract firstLevel from each of
 347     * these:
 348     */
 349    brw_emit_sampler_state(brw,
 350                           sampler_state,
 351                           sampler_offset,
 352                           tex_filter, /* min filter */
 353                           tex_filter, /* mag filter */
 354                           BRW_MIPFILTER_NONE,
 355                           BRW_ANISORATIO_2,
 356                           address_rounding,
 357                           BRW_TEXCOORDMODE_CLAMP,
 358                           BRW_TEXCOORDMODE_CLAMP,
 359                           BRW_TEXCOORDMODE_CLAMP,
 360                           0, /* min LOD */
 361                           max_lod,
 362                           0, /* LOD bias */
 363                           0, /* shadow function */
 364                           non_normalized_coords,
 365                           0); /* border color offset - unused */
 366
 367    return sampler_offset;
 368 }
 369
 370
 371 /* 3DSTATE_CLIP
 372  *
 373  * Disable the clipper.
 374  *
 375  * The BLORP op emits a rectangle primitive, which requires clipping to
 376  * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1
 377  * Section 1.3 "3D Primitives Overview":
 378  *    RECTLIST:
 379  *    Either the CLIP unit should be DISABLED, or the CLIP unit's Clip
 380  *    Mode should be set to a value other than CLIPMODE_NORMAL.
 381  *
 382  * Also disable perspective divide. This doesn't change the clipper's
 383  * output, but does spare a few electrons.
 384  */
 385 void
 386 gen6_blorp_emit_clip_disable(struct brw_context *brw)
 387 {
 388    BEGIN_BATCH(4);
 389    OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
 390    OUT_BATCH(0);
 391    OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE);
 392    OUT_BATCH(0);
 393    ADVANCE_BATCH();
 394 }
 395
 396
 397 /* 3DSTATE_DRAWING_RECTANGLE */
 398 void
 399 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 400                                   const struct brw_blorp_params *params)
 401 {
 402    BEGIN_BATCH(4);
 403    OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
 404    OUT_BATCH(0);
 405    OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0xffff) |
 406              ((MAX2(params->y1, params->y0) - 1) << 16));
 407    OUT_BATCH(0);
 408    ADVANCE_BATCH();
 409 }
 410
 411
 412 /* Once vertex fetcher has written full VUE entries with complete
 413  * header the space requirement is as follows per vertex (in bytes):
 414  *
 415  *     Header    Position    Program constants
 416  *   +--------+------------+-------------------+
 417  *   |   16   |     16     |      n x 16       |
 418  *   +--------+------------+-------------------+
 419  *
 420  * where 'n' stands for number of varying inputs expressed as vec4s.
 421  *
 422  * The URB size is in turn expressed in 64 bytes (512 bits).
 423  */
 424 static unsigned
 425 gen7_blorp_get_vs_entry_size(const struct brw_blorp_params *params)
 426 {
 427     const unsigned num_varyings =
 428        params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
 429     const unsigned total_needed = 16 + 16 + num_varyings * 16;
 430
 431    return DIV_ROUND_UP(total_needed, 64);
 432 }
 433
 434 /* 3DSTATE_URB_VS
 435  * 3DSTATE_URB_HS
 436  * 3DSTATE_URB_DS
 437  * 3DSTATE_URB_GS
 438  *
 439  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
 440  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
 441  *
 442  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
 443  *     programmed in order for the programming of this state to be
 444  *     valid.
 445  */
 446 void
 447 gen7_blorp_emit_urb_config(struct brw_context *brw,
 448                            const struct brw_blorp_params *params)
 449 {
 450    const unsigned vs_entry_size = gen7_blorp_get_vs_entry_size(params);
 451
 452    if (!(brw->ctx.NewDriverState & (BRW_NEW_CONTEXT | BRW_NEW_URB_SIZE)) &&
 453        brw->urb.vsize >= vs_entry_size)
 454       return;
 455
 456    brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE;
 457
 458    gen7_upload_urb(brw, vs_entry_size, false, false);
 459 }
 460
 461
 462 /* 3DSTATE_BLEND_STATE_POINTERS */
 463 void
 464 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 465                                     uint32_t cc_blend_state_offset)
 466 {
 467    BEGIN_BATCH(2);
 468    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
 469    OUT_BATCH(cc_blend_state_offset | 1);
 470    ADVANCE_BATCH();
 471 }
 472
 473
 474 /* 3DSTATE_CC_STATE_POINTERS */
 475 void
 476 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 477                                  uint32_t cc_state_offset)
 478 {
 479    BEGIN_BATCH(2);
 480    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 481    OUT_BATCH(cc_state_offset | 1);
 482    ADVANCE_BATCH();
 483 }
 484
 485 void
 486 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
 487 {
 488    struct brw_cc_viewport *ccv;
 489    uint32_t cc_vp_offset;
 490
 491    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 492                                                    sizeof(*ccv), 32,
 493                                                    &cc_vp_offset);
 494    ccv->min_depth = 0.0;
 495    ccv->max_depth = 1.0;
 496
 497    BEGIN_BATCH(2);
 498    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 499    OUT_BATCH(cc_vp_offset);
 500    ADVANCE_BATCH();
 501 }
 502
 503
 504 /* 3DSTATE_TE
 505  *
 506  * Disable the tesselation engine.
 507  */
 508 void
 509 gen7_blorp_emit_te_disable(struct brw_context *brw)
 510 {
 511    BEGIN_BATCH(4);
 512    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 513    OUT_BATCH(0);
 514    OUT_BATCH(0);
 515    OUT_BATCH(0);
 516    ADVANCE_BATCH();
 517 }
 518
 519
 520 void
 521 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 522                                           uint32_t wm_bind_bo_offset)
 523 {
 524    BEGIN_BATCH(2);
 525    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 526    OUT_BATCH(wm_bind_bo_offset);
 527    ADVANCE_BATCH();
 528 }
 529
 530
 531 void
 532 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 533                                           uint32_t sampler_offset)
 534 {
 535    BEGIN_BATCH(2);
 536    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 537    OUT_BATCH(sampler_offset);
 538    ADVANCE_BATCH();
 539 }
 540
 541
 542 /* 3DSTATE_CLEAR_PARAMS
 543  *
 544  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 545  * 3DSTATE_CLEAR_PARAMS:
 546  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 547  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 548  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 549  */
 550 void
 551 gen7_blorp_emit_clear_params(struct brw_context *brw,
 552                              const struct brw_blorp_params *params)
 553 {
 554    BEGIN_BATCH(3);
 555    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 556    OUT_BATCH(params->depth.clear_color.u32[0]);
 557    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 558    ADVANCE_BATCH();
 559 }
 560
 561
 562 /* 3DPRIMITIVE */
 563 void
 564 gen7_blorp_emit_primitive(struct brw_context *brw,
 565                           const struct brw_blorp_params *params)
 566 {
 567    BEGIN_BATCH(7);
 568    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 569    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 570              _3DPRIM_RECTLIST);
 571    OUT_BATCH(3); /* vertex count per instance */
 572    OUT_BATCH(0);
 573    OUT_BATCH(params->num_layers); /* instance count */
 574    OUT_BATCH(0);
 575    OUT_BATCH(0);
 576    ADVANCE_BATCH();
 577 }