1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <util/u_atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "common/gen_debug.h"
60 #include "common/gen_device_info.h"
61 #include "libdrm_macros.h"
62 #include "main/macros.h"
63 #include "util/macros.h"
64 #include "util/hash_table.h"
65 #include "util/list.h"
66 #include "brw_bufmgr.h"
67 #include "brw_context.h"
80 #define memclear(s) memset(&s, 0, sizeof(s))
82 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
85 atomic_add_unless(int *v
, int add
, int unless
)
89 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
94 struct bo_cache_bucket
{
95 struct list_head head
;
102 pthread_mutex_t lock
;
104 /** Array of lists of cached gem objects of power-of-two sizes */
105 struct bo_cache_bucket cache_bucket
[14 * 4];
109 struct hash_table
*name_table
;
110 struct hash_table
*handle_table
;
116 static int bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
119 static void bo_free(struct brw_bo
*bo
);
122 key_hash_uint(const void *key
)
124 return _mesa_hash_data(key
, 4);
128 key_uint_equal(const void *a
, const void *b
)
130 return *((unsigned *) a
) == *((unsigned *) b
);
133 static struct brw_bo
*
134 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
136 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
137 return entry
? (struct brw_bo
*) entry
->data
: NULL
;
141 bo_tile_size(struct brw_bufmgr
*bufmgr
, uint64_t size
, uint32_t tiling
)
143 if (tiling
== I915_TILING_NONE
)
146 /* 965+ just need multiples of page size for tiling */
147 return ALIGN(size
, 4096);
151 * Round a given pitch up to the minimum required for X tiling on a
152 * given chip. We use 512 as the minimum to allow for a later tiling
156 bo_tile_pitch(struct brw_bufmgr
*bufmgr
, uint32_t pitch
, uint32_t tiling
)
158 unsigned long tile_width
;
160 /* If untiled, then just align it so that we can do rendering
161 * to it with the 3D engine.
163 if (tiling
== I915_TILING_NONE
)
164 return ALIGN(pitch
, 64);
166 if (tiling
== I915_TILING_X
)
171 /* 965 is flexible */
172 return ALIGN(pitch
, tile_width
);
175 static struct bo_cache_bucket
*
176 bucket_for_size(struct brw_bufmgr
*bufmgr
, uint64_t size
)
180 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
181 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
182 if (bucket
->size
>= size
) {
191 brw_bo_reference(struct brw_bo
*bo
)
193 p_atomic_inc(&bo
->refcount
);
197 brw_bo_busy(struct brw_bo
*bo
)
199 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
200 struct drm_i915_gem_busy busy
;
204 busy
.handle
= bo
->gem_handle
;
206 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
208 bo
->idle
= !busy
.busy
;
215 brw_bo_madvise(struct brw_bo
*bo
, int state
)
217 struct drm_i915_gem_madvise madv
;
220 madv
.handle
= bo
->gem_handle
;
223 drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
225 return madv
.retained
;
228 /* drop the oldest entries that have been purged by the kernel */
230 brw_bo_cache_purge_bucket(struct brw_bufmgr
*bufmgr
,
231 struct bo_cache_bucket
*bucket
)
233 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
234 if (brw_bo_madvise(bo
, I915_MADV_DONTNEED
))
242 static struct brw_bo
*
243 bo_alloc_internal(struct brw_bufmgr
*bufmgr
,
247 uint32_t tiling_mode
,
248 uint32_t stride
, uint64_t alignment
)
251 unsigned int page_size
= getpagesize();
253 struct bo_cache_bucket
*bucket
;
254 bool alloc_from_cache
;
256 bool for_render
= false;
258 if (flags
& BO_ALLOC_FOR_RENDER
)
261 /* Round the allocated size up to a power of two number of pages. */
262 bucket
= bucket_for_size(bufmgr
, size
);
264 /* If we don't have caching at this size, don't actually round the
267 if (bucket
== NULL
) {
269 if (bo_size
< page_size
)
272 bo_size
= bucket
->size
;
275 pthread_mutex_lock(&bufmgr
->lock
);
276 /* Get a buffer out of the cache if available */
278 alloc_from_cache
= false;
279 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
281 /* Allocate new render-target BOs from the tail (MRU)
282 * of the list, as it will likely be hot in the GPU
283 * cache and in the aperture for us.
285 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.prev
, head
);
287 alloc_from_cache
= true;
288 bo
->align
= alignment
;
290 assert(alignment
== 0);
291 /* For non-render-target BOs (where we're probably
292 * going to map it first thing in order to fill it
293 * with data), check if the last BO in the cache is
294 * unbusy, and only reuse in that case. Otherwise,
295 * allocating a new buffer is probably faster than
296 * waiting for the GPU to finish.
298 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.next
, head
);
299 if (!brw_bo_busy(bo
)) {
300 alloc_from_cache
= true;
305 if (alloc_from_cache
) {
306 if (!brw_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
308 brw_bo_cache_purge_bucket(bufmgr
, bucket
);
312 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
319 if (!alloc_from_cache
) {
320 struct drm_i915_gem_create create
;
322 bo
= calloc(1, sizeof(*bo
));
330 create
.size
= bo_size
;
332 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
338 bo
->gem_handle
= create
.handle
;
339 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
342 bo
->align
= alignment
;
344 bo
->tiling_mode
= I915_TILING_NONE
;
345 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
348 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
353 p_atomic_set(&bo
->refcount
, 1);
355 bo
->cache_coherent
= bufmgr
->has_llc
;
357 pthread_mutex_unlock(&bufmgr
->lock
);
359 DBG("bo_create: buf %d (%s) %ldb\n", bo
->gem_handle
, bo
->name
, size
);
366 pthread_mutex_unlock(&bufmgr
->lock
);
371 brw_bo_alloc(struct brw_bufmgr
*bufmgr
,
372 const char *name
, uint64_t size
, uint64_t alignment
)
374 return bo_alloc_internal(bufmgr
, name
, size
, 0, I915_TILING_NONE
, 0, 0);
378 brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
, const char *name
,
379 uint64_t size
, uint32_t tiling_mode
, uint32_t pitch
,
382 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling_mode
, pitch
, 0);
386 brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
, const char *name
,
387 int x
, int y
, int cpp
, uint32_t tiling
,
388 uint32_t *pitch
, unsigned flags
)
392 unsigned long aligned_y
, height_alignment
;
394 /* If we're tiled, our allocations are in 8 or 32-row blocks,
395 * so failure to align our height means that we won't allocate
398 * If we're untiled, we still have to align to 2 rows high
399 * because the data port accesses 2x2 blocks even if the
400 * bottom row isn't to be rendered, so failure to align means
401 * we could walk off the end of the GTT and fault. This is
402 * documented on 965, and may be the case on older chipsets
403 * too so we try to be careful.
406 height_alignment
= 2;
408 if (tiling
== I915_TILING_X
)
409 height_alignment
= 8;
410 else if (tiling
== I915_TILING_Y
)
411 height_alignment
= 32;
412 aligned_y
= ALIGN(y
, height_alignment
);
415 stride
= bo_tile_pitch(bufmgr
, stride
, tiling
);
416 size
= stride
* aligned_y
;
417 size
= bo_tile_size(bufmgr
, size
, tiling
);
420 if (tiling
== I915_TILING_NONE
)
423 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling
, stride
, 0);
427 * Returns a brw_bo wrapping the given buffer object handle.
429 * This can be used when one application needs to pass a buffer object
433 brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
434 const char *name
, unsigned int handle
)
438 struct drm_gem_open open_arg
;
439 struct drm_i915_gem_get_tiling get_tiling
;
441 /* At the moment most applications only have a few named bo.
442 * For instance, in a DRI client only the render buffers passed
443 * between X and the client are named. And since X returns the
444 * alternating names for the front/back buffer a linear search
445 * provides a sufficiently fast match.
447 pthread_mutex_lock(&bufmgr
->lock
);
448 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
450 brw_bo_reference(bo
);
455 open_arg
.name
= handle
;
456 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
458 DBG("Couldn't reference %s handle 0x%08x: %s\n",
459 name
, handle
, strerror(errno
));
463 /* Now see if someone has used a prime handle to get this
464 * object from the kernel before by looking through the list
465 * again for a matching gem_handle
467 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
469 brw_bo_reference(bo
);
473 bo
= calloc(1, sizeof(*bo
));
477 p_atomic_set(&bo
->refcount
, 1);
479 bo
->size
= open_arg
.size
;
482 bo
->gem_handle
= open_arg
.handle
;
484 bo
->global_name
= handle
;
485 bo
->reusable
= false;
488 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
489 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
491 memclear(get_tiling
);
492 get_tiling
.handle
= bo
->gem_handle
;
493 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
497 bo
->tiling_mode
= get_tiling
.tiling_mode
;
498 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
499 /* XXX stride is unknown */
500 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
503 pthread_mutex_unlock(&bufmgr
->lock
);
508 pthread_mutex_unlock(&bufmgr
->lock
);
513 bo_free(struct brw_bo
*bo
)
515 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
516 struct drm_gem_close close
;
517 struct hash_entry
*entry
;
521 VG(VALGRIND_FREELIKE_BLOCK(bo
->map_cpu
, 0));
522 drm_munmap(bo
->map_cpu
, bo
->size
);
525 VG(VALGRIND_FREELIKE_BLOCK(bo
->map_wc
, 0));
526 drm_munmap(bo
->map_wc
, bo
->size
);
529 drm_munmap(bo
->map_gtt
, bo
->size
);
532 if (bo
->global_name
) {
533 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
534 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
536 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
537 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
539 /* Close this object */
541 close
.handle
= bo
->gem_handle
;
542 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
544 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
545 bo
->gem_handle
, bo
->name
, strerror(errno
));
550 /** Frees all cached buffers significantly older than @time. */
552 cleanup_bo_cache(struct brw_bufmgr
*bufmgr
, time_t time
)
556 if (bufmgr
->time
== time
)
559 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
560 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
562 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
563 if (time
- bo
->free_time
<= 1)
576 bo_unreference_final(struct brw_bo
*bo
, time_t time
)
578 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
579 struct bo_cache_bucket
*bucket
;
581 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
583 bucket
= bucket_for_size(bufmgr
, bo
->size
);
584 /* Put the buffer into our internal cache for reuse if we can. */
585 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
586 brw_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
587 bo
->free_time
= time
;
592 list_addtail(&bo
->head
, &bucket
->head
);
599 brw_bo_unreference(struct brw_bo
*bo
)
604 assert(p_atomic_read(&bo
->refcount
) > 0);
606 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
607 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
608 struct timespec time
;
610 clock_gettime(CLOCK_MONOTONIC
, &time
);
612 pthread_mutex_lock(&bufmgr
->lock
);
614 if (p_atomic_dec_zero(&bo
->refcount
)) {
615 bo_unreference_final(bo
, time
.tv_sec
);
616 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
619 pthread_mutex_unlock(&bufmgr
->lock
);
624 set_domain(struct brw_context
*brw
, const char *action
,
625 struct brw_bo
*bo
, uint32_t read_domains
, uint32_t write_domain
)
627 struct drm_i915_gem_set_domain sd
= {
628 .handle
= bo
->gem_handle
,
629 .read_domains
= read_domains
,
630 .write_domain
= write_domain
,
633 double elapsed
= unlikely(brw
&& brw
->perf_debug
) ? -get_time() : 0.0;
635 if (drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0) {
636 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s.\n",
637 __FILE__
, __LINE__
, bo
->gem_handle
, read_domains
, write_domain
,
641 if (unlikely(brw
&& brw
->perf_debug
)) {
642 elapsed
+= get_time();
643 if (elapsed
> 1e-5) /* 0.01ms */
644 perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n",
645 action
, bo
->name
, elapsed
* 1000);
650 print_flags(unsigned flags
)
652 if (flags
& MAP_READ
)
654 if (flags
& MAP_WRITE
)
656 if (flags
& MAP_ASYNC
)
658 if (flags
& MAP_PERSISTENT
)
660 if (flags
& MAP_COHERENT
)
668 brw_bo_map_cpu(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
670 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
673 struct drm_i915_gem_mmap mmap_arg
;
676 DBG("brw_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
679 mmap_arg
.handle
= bo
->gem_handle
;
680 mmap_arg
.size
= bo
->size
;
681 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
684 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
685 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
688 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg
.addr_ptr
, mmap_arg
.size
, 0, 1));
689 map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
691 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
692 VG(VALGRIND_FREELIKE_BLOCK(map
, 0));
693 drm_munmap(map
, bo
->size
);
696 DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
700 if (!(flags
& MAP_ASYNC
) || !bufmgr
->has_llc
) {
701 set_domain(brw
, "CPU mapping", bo
, I915_GEM_DOMAIN_CPU
,
702 flags
& MAP_WRITE
? I915_GEM_DOMAIN_CPU
: 0);
709 brw_bo_map_gtt(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
711 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
713 /* Get a mapping of the buffer if we haven't before. */
714 if (bo
->map_gtt
== NULL
) {
715 struct drm_i915_gem_mmap_gtt mmap_arg
;
718 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
721 mmap_arg
.handle
= bo
->gem_handle
;
723 /* Get the fake offset back... */
724 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
726 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
727 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
728 pthread_mutex_unlock(&bufmgr
->lock
);
732 /* and mmap it. We don't need to use VALGRIND_MALLOCLIKE_BLOCK
733 * because Valgrind will already intercept this mmap call.
735 map
= drm_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
736 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
737 if (map
== MAP_FAILED
) {
738 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
739 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
743 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
744 drm_munmap(map
, bo
->size
);
748 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
751 if (!(flags
& MAP_ASYNC
) || !bufmgr
->has_llc
) {
752 set_domain(brw
, "GTT mapping", bo
,
753 I915_GEM_DOMAIN_GTT
, I915_GEM_DOMAIN_GTT
);
760 can_map_cpu(struct brw_bo
*bo
, unsigned flags
)
762 if (bo
->cache_coherent
)
765 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
766 * across batch flushes where the kernel will change cache domains of the
767 * bo, invalidating continued access to the CPU mmap on non-LLC device.
769 * Similarly, ASYNC typically means that the buffer will be accessed via
770 * both the CPU and the GPU simultaneously. Batches may be executed that
771 * use the BO even while it is mapped. While OpenGL technically disallows
772 * most drawing while non-persistent mappings are active, we may still use
773 * the GPU for blits or other operations, causing batches to happen at
774 * inconvenient times.
776 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
779 return !(flags
& MAP_WRITE
);
783 brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
785 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
786 return brw_bo_map_gtt(brw
, bo
, flags
);
787 else if (can_map_cpu(bo
, flags
))
788 return brw_bo_map_cpu(brw
, bo
, flags
);
790 return brw_bo_map_gtt(brw
, bo
, flags
);
794 brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
795 uint64_t size
, const void *data
)
797 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
798 struct drm_i915_gem_pwrite pwrite
;
802 pwrite
.handle
= bo
->gem_handle
;
803 pwrite
.offset
= offset
;
805 pwrite
.data_ptr
= (uint64_t) (uintptr_t) data
;
806 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
809 DBG("%s:%d: Error writing data to buffer %d: "
810 "(%"PRIu64
" %"PRIu64
") %s .\n",
811 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
818 brw_bo_get_subdata(struct brw_bo
*bo
, uint64_t offset
,
819 uint64_t size
, void *data
)
821 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
822 struct drm_i915_gem_pread pread
;
826 pread
.handle
= bo
->gem_handle
;
827 pread
.offset
= offset
;
829 pread
.data_ptr
= (uint64_t) (uintptr_t) data
;
830 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PREAD
, &pread
);
833 DBG("%s:%d: Error reading data from buffer %d: "
834 "(%"PRIu64
" %"PRIu64
") %s .\n",
835 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
841 /** Waits for all GPU rendering with the object to have completed. */
843 brw_bo_wait_rendering(struct brw_bo
*bo
)
845 /* We require a kernel recent enough for WAIT_IOCTL support.
846 * See intel_init_bufmgr()
852 * Waits on a BO for the given amount of time.
854 * @bo: buffer object to wait for
855 * @timeout_ns: amount of time to wait in nanoseconds.
856 * If value is less than 0, an infinite wait will occur.
858 * Returns 0 if the wait was successful ie. the last batch referencing the
859 * object has completed within the allotted time. Otherwise some negative return
860 * value describes the error. Of particular interest is -ETIME when the wait has
861 * failed to yield the desired result.
863 * Similar to brw_bo_wait_rendering except a timeout parameter allows
864 * the operation to give up after a certain amount of time. Another subtle
865 * difference is the internal locking semantics are different (this variant does
866 * not hold the lock for the duration of the wait). This makes the wait subject
867 * to a larger userspace race window.
869 * The implementation shall wait until the object is no longer actively
870 * referenced within a batch buffer at the time of the call. The wait will
871 * not guarantee that the buffer is re-issued via another thread, or an flinked
872 * handle. Userspace must make sure this race does not occur if such precision
875 * Note that some kernels have broken the inifite wait for negative values
876 * promise, upgrade to latest stable kernels if this is the case.
879 brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
)
881 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
882 struct drm_i915_gem_wait wait
;
886 wait
.bo_handle
= bo
->gem_handle
;
887 wait
.timeout_ns
= timeout_ns
;
888 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
896 brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
)
898 pthread_mutex_destroy(&bufmgr
->lock
);
900 /* Free any cached buffer objects we were going to reuse */
901 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
902 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
904 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
911 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
912 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
918 bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
921 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
922 struct drm_i915_gem_set_tiling set_tiling
;
925 if (bo
->global_name
== 0 &&
926 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
929 memset(&set_tiling
, 0, sizeof(set_tiling
));
931 /* set_tiling is slightly broken and overwrites the
932 * input on the error path, so we have to open code
935 set_tiling
.handle
= bo
->gem_handle
;
936 set_tiling
.tiling_mode
= tiling_mode
;
937 set_tiling
.stride
= stride
;
939 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
940 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
944 bo
->tiling_mode
= set_tiling
.tiling_mode
;
945 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
946 bo
->stride
= set_tiling
.stride
;
951 brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
952 uint32_t *swizzle_mode
)
954 *tiling_mode
= bo
->tiling_mode
;
955 *swizzle_mode
= bo
->swizzle_mode
;
960 brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
, int prime_fd
)
965 struct drm_i915_gem_get_tiling get_tiling
;
967 pthread_mutex_lock(&bufmgr
->lock
);
968 ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
970 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
972 pthread_mutex_unlock(&bufmgr
->lock
);
977 * See if the kernel has already returned this buffer to us. Just as
978 * for named buffers, we must not create two bo's pointing at the same
981 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
983 brw_bo_reference(bo
);
987 bo
= calloc(1, sizeof(*bo
));
991 p_atomic_set(&bo
->refcount
, 1);
993 /* Determine size of bo. The fd-to-handle ioctl really should
994 * return the size, but it doesn't. If we have kernel 3.12 or
995 * later, we can lseek on the prime fd to get the size. Older
996 * kernels will just fail, in which case we fall back to the
997 * provided (estimated or guess size). */
998 ret
= lseek(prime_fd
, 0, SEEK_END
);
1002 bo
->bufmgr
= bufmgr
;
1004 bo
->gem_handle
= handle
;
1005 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1008 bo
->reusable
= false;
1009 bo
->external
= true;
1011 memclear(get_tiling
);
1012 get_tiling
.handle
= bo
->gem_handle
;
1013 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1016 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1017 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1018 /* XXX stride is unknown */
1021 pthread_mutex_unlock(&bufmgr
->lock
);
1026 pthread_mutex_unlock(&bufmgr
->lock
);
1031 brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
)
1033 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1035 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1036 DRM_CLOEXEC
, prime_fd
) != 0)
1039 bo
->reusable
= false;
1040 bo
->external
= true;
1046 brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
)
1048 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1050 if (!bo
->global_name
) {
1051 struct drm_gem_flink flink
;
1054 flink
.handle
= bo
->gem_handle
;
1055 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1058 pthread_mutex_lock(&bufmgr
->lock
);
1059 if (!bo
->global_name
) {
1060 bo
->global_name
= flink
.name
;
1061 bo
->reusable
= false;
1062 bo
->external
= true;
1064 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1066 pthread_mutex_unlock(&bufmgr
->lock
);
1069 *name
= bo
->global_name
;
1074 * Enables unlimited caching of buffer objects for reuse.
1076 * This is potentially very memory expensive, as the cache at each bucket
1077 * size is only bounded by how many buffers of that size we've managed to have
1078 * in flight at once.
1081 brw_bufmgr_enable_reuse(struct brw_bufmgr
*bufmgr
)
1083 bufmgr
->bo_reuse
= true;
1087 add_bucket(struct brw_bufmgr
*bufmgr
, int size
)
1089 unsigned int i
= bufmgr
->num_buckets
;
1091 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1093 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1094 bufmgr
->cache_bucket
[i
].size
= size
;
1095 bufmgr
->num_buckets
++;
1099 init_cache_buckets(struct brw_bufmgr
*bufmgr
)
1101 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1103 /* OK, so power of two buckets was too wasteful of memory.
1104 * Give 3 other sizes between each power of two, to hopefully
1105 * cover things accurately enough. (The alternative is
1106 * probably to just go for exact matching of sizes, and assume
1107 * that for things like composited window resize the tiled
1108 * width/height alignment and rounding of sizes to pages will
1109 * get us useful cache hit rates anyway)
1111 add_bucket(bufmgr
, 4096);
1112 add_bucket(bufmgr
, 4096 * 2);
1113 add_bucket(bufmgr
, 4096 * 3);
1115 /* Initialize the linked lists for BO reuse cache. */
1116 for (size
= 4 * 4096; size
<= cache_max_size
; size
*= 2) {
1117 add_bucket(bufmgr
, size
);
1119 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1120 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1121 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1126 brw_create_hw_context(struct brw_bufmgr
*bufmgr
)
1128 struct drm_i915_gem_context_create create
;
1132 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1134 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1138 return create
.ctx_id
;
1142 brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
)
1144 struct drm_i915_gem_context_destroy d
= {.ctx_id
= ctx_id
};
1147 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1148 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1154 brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1156 struct drm_i915_reg_read reg_read
;
1160 reg_read
.offset
= offset
;
1162 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1164 *result
= reg_read
.val
;
1169 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1170 * and manage map buffer objections.
1172 * \param fd File descriptor of the opened DRM device.
1175 brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, int batch_size
)
1177 struct brw_bufmgr
*bufmgr
;
1179 bufmgr
= calloc(1, sizeof(*bufmgr
));
1183 /* Handles to buffer objects belong to the device fd and are not
1184 * reference counted by the kernel. If the same fd is used by
1185 * multiple parties (threads sharing the same screen bufmgr, or
1186 * even worse the same device fd passed to multiple libraries)
1187 * ownership of those handles is shared by those independent parties.
1189 * Don't do this! Ensure that each library/bufmgr has its own device
1190 * fd so that its namespace does not clash with another.
1194 if (pthread_mutex_init(&bufmgr
->lock
, NULL
) != 0) {
1199 bufmgr
->has_llc
= devinfo
->has_llc
;
1201 init_cache_buckets(bufmgr
);
1203 bufmgr
->name_table
=
1204 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1205 bufmgr
->handle_table
=
1206 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);