2 * Copyright © 2007 Red Hat Inc.
3 * Copyright © 2007-2017 Intel Corporation
4 * Copyright © 2006 VMware, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * Authors: Thomas Hellström <thellstrom@vmware.com>
29 * Keith Whitwell <keithw@vmware.com>
30 * Eric Anholt <eric@anholt.net>
31 * Dave Airlie <airlied@linux.ie>
39 #include <util/u_atomic.h>
47 #include <sys/ioctl.h>
49 #include <sys/types.h>
54 #define ETIME ETIMEDOUT
56 #include "common/gen_clflush.h"
57 #include "common/gen_debug.h"
58 #include "common/gen_device_info.h"
59 #include "libdrm_macros.h"
60 #include "main/macros.h"
61 #include "util/macros.h"
62 #include "util/hash_table.h"
63 #include "util/list.h"
64 #include "brw_bufmgr.h"
65 #include "brw_context.h"
78 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
79 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
80 * leaked. All because it does not call VG(cli_free) from its
81 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
82 * and allocation, we mark it available for use upon mmapping and remove
85 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
86 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
88 #define memclear(s) memset(&s, 0, sizeof(s))
90 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
93 atomic_add_unless(int *v
, int add
, int unless
)
97 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
102 struct bo_cache_bucket
{
103 struct list_head head
;
110 pthread_mutex_t lock
;
112 /** Array of lists of cached gem objects of power-of-two sizes */
113 struct bo_cache_bucket cache_bucket
[14 * 4];
117 struct hash_table
*name_table
;
118 struct hash_table
*handle_table
;
125 static int bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
128 static void bo_free(struct brw_bo
*bo
);
131 key_hash_uint(const void *key
)
133 return _mesa_hash_data(key
, 4);
137 key_uint_equal(const void *a
, const void *b
)
139 return *((unsigned *) a
) == *((unsigned *) b
);
142 static struct brw_bo
*
143 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
145 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
146 return entry
? (struct brw_bo
*) entry
->data
: NULL
;
150 bo_tile_size(struct brw_bufmgr
*bufmgr
, uint64_t size
, uint32_t tiling
)
152 if (tiling
== I915_TILING_NONE
)
155 /* 965+ just need multiples of page size for tiling */
156 return ALIGN(size
, 4096);
160 * Round a given pitch up to the minimum required for X tiling on a
161 * given chip. We use 512 as the minimum to allow for a later tiling
165 bo_tile_pitch(struct brw_bufmgr
*bufmgr
, uint32_t pitch
, uint32_t tiling
)
167 unsigned long tile_width
;
169 /* If untiled, then just align it so that we can do rendering
170 * to it with the 3D engine.
172 if (tiling
== I915_TILING_NONE
)
173 return ALIGN(pitch
, 64);
175 if (tiling
== I915_TILING_X
)
180 /* 965 is flexible */
181 return ALIGN(pitch
, tile_width
);
184 static struct bo_cache_bucket
*
185 bucket_for_size(struct brw_bufmgr
*bufmgr
, uint64_t size
)
189 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
190 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
191 if (bucket
->size
>= size
) {
200 brw_bo_busy(struct brw_bo
*bo
)
202 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
203 struct drm_i915_gem_busy busy
;
207 busy
.handle
= bo
->gem_handle
;
209 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
211 bo
->idle
= !busy
.busy
;
218 brw_bo_madvise(struct brw_bo
*bo
, int state
)
220 struct drm_i915_gem_madvise madv
;
223 madv
.handle
= bo
->gem_handle
;
226 drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
228 return madv
.retained
;
231 /* drop the oldest entries that have been purged by the kernel */
233 brw_bo_cache_purge_bucket(struct brw_bufmgr
*bufmgr
,
234 struct bo_cache_bucket
*bucket
)
236 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
237 if (brw_bo_madvise(bo
, I915_MADV_DONTNEED
))
245 static struct brw_bo
*
246 bo_alloc_internal(struct brw_bufmgr
*bufmgr
,
250 uint32_t tiling_mode
,
251 uint32_t stride
, uint64_t alignment
)
254 unsigned int page_size
= getpagesize();
256 struct bo_cache_bucket
*bucket
;
257 bool alloc_from_cache
;
259 bool for_render
= false;
262 if (flags
& BO_ALLOC_FOR_RENDER
)
265 if (flags
& BO_ALLOC_ZEROED
)
268 /* FOR_RENDER really means "I'm ok with a busy BO". This doesn't really
269 * jive with ZEROED as we have to wait for it to be idle before we can
270 * memset. Just disallow that combination.
272 assert(!(for_render
&& zeroed
));
274 /* Round the allocated size up to a power of two number of pages. */
275 bucket
= bucket_for_size(bufmgr
, size
);
277 /* If we don't have caching at this size, don't actually round the
280 if (bucket
== NULL
) {
282 if (bo_size
< page_size
)
285 bo_size
= bucket
->size
;
288 pthread_mutex_lock(&bufmgr
->lock
);
289 /* Get a buffer out of the cache if available */
291 alloc_from_cache
= false;
292 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
293 if (for_render
&& !zeroed
) {
294 /* Allocate new render-target BOs from the tail (MRU)
295 * of the list, as it will likely be hot in the GPU
296 * cache and in the aperture for us. If the caller
297 * asked us to zero the buffer, we don't want this
298 * because we are going to mmap it.
300 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.prev
, head
);
302 alloc_from_cache
= true;
303 bo
->align
= alignment
;
305 assert(alignment
== 0);
306 /* For non-render-target BOs (where we're probably
307 * going to map it first thing in order to fill it
308 * with data), check if the last BO in the cache is
309 * unbusy, and only reuse in that case. Otherwise,
310 * allocating a new buffer is probably faster than
311 * waiting for the GPU to finish.
313 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.next
, head
);
314 if (!brw_bo_busy(bo
)) {
315 alloc_from_cache
= true;
320 if (alloc_from_cache
) {
321 if (!brw_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
323 brw_bo_cache_purge_bucket(bufmgr
, bucket
);
327 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
333 void *map
= brw_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
338 memset(map
, 0, bo_size
);
343 if (!alloc_from_cache
) {
344 struct drm_i915_gem_create create
;
346 bo
= calloc(1, sizeof(*bo
));
354 create
.size
= bo_size
;
356 /* All new BOs we get from the kernel are zeroed, so we don't need to
357 * worry about that here.
359 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
365 bo
->gem_handle
= create
.handle
;
366 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
369 bo
->align
= alignment
;
371 bo
->tiling_mode
= I915_TILING_NONE
;
372 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
375 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
378 /* Calling set_domain() will allocate pages for the BO outside of the
379 * struct mutex lock in the kernel, which is more efficient than waiting
380 * to create them during the first execbuf that uses the BO.
382 struct drm_i915_gem_set_domain sd
= {
383 .handle
= bo
->gem_handle
,
384 .read_domains
= I915_GEM_DOMAIN_CPU
,
388 if (drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
393 p_atomic_set(&bo
->refcount
, 1);
395 bo
->cache_coherent
= bufmgr
->has_llc
;
398 pthread_mutex_unlock(&bufmgr
->lock
);
400 DBG("bo_create: buf %d (%s) %ldb\n", bo
->gem_handle
, bo
->name
, size
);
407 pthread_mutex_unlock(&bufmgr
->lock
);
412 brw_bo_alloc(struct brw_bufmgr
*bufmgr
,
413 const char *name
, uint64_t size
, uint64_t alignment
)
415 return bo_alloc_internal(bufmgr
, name
, size
, 0, I915_TILING_NONE
, 0, 0);
419 brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
, const char *name
,
420 uint64_t size
, uint32_t tiling_mode
, uint32_t pitch
,
423 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling_mode
, pitch
, 0);
427 brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
, const char *name
,
428 int x
, int y
, int cpp
, uint32_t tiling
,
429 uint32_t *pitch
, unsigned flags
)
433 unsigned long aligned_y
, height_alignment
;
435 /* If we're tiled, our allocations are in 8 or 32-row blocks,
436 * so failure to align our height means that we won't allocate
439 * If we're untiled, we still have to align to 2 rows high
440 * because the data port accesses 2x2 blocks even if the
441 * bottom row isn't to be rendered, so failure to align means
442 * we could walk off the end of the GTT and fault. This is
443 * documented on 965, and may be the case on older chipsets
444 * too so we try to be careful.
447 height_alignment
= 2;
449 if (tiling
== I915_TILING_X
)
450 height_alignment
= 8;
451 else if (tiling
== I915_TILING_Y
)
452 height_alignment
= 32;
453 aligned_y
= ALIGN(y
, height_alignment
);
456 stride
= bo_tile_pitch(bufmgr
, stride
, tiling
);
457 size
= stride
* aligned_y
;
458 size
= bo_tile_size(bufmgr
, size
, tiling
);
461 if (tiling
== I915_TILING_NONE
)
464 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling
, stride
, 0);
468 * Returns a brw_bo wrapping the given buffer object handle.
470 * This can be used when one application needs to pass a buffer object
474 brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
475 const char *name
, unsigned int handle
)
479 struct drm_gem_open open_arg
;
480 struct drm_i915_gem_get_tiling get_tiling
;
482 /* At the moment most applications only have a few named bo.
483 * For instance, in a DRI client only the render buffers passed
484 * between X and the client are named. And since X returns the
485 * alternating names for the front/back buffer a linear search
486 * provides a sufficiently fast match.
488 pthread_mutex_lock(&bufmgr
->lock
);
489 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
491 brw_bo_reference(bo
);
496 open_arg
.name
= handle
;
497 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
499 DBG("Couldn't reference %s handle 0x%08x: %s\n",
500 name
, handle
, strerror(errno
));
504 /* Now see if someone has used a prime handle to get this
505 * object from the kernel before by looking through the list
506 * again for a matching gem_handle
508 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
510 brw_bo_reference(bo
);
514 bo
= calloc(1, sizeof(*bo
));
518 p_atomic_set(&bo
->refcount
, 1);
520 bo
->size
= open_arg
.size
;
523 bo
->gem_handle
= open_arg
.handle
;
525 bo
->global_name
= handle
;
526 bo
->reusable
= false;
529 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
530 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
532 memclear(get_tiling
);
533 get_tiling
.handle
= bo
->gem_handle
;
534 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
538 bo
->tiling_mode
= get_tiling
.tiling_mode
;
539 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
540 /* XXX stride is unknown */
541 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
544 pthread_mutex_unlock(&bufmgr
->lock
);
549 pthread_mutex_unlock(&bufmgr
->lock
);
554 bo_free(struct brw_bo
*bo
)
556 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
557 struct drm_gem_close close
;
558 struct hash_entry
*entry
;
562 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
563 drm_munmap(bo
->map_cpu
, bo
->size
);
566 VG_NOACCESS(bo
->map_wc
, bo
->size
);
567 drm_munmap(bo
->map_wc
, bo
->size
);
570 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
571 drm_munmap(bo
->map_gtt
, bo
->size
);
574 if (bo
->global_name
) {
575 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
576 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
578 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
579 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
581 /* Close this object */
583 close
.handle
= bo
->gem_handle
;
584 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
586 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
587 bo
->gem_handle
, bo
->name
, strerror(errno
));
592 /** Frees all cached buffers significantly older than @time. */
594 cleanup_bo_cache(struct brw_bufmgr
*bufmgr
, time_t time
)
598 if (bufmgr
->time
== time
)
601 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
602 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
604 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
605 if (time
- bo
->free_time
<= 1)
618 bo_unreference_final(struct brw_bo
*bo
, time_t time
)
620 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
621 struct bo_cache_bucket
*bucket
;
623 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
625 bucket
= bucket_for_size(bufmgr
, bo
->size
);
626 /* Put the buffer into our internal cache for reuse if we can. */
627 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
628 brw_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
629 bo
->free_time
= time
;
634 list_addtail(&bo
->head
, &bucket
->head
);
641 brw_bo_unreference(struct brw_bo
*bo
)
646 assert(p_atomic_read(&bo
->refcount
) > 0);
648 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
649 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
650 struct timespec time
;
652 clock_gettime(CLOCK_MONOTONIC
, &time
);
654 pthread_mutex_lock(&bufmgr
->lock
);
656 if (p_atomic_dec_zero(&bo
->refcount
)) {
657 bo_unreference_final(bo
, time
.tv_sec
);
658 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
661 pthread_mutex_unlock(&bufmgr
->lock
);
666 bo_wait_with_stall_warning(struct brw_context
*brw
,
670 double elapsed
= unlikely(brw
&& brw
->perf_debug
) ? -get_time() : 0.0;
672 brw_bo_wait_rendering(bo
);
674 if (unlikely(brw
&& brw
->perf_debug
)) {
675 elapsed
+= get_time();
676 if (elapsed
> 1e-5) /* 0.01ms */
677 perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n",
678 action
, bo
->name
, elapsed
* 1000);
683 print_flags(unsigned flags
)
685 if (flags
& MAP_READ
)
687 if (flags
& MAP_WRITE
)
689 if (flags
& MAP_ASYNC
)
691 if (flags
& MAP_PERSISTENT
)
693 if (flags
& MAP_COHERENT
)
701 brw_bo_map_cpu(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
703 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
705 /* We disallow CPU maps for writing to non-coherent buffers, as the
706 * CPU map can become invalidated when a batch is flushed out, which
707 * can happen at unpredictable times. You should use WC maps instead.
709 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
712 struct drm_i915_gem_mmap mmap_arg
;
715 DBG("brw_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
718 mmap_arg
.handle
= bo
->gem_handle
;
719 mmap_arg
.size
= bo
->size
;
720 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
723 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
724 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
727 map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
728 VG_DEFINED(map
, bo
->size
);
730 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
731 VG_NOACCESS(map
, bo
->size
);
732 drm_munmap(map
, bo
->size
);
737 DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
741 if (!(flags
& MAP_ASYNC
)) {
742 bo_wait_with_stall_warning(brw
, bo
, "CPU mapping");
745 if (!bo
->cache_coherent
) {
746 /* If we're reusing an existing CPU mapping, the CPU caches may
747 * contain stale data from the last time we read from that mapping.
748 * (With the BO cache, it might even be data from a previous buffer!)
749 * Even if it's a brand new mapping, the kernel may have zeroed the
750 * buffer via CPU writes.
752 * We need to invalidate those cachelines so that we see the latest
753 * contents, and so long as we only read from the CPU mmap we do not
754 * need to write those cachelines back afterwards.
756 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
763 brw_bo_map_wc(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
765 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
767 if (!bufmgr
->has_mmap_wc
)
771 struct drm_i915_gem_mmap mmap_arg
;
774 DBG("brw_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
777 mmap_arg
.handle
= bo
->gem_handle
;
778 mmap_arg
.size
= bo
->size
;
779 mmap_arg
.flags
= I915_MMAP_WC
;
780 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
783 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
784 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
788 map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
789 VG_DEFINED(map
, bo
->size
);
791 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
792 VG_NOACCESS(map
, bo
->size
);
793 drm_munmap(map
, bo
->size
);
798 DBG("brw_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
801 if (!(flags
& MAP_ASYNC
)) {
802 bo_wait_with_stall_warning(brw
, bo
, "WC mapping");
809 * Perform an uncached mapping via the GTT.
811 * Write access through the GTT is not quite fully coherent. On low power
812 * systems especially, like modern Atoms, we can observe reads from RAM before
813 * the write via GTT has landed. A write memory barrier that flushes the Write
814 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
815 * read after the write as the GTT write suffers a small delay through the GTT
816 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
817 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
818 * flushes prior to execbuf submission. However, if we are not informing the
819 * kernel about our GTT writes, it will not flush before earlier access, such
820 * as when using the cmdparser. Similarly, we need to be careful if we should
821 * ever issue a CPU read immediately following a GTT write.
823 * Telling the kernel about write access also has one more important
824 * side-effect. Upon receiving notification about the write, it cancels any
825 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
826 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
827 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
828 * tracking is handled on the buffer exchange instead.
831 brw_bo_map_gtt(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
833 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
835 /* Get a mapping of the buffer if we haven't before. */
836 if (bo
->map_gtt
== NULL
) {
837 struct drm_i915_gem_mmap_gtt mmap_arg
;
840 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
843 mmap_arg
.handle
= bo
->gem_handle
;
845 /* Get the fake offset back... */
846 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
848 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
849 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
854 map
= drm_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
855 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
856 if (map
== MAP_FAILED
) {
857 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
858 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
862 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
863 * already intercept this mmap call. However, for consistency between
864 * all the mmap paths, we mark the pointer as defined now and mark it
865 * as inaccessible afterwards.
867 VG_DEFINED(map
, bo
->size
);
869 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
870 VG_NOACCESS(map
, bo
->size
);
871 drm_munmap(map
, bo
->size
);
876 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
879 if (!(flags
& MAP_ASYNC
)) {
880 bo_wait_with_stall_warning(brw
, bo
, "GTT mapping");
887 can_map_cpu(struct brw_bo
*bo
, unsigned flags
)
889 if (bo
->cache_coherent
)
892 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
893 * across batch flushes where the kernel will change cache domains of the
894 * bo, invalidating continued access to the CPU mmap on non-LLC device.
896 * Similarly, ASYNC typically means that the buffer will be accessed via
897 * both the CPU and the GPU simultaneously. Batches may be executed that
898 * use the BO even while it is mapped. While OpenGL technically disallows
899 * most drawing while non-persistent mappings are active, we may still use
900 * the GPU for blits or other operations, causing batches to happen at
901 * inconvenient times.
903 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
906 return !(flags
& MAP_WRITE
);
910 brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
912 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
913 return brw_bo_map_gtt(brw
, bo
, flags
);
917 if (can_map_cpu(bo
, flags
))
918 map
= brw_bo_map_cpu(brw
, bo
, flags
);
920 map
= brw_bo_map_wc(brw
, bo
, flags
);
922 /* Allow the attempt to fail by falling back to the GTT where necessary.
924 * Not every buffer can be mmaped directly using the CPU (or WC), for
925 * example buffers that wrap stolen memory or are imported from other
926 * devices. For those, we have little choice but to use a GTT mmapping.
927 * However, if we use a slow GTT mmapping for reads where we expected fast
928 * access, that order of magnitude difference in throughput will be clearly
929 * expressed by angry users.
931 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
933 if (!map
&& !(flags
& MAP_RAW
)) {
934 perf_debug("Fallback GTT mapping for %s with access flags %x\n",
936 map
= brw_bo_map_gtt(brw
, bo
, flags
);
943 brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
944 uint64_t size
, const void *data
)
946 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
947 struct drm_i915_gem_pwrite pwrite
;
951 pwrite
.handle
= bo
->gem_handle
;
952 pwrite
.offset
= offset
;
954 pwrite
.data_ptr
= (uint64_t) (uintptr_t) data
;
955 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
958 DBG("%s:%d: Error writing data to buffer %d: "
959 "(%"PRIu64
" %"PRIu64
") %s .\n",
960 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
966 /** Waits for all GPU rendering with the object to have completed. */
968 brw_bo_wait_rendering(struct brw_bo
*bo
)
970 /* We require a kernel recent enough for WAIT_IOCTL support.
971 * See intel_init_bufmgr()
977 * Waits on a BO for the given amount of time.
979 * @bo: buffer object to wait for
980 * @timeout_ns: amount of time to wait in nanoseconds.
981 * If value is less than 0, an infinite wait will occur.
983 * Returns 0 if the wait was successful ie. the last batch referencing the
984 * object has completed within the allotted time. Otherwise some negative return
985 * value describes the error. Of particular interest is -ETIME when the wait has
986 * failed to yield the desired result.
988 * Similar to brw_bo_wait_rendering except a timeout parameter allows
989 * the operation to give up after a certain amount of time. Another subtle
990 * difference is the internal locking semantics are different (this variant does
991 * not hold the lock for the duration of the wait). This makes the wait subject
992 * to a larger userspace race window.
994 * The implementation shall wait until the object is no longer actively
995 * referenced within a batch buffer at the time of the call. The wait will
996 * not guarantee that the buffer is re-issued via another thread, or an flinked
997 * handle. Userspace must make sure this race does not occur if such precision
1000 * Note that some kernels have broken the inifite wait for negative values
1001 * promise, upgrade to latest stable kernels if this is the case.
1004 brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
)
1006 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1007 struct drm_i915_gem_wait wait
;
1010 /* If we know it's idle, don't bother with the kernel round trip */
1011 if (bo
->idle
&& !bo
->external
)
1015 wait
.bo_handle
= bo
->gem_handle
;
1016 wait
.timeout_ns
= timeout_ns
;
1017 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1025 brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
)
1027 pthread_mutex_destroy(&bufmgr
->lock
);
1029 /* Free any cached buffer objects we were going to reuse */
1030 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1031 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1033 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
1034 list_del(&bo
->head
);
1040 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1041 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1047 bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
1050 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1051 struct drm_i915_gem_set_tiling set_tiling
;
1054 if (bo
->global_name
== 0 &&
1055 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1058 memset(&set_tiling
, 0, sizeof(set_tiling
));
1060 /* set_tiling is slightly broken and overwrites the
1061 * input on the error path, so we have to open code
1064 set_tiling
.handle
= bo
->gem_handle
;
1065 set_tiling
.tiling_mode
= tiling_mode
;
1066 set_tiling
.stride
= stride
;
1068 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1069 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1073 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1074 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1075 bo
->stride
= set_tiling
.stride
;
1080 brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
1081 uint32_t *swizzle_mode
)
1083 *tiling_mode
= bo
->tiling_mode
;
1084 *swizzle_mode
= bo
->swizzle_mode
;
1089 brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
, int prime_fd
)
1094 struct drm_i915_gem_get_tiling get_tiling
;
1096 pthread_mutex_lock(&bufmgr
->lock
);
1097 ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1099 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
1101 pthread_mutex_unlock(&bufmgr
->lock
);
1106 * See if the kernel has already returned this buffer to us. Just as
1107 * for named buffers, we must not create two bo's pointing at the same
1110 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1112 brw_bo_reference(bo
);
1116 bo
= calloc(1, sizeof(*bo
));
1120 p_atomic_set(&bo
->refcount
, 1);
1122 /* Determine size of bo. The fd-to-handle ioctl really should
1123 * return the size, but it doesn't. If we have kernel 3.12 or
1124 * later, we can lseek on the prime fd to get the size. Older
1125 * kernels will just fail, in which case we fall back to the
1126 * provided (estimated or guess size). */
1127 ret
= lseek(prime_fd
, 0, SEEK_END
);
1131 bo
->bufmgr
= bufmgr
;
1133 bo
->gem_handle
= handle
;
1134 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1137 bo
->reusable
= false;
1138 bo
->external
= true;
1140 memclear(get_tiling
);
1141 get_tiling
.handle
= bo
->gem_handle
;
1142 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1145 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1146 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1147 /* XXX stride is unknown */
1150 pthread_mutex_unlock(&bufmgr
->lock
);
1155 pthread_mutex_unlock(&bufmgr
->lock
);
1160 brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
)
1162 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1164 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1165 DRM_CLOEXEC
, prime_fd
) != 0)
1168 bo
->reusable
= false;
1169 bo
->external
= true;
1175 brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
)
1177 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1179 if (!bo
->global_name
) {
1180 struct drm_gem_flink flink
;
1183 flink
.handle
= bo
->gem_handle
;
1184 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1187 pthread_mutex_lock(&bufmgr
->lock
);
1188 if (!bo
->global_name
) {
1189 bo
->global_name
= flink
.name
;
1190 bo
->reusable
= false;
1191 bo
->external
= true;
1193 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1195 pthread_mutex_unlock(&bufmgr
->lock
);
1198 *name
= bo
->global_name
;
1203 * Enables unlimited caching of buffer objects for reuse.
1205 * This is potentially very memory expensive, as the cache at each bucket
1206 * size is only bounded by how many buffers of that size we've managed to have
1207 * in flight at once.
1210 brw_bufmgr_enable_reuse(struct brw_bufmgr
*bufmgr
)
1212 bufmgr
->bo_reuse
= true;
1216 add_bucket(struct brw_bufmgr
*bufmgr
, int size
)
1218 unsigned int i
= bufmgr
->num_buckets
;
1220 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1222 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1223 bufmgr
->cache_bucket
[i
].size
= size
;
1224 bufmgr
->num_buckets
++;
1228 init_cache_buckets(struct brw_bufmgr
*bufmgr
)
1230 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1232 /* OK, so power of two buckets was too wasteful of memory.
1233 * Give 3 other sizes between each power of two, to hopefully
1234 * cover things accurately enough. (The alternative is
1235 * probably to just go for exact matching of sizes, and assume
1236 * that for things like composited window resize the tiled
1237 * width/height alignment and rounding of sizes to pages will
1238 * get us useful cache hit rates anyway)
1240 add_bucket(bufmgr
, 4096);
1241 add_bucket(bufmgr
, 4096 * 2);
1242 add_bucket(bufmgr
, 4096 * 3);
1244 /* Initialize the linked lists for BO reuse cache. */
1245 for (size
= 4 * 4096; size
<= cache_max_size
; size
*= 2) {
1246 add_bucket(bufmgr
, size
);
1248 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1249 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1250 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1255 brw_create_hw_context(struct brw_bufmgr
*bufmgr
)
1257 struct drm_i915_gem_context_create create
;
1261 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1263 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1267 return create
.ctx_id
;
1271 brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
)
1273 struct drm_i915_gem_context_destroy d
= {.ctx_id
= ctx_id
};
1276 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1277 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1283 brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1285 struct drm_i915_reg_read reg_read
;
1289 reg_read
.offset
= offset
;
1291 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1293 *result
= reg_read
.val
;
1298 gem_param(int fd
, int name
)
1300 drm_i915_getparam_t gp
;
1301 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1303 memset(&gp
, 0, sizeof(gp
));
1306 if (drmIoctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1313 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1314 * and manage map buffer objections.
1316 * \param fd File descriptor of the opened DRM device.
1319 brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, int batch_size
)
1321 struct brw_bufmgr
*bufmgr
;
1323 bufmgr
= calloc(1, sizeof(*bufmgr
));
1327 /* Handles to buffer objects belong to the device fd and are not
1328 * reference counted by the kernel. If the same fd is used by
1329 * multiple parties (threads sharing the same screen bufmgr, or
1330 * even worse the same device fd passed to multiple libraries)
1331 * ownership of those handles is shared by those independent parties.
1333 * Don't do this! Ensure that each library/bufmgr has its own device
1334 * fd so that its namespace does not clash with another.
1338 if (pthread_mutex_init(&bufmgr
->lock
, NULL
) != 0) {
1343 bufmgr
->has_llc
= devinfo
->has_llc
;
1344 bufmgr
->has_mmap_wc
= gem_param(fd
, I915_PARAM_MMAP_VERSION
) > 0;
1346 init_cache_buckets(bufmgr
);
1348 bufmgr
->name_table
=
1349 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1350 bufmgr
->handle_table
=
1351 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);