i965/bufmgr: Remove some reuse functions
[mesa.git] / src / mesa / drivers / dri / i965 / brw_bufmgr.c
1 /**************************************************************************
2 *
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
26 * of the Software.
27 *
28 *
29 **************************************************************************/
30 /*
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
35 */
36
37 #ifdef HAVE_CONFIG_H
38 #include "config.h"
39 #endif
40
41 #include <xf86drm.h>
42 #include <util/u_atomic.h>
43 #include <fcntl.h>
44 #include <stdio.h>
45 #include <stdlib.h>
46 #include <string.h>
47 #include <unistd.h>
48 #include <assert.h>
49 #include <pthread.h>
50 #include <sys/ioctl.h>
51 #include <sys/stat.h>
52 #include <sys/types.h>
53 #include <stdbool.h>
54
55 #include "errno.h"
56 #ifndef ETIME
57 #define ETIME ETIMEDOUT
58 #endif
59 #include "common/gen_debug.h"
60 #include "common/gen_device_info.h"
61 #include "libdrm_macros.h"
62 #include "main/macros.h"
63 #include "util/macros.h"
64 #include "util/hash_table.h"
65 #include "util/list.h"
66 #include "brw_bufmgr.h"
67 #include "string.h"
68
69 #include "i915_drm.h"
70
71 #ifdef HAVE_VALGRIND
72 #include <valgrind.h>
73 #include <memcheck.h>
74 #define VG(x) x
75 #else
76 #define VG(x)
77 #endif
78
79 #define memclear(s) memset(&s, 0, sizeof(s))
80
81 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
82
83 static inline int
84 atomic_add_unless(int *v, int add, int unless)
85 {
86 int c, old;
87 c = p_atomic_read(v);
88 while (c != unless && (old = p_atomic_cmpxchg(v, c, c + add)) != c)
89 c = old;
90 return c == unless;
91 }
92
93 struct bo_cache_bucket {
94 struct list_head head;
95 unsigned long size;
96 };
97
98 struct brw_bufmgr {
99 int fd;
100
101 pthread_mutex_t lock;
102
103 /** Array of lists of cached gem objects of power-of-two sizes */
104 struct bo_cache_bucket cache_bucket[14 * 4];
105 int num_buckets;
106 time_t time;
107
108 struct hash_table *name_table;
109 struct hash_table *handle_table;
110
111 struct list_head vma_cache;
112 int vma_count, vma_open, vma_max;
113
114 unsigned int has_llc:1;
115 unsigned int bo_reuse:1;
116 };
117
118 static int bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode,
119 uint32_t stride);
120
121 static void bo_free(struct brw_bo *bo);
122
123 static uint32_t
124 key_hash_uint(const void *key)
125 {
126 return _mesa_hash_data(key, 4);
127 }
128
129 static bool
130 key_uint_equal(const void *a, const void *b)
131 {
132 return *((unsigned *) a) == *((unsigned *) b);
133 }
134
135 static struct brw_bo *
136 hash_find_bo(struct hash_table *ht, unsigned int key)
137 {
138 struct hash_entry *entry = _mesa_hash_table_search(ht, &key);
139 return entry ? (struct brw_bo *) entry->data : NULL;
140 }
141
142 static unsigned long
143 bo_tile_size(struct brw_bufmgr *bufmgr, unsigned long size,
144 uint32_t *tiling_mode)
145 {
146 if (*tiling_mode == I915_TILING_NONE)
147 return size;
148
149 /* 965+ just need multiples of page size for tiling */
150 return ALIGN(size, 4096);
151 }
152
153 /*
154 * Round a given pitch up to the minimum required for X tiling on a
155 * given chip. We use 512 as the minimum to allow for a later tiling
156 * change.
157 */
158 static unsigned long
159 bo_tile_pitch(struct brw_bufmgr *bufmgr,
160 unsigned long pitch, uint32_t *tiling_mode)
161 {
162 unsigned long tile_width;
163
164 /* If untiled, then just align it so that we can do rendering
165 * to it with the 3D engine.
166 */
167 if (*tiling_mode == I915_TILING_NONE)
168 return ALIGN(pitch, 64);
169
170 if (*tiling_mode == I915_TILING_X)
171 tile_width = 512;
172 else
173 tile_width = 128;
174
175 /* 965 is flexible */
176 return ALIGN(pitch, tile_width);
177 }
178
179 static struct bo_cache_bucket *
180 bucket_for_size(struct brw_bufmgr *bufmgr, unsigned long size)
181 {
182 int i;
183
184 for (i = 0; i < bufmgr->num_buckets; i++) {
185 struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i];
186 if (bucket->size >= size) {
187 return bucket;
188 }
189 }
190
191 return NULL;
192 }
193
194 inline void
195 brw_bo_reference(struct brw_bo *bo)
196 {
197 p_atomic_inc(&bo->refcount);
198 }
199
200 int
201 brw_bo_busy(struct brw_bo *bo)
202 {
203 struct brw_bufmgr *bufmgr = bo->bufmgr;
204 struct drm_i915_gem_busy busy;
205 int ret;
206
207 memclear(busy);
208 busy.handle = bo->gem_handle;
209
210 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
211 if (ret == 0) {
212 bo->idle = !busy.busy;
213 return busy.busy;
214 } else {
215 return false;
216 }
217 return (ret == 0 && busy.busy);
218 }
219
220 int
221 brw_bo_madvise(struct brw_bo *bo, int state)
222 {
223 struct drm_i915_gem_madvise madv;
224
225 memclear(madv);
226 madv.handle = bo->gem_handle;
227 madv.madv = state;
228 madv.retained = 1;
229 drmIoctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
230
231 return madv.retained;
232 }
233
234 /* drop the oldest entries that have been purged by the kernel */
235 static void
236 brw_bo_cache_purge_bucket(struct brw_bufmgr *bufmgr,
237 struct bo_cache_bucket *bucket)
238 {
239 list_for_each_entry_safe(struct brw_bo, bo, &bucket->head, head) {
240 if (brw_bo_madvise(bo, I915_MADV_DONTNEED))
241 break;
242
243 list_del(&bo->head);
244 bo_free(bo);
245 }
246 }
247
248 static struct brw_bo *
249 bo_alloc_internal(struct brw_bufmgr *bufmgr,
250 const char *name,
251 unsigned long size,
252 unsigned long flags,
253 uint32_t tiling_mode,
254 unsigned long stride, unsigned int alignment)
255 {
256 struct brw_bo *bo;
257 unsigned int page_size = getpagesize();
258 int ret;
259 struct bo_cache_bucket *bucket;
260 bool alloc_from_cache;
261 unsigned long bo_size;
262 bool for_render = false;
263
264 if (flags & BO_ALLOC_FOR_RENDER)
265 for_render = true;
266
267 /* Round the allocated size up to a power of two number of pages. */
268 bucket = bucket_for_size(bufmgr, size);
269
270 /* If we don't have caching at this size, don't actually round the
271 * allocation up.
272 */
273 if (bucket == NULL) {
274 bo_size = size;
275 if (bo_size < page_size)
276 bo_size = page_size;
277 } else {
278 bo_size = bucket->size;
279 }
280
281 pthread_mutex_lock(&bufmgr->lock);
282 /* Get a buffer out of the cache if available */
283 retry:
284 alloc_from_cache = false;
285 if (bucket != NULL && !list_empty(&bucket->head)) {
286 if (for_render) {
287 /* Allocate new render-target BOs from the tail (MRU)
288 * of the list, as it will likely be hot in the GPU
289 * cache and in the aperture for us.
290 */
291 bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
292 list_del(&bo->head);
293 alloc_from_cache = true;
294 bo->align = alignment;
295 } else {
296 assert(alignment == 0);
297 /* For non-render-target BOs (where we're probably
298 * going to map it first thing in order to fill it
299 * with data), check if the last BO in the cache is
300 * unbusy, and only reuse in that case. Otherwise,
301 * allocating a new buffer is probably faster than
302 * waiting for the GPU to finish.
303 */
304 bo = LIST_ENTRY(struct brw_bo, bucket->head.next, head);
305 if (!brw_bo_busy(bo)) {
306 alloc_from_cache = true;
307 list_del(&bo->head);
308 }
309 }
310
311 if (alloc_from_cache) {
312 if (!brw_bo_madvise(bo, I915_MADV_WILLNEED)) {
313 bo_free(bo);
314 brw_bo_cache_purge_bucket(bufmgr, bucket);
315 goto retry;
316 }
317
318 if (bo_set_tiling_internal(bo, tiling_mode, stride)) {
319 bo_free(bo);
320 goto retry;
321 }
322 }
323 }
324
325 if (!alloc_from_cache) {
326 struct drm_i915_gem_create create;
327
328 bo = calloc(1, sizeof(*bo));
329 if (!bo)
330 goto err;
331
332 /* bo_free calls list_del() for an uninitialized
333 list (vma_list), so better set the list head here */
334 list_inithead(&bo->vma_list);
335
336 bo->size = bo_size;
337
338 memclear(create);
339 create.size = bo_size;
340
341 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
342 if (ret != 0) {
343 free(bo);
344 goto err;
345 }
346
347 bo->gem_handle = create.handle;
348 _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
349
350 bo->bufmgr = bufmgr;
351 bo->align = alignment;
352
353 bo->tiling_mode = I915_TILING_NONE;
354 bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
355 bo->stride = 0;
356
357 if (bo_set_tiling_internal(bo, tiling_mode, stride))
358 goto err_free;
359 }
360
361 bo->name = name;
362 p_atomic_set(&bo->refcount, 1);
363 bo->reusable = true;
364
365 pthread_mutex_unlock(&bufmgr->lock);
366
367 DBG("bo_create: buf %d (%s) %ldb\n", bo->gem_handle, bo->name, size);
368
369 return bo;
370
371 err_free:
372 bo_free(bo);
373 err:
374 pthread_mutex_unlock(&bufmgr->lock);
375 return NULL;
376 }
377
378 struct brw_bo *
379 brw_bo_alloc(struct brw_bufmgr *bufmgr,
380 const char *name, unsigned long size, unsigned int alignment)
381 {
382 return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0, 0);
383 }
384
385 struct brw_bo *
386 brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char *name,
387 int x, int y, int cpp, uint32_t *tiling_mode,
388 unsigned long *pitch, unsigned long flags)
389 {
390 unsigned long size, stride;
391 uint32_t tiling;
392
393 do {
394 unsigned long aligned_y, height_alignment;
395
396 tiling = *tiling_mode;
397
398 /* If we're tiled, our allocations are in 8 or 32-row blocks,
399 * so failure to align our height means that we won't allocate
400 * enough pages.
401 *
402 * If we're untiled, we still have to align to 2 rows high
403 * because the data port accesses 2x2 blocks even if the
404 * bottom row isn't to be rendered, so failure to align means
405 * we could walk off the end of the GTT and fault. This is
406 * documented on 965, and may be the case on older chipsets
407 * too so we try to be careful.
408 */
409 aligned_y = y;
410 height_alignment = 2;
411
412 if (tiling == I915_TILING_X)
413 height_alignment = 8;
414 else if (tiling == I915_TILING_Y)
415 height_alignment = 32;
416 aligned_y = ALIGN(y, height_alignment);
417
418 stride = x * cpp;
419 stride = bo_tile_pitch(bufmgr, stride, tiling_mode);
420 size = stride * aligned_y;
421 size = bo_tile_size(bufmgr, size, tiling_mode);
422 } while (*tiling_mode != tiling);
423 *pitch = stride;
424
425 if (tiling == I915_TILING_NONE)
426 stride = 0;
427
428 return bo_alloc_internal(bufmgr, name, size, flags, tiling, stride, 0);
429 }
430
431 /**
432 * Returns a brw_bo wrapping the given buffer object handle.
433 *
434 * This can be used when one application needs to pass a buffer object
435 * to another.
436 */
437 struct brw_bo *
438 brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
439 const char *name, unsigned int handle)
440 {
441 struct brw_bo *bo;
442 int ret;
443 struct drm_gem_open open_arg;
444 struct drm_i915_gem_get_tiling get_tiling;
445
446 /* At the moment most applications only have a few named bo.
447 * For instance, in a DRI client only the render buffers passed
448 * between X and the client are named. And since X returns the
449 * alternating names for the front/back buffer a linear search
450 * provides a sufficiently fast match.
451 */
452 pthread_mutex_lock(&bufmgr->lock);
453 bo = hash_find_bo(bufmgr->name_table, handle);
454 if (bo) {
455 brw_bo_reference(bo);
456 goto out;
457 }
458
459 memclear(open_arg);
460 open_arg.name = handle;
461 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
462 if (ret != 0) {
463 DBG("Couldn't reference %s handle 0x%08x: %s\n",
464 name, handle, strerror(errno));
465 bo = NULL;
466 goto out;
467 }
468 /* Now see if someone has used a prime handle to get this
469 * object from the kernel before by looking through the list
470 * again for a matching gem_handle
471 */
472 bo = hash_find_bo(bufmgr->handle_table, open_arg.handle);
473 if (bo) {
474 brw_bo_reference(bo);
475 goto out;
476 }
477
478 bo = calloc(1, sizeof(*bo));
479 if (!bo)
480 goto out;
481
482 p_atomic_set(&bo->refcount, 1);
483 list_inithead(&bo->vma_list);
484
485 bo->size = open_arg.size;
486 bo->offset64 = 0;
487 bo->virtual = NULL;
488 bo->bufmgr = bufmgr;
489 bo->gem_handle = open_arg.handle;
490 bo->name = name;
491 bo->global_name = handle;
492 bo->reusable = false;
493
494 _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
495 _mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo);
496
497 memclear(get_tiling);
498 get_tiling.handle = bo->gem_handle;
499 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
500 if (ret != 0)
501 goto err_unref;
502
503 bo->tiling_mode = get_tiling.tiling_mode;
504 bo->swizzle_mode = get_tiling.swizzle_mode;
505 /* XXX stride is unknown */
506 DBG("bo_create_from_handle: %d (%s)\n", handle, bo->name);
507
508 out:
509 pthread_mutex_unlock(&bufmgr->lock);
510 return bo;
511
512 err_unref:
513 bo_free(bo);
514 pthread_mutex_unlock(&bufmgr->lock);
515 return NULL;
516 }
517
518 static void
519 bo_free(struct brw_bo *bo)
520 {
521 struct brw_bufmgr *bufmgr = bo->bufmgr;
522 struct drm_gem_close close;
523 struct hash_entry *entry;
524 int ret;
525
526 list_del(&bo->vma_list);
527 if (bo->mem_virtual) {
528 VG(VALGRIND_FREELIKE_BLOCK(bo->mem_virtual, 0));
529 drm_munmap(bo->mem_virtual, bo->size);
530 bufmgr->vma_count--;
531 }
532 if (bo->wc_virtual) {
533 VG(VALGRIND_FREELIKE_BLOCK(bo->wc_virtual, 0));
534 drm_munmap(bo->wc_virtual, bo->size);
535 bufmgr->vma_count--;
536 }
537 if (bo->gtt_virtual) {
538 drm_munmap(bo->gtt_virtual, bo->size);
539 bufmgr->vma_count--;
540 }
541
542 if (bo->global_name) {
543 entry = _mesa_hash_table_search(bufmgr->name_table, &bo->global_name);
544 _mesa_hash_table_remove(bufmgr->name_table, entry);
545 }
546 entry = _mesa_hash_table_search(bufmgr->handle_table, &bo->gem_handle);
547 _mesa_hash_table_remove(bufmgr->handle_table, entry);
548
549 /* Close this object */
550 memclear(close);
551 close.handle = bo->gem_handle;
552 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_GEM_CLOSE, &close);
553 if (ret != 0) {
554 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
555 bo->gem_handle, bo->name, strerror(errno));
556 }
557 free(bo);
558 }
559
560 static void
561 bo_mark_mmaps_incoherent(struct brw_bo *bo)
562 {
563 #if HAVE_VALGRIND
564 if (bo->mem_virtual)
565 VALGRIND_MAKE_MEM_NOACCESS(bo->mem_virtual, bo->size);
566
567 if (bo->wc_virtual)
568 VALGRIND_MAKE_MEM_NOACCESS(bo->wc_virtual, bo->size);
569
570 if (bo->gtt_virtual)
571 VALGRIND_MAKE_MEM_NOACCESS(bo->gtt_virtual, bo->size);
572 #endif
573 }
574
575 /** Frees all cached buffers significantly older than @time. */
576 static void
577 cleanup_bo_cache(struct brw_bufmgr *bufmgr, time_t time)
578 {
579 int i;
580
581 if (bufmgr->time == time)
582 return;
583
584 for (i = 0; i < bufmgr->num_buckets; i++) {
585 struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i];
586
587 list_for_each_entry_safe(struct brw_bo, bo, &bucket->head, head) {
588 if (time - bo->free_time <= 1)
589 break;
590
591 list_del(&bo->head);
592
593 bo_free(bo);
594 }
595 }
596
597 bufmgr->time = time;
598 }
599
600 static void
601 bo_purge_vma_cache(struct brw_bufmgr *bufmgr)
602 {
603 int limit;
604
605 DBG("%s: cached=%d, open=%d, limit=%d\n", __FUNCTION__,
606 bufmgr->vma_count, bufmgr->vma_open, bufmgr->vma_max);
607
608 if (bufmgr->vma_max < 0)
609 return;
610
611 /* We may need to evict a few entries in order to create new mmaps */
612 limit = bufmgr->vma_max - 2 * bufmgr->vma_open;
613 if (limit < 0)
614 limit = 0;
615
616 while (bufmgr->vma_count > limit) {
617 struct brw_bo *bo;
618
619 bo = LIST_ENTRY(struct brw_bo, bufmgr->vma_cache.next, vma_list);
620 assert(bo->map_count == 0);
621 list_delinit(&bo->vma_list);
622
623 if (bo->mem_virtual) {
624 drm_munmap(bo->mem_virtual, bo->size);
625 bo->mem_virtual = NULL;
626 bufmgr->vma_count--;
627 }
628 if (bo->wc_virtual) {
629 drm_munmap(bo->wc_virtual, bo->size);
630 bo->wc_virtual = NULL;
631 bufmgr->vma_count--;
632 }
633 if (bo->gtt_virtual) {
634 drm_munmap(bo->gtt_virtual, bo->size);
635 bo->gtt_virtual = NULL;
636 bufmgr->vma_count--;
637 }
638 }
639 }
640
641 static void
642 bo_close_vma(struct brw_bufmgr *bufmgr, struct brw_bo *bo)
643 {
644 bufmgr->vma_open--;
645 list_addtail(&bo->vma_list, &bufmgr->vma_cache);
646 if (bo->mem_virtual)
647 bufmgr->vma_count++;
648 if (bo->wc_virtual)
649 bufmgr->vma_count++;
650 if (bo->gtt_virtual)
651 bufmgr->vma_count++;
652 bo_purge_vma_cache(bufmgr);
653 }
654
655 static void
656 bo_open_vma(struct brw_bufmgr *bufmgr, struct brw_bo *bo)
657 {
658 bufmgr->vma_open++;
659 list_del(&bo->vma_list);
660 if (bo->mem_virtual)
661 bufmgr->vma_count--;
662 if (bo->wc_virtual)
663 bufmgr->vma_count--;
664 if (bo->gtt_virtual)
665 bufmgr->vma_count--;
666 bo_purge_vma_cache(bufmgr);
667 }
668
669 static void
670 bo_unreference_final(struct brw_bo *bo, time_t time)
671 {
672 struct brw_bufmgr *bufmgr = bo->bufmgr;
673 struct bo_cache_bucket *bucket;
674
675 DBG("bo_unreference final: %d (%s)\n", bo->gem_handle, bo->name);
676
677 /* Clear any left-over mappings */
678 if (bo->map_count) {
679 DBG("bo freed with non-zero map-count %d\n", bo->map_count);
680 bo->map_count = 0;
681 bo_close_vma(bufmgr, bo);
682 bo_mark_mmaps_incoherent(bo);
683 }
684
685 bucket = bucket_for_size(bufmgr, bo->size);
686 /* Put the buffer into our internal cache for reuse if we can. */
687 if (bufmgr->bo_reuse && bo->reusable && bucket != NULL &&
688 brw_bo_madvise(bo, I915_MADV_DONTNEED)) {
689 bo->free_time = time;
690
691 bo->name = NULL;
692
693 list_addtail(&bo->head, &bucket->head);
694 } else {
695 bo_free(bo);
696 }
697 }
698
699 void
700 brw_bo_unreference(struct brw_bo *bo)
701 {
702 if (bo == NULL)
703 return;
704
705 assert(p_atomic_read(&bo->refcount) > 0);
706
707 if (atomic_add_unless(&bo->refcount, -1, 1)) {
708 struct brw_bufmgr *bufmgr = bo->bufmgr;
709 struct timespec time;
710
711 clock_gettime(CLOCK_MONOTONIC, &time);
712
713 pthread_mutex_lock(&bufmgr->lock);
714
715 if (p_atomic_dec_zero(&bo->refcount)) {
716 bo_unreference_final(bo, time.tv_sec);
717 cleanup_bo_cache(bufmgr, time.tv_sec);
718 }
719
720 pthread_mutex_unlock(&bufmgr->lock);
721 }
722 }
723
724 int
725 brw_bo_map(struct brw_bo *bo, int write_enable)
726 {
727 struct brw_bufmgr *bufmgr = bo->bufmgr;
728 struct drm_i915_gem_set_domain set_domain;
729 int ret;
730
731 pthread_mutex_lock(&bufmgr->lock);
732
733 if (bo->map_count++ == 0)
734 bo_open_vma(bufmgr, bo);
735
736 if (!bo->mem_virtual) {
737 struct drm_i915_gem_mmap mmap_arg;
738
739 DBG("bo_map: %d (%s), map_count=%d\n",
740 bo->gem_handle, bo->name, bo->map_count);
741
742 memclear(mmap_arg);
743 mmap_arg.handle = bo->gem_handle;
744 mmap_arg.size = bo->size;
745 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
746 if (ret != 0) {
747 ret = -errno;
748 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
749 __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
750 if (--bo->map_count == 0)
751 bo_close_vma(bufmgr, bo);
752 pthread_mutex_unlock(&bufmgr->lock);
753 return ret;
754 }
755 VG(VALGRIND_MALLOCLIKE_BLOCK(mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
756 bo->mem_virtual = (void *) (uintptr_t) mmap_arg.addr_ptr;
757 }
758 DBG("bo_map: %d (%s) -> %p\n", bo->gem_handle, bo->name, bo->mem_virtual);
759 bo->virtual = bo->mem_virtual;
760
761 memclear(set_domain);
762 set_domain.handle = bo->gem_handle;
763 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
764 if (write_enable)
765 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
766 else
767 set_domain.write_domain = 0;
768 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
769 if (ret != 0) {
770 DBG("%s:%d: Error setting to CPU domain %d: %s\n",
771 __FILE__, __LINE__, bo->gem_handle, strerror(errno));
772 }
773
774 bo_mark_mmaps_incoherent(bo);
775 VG(VALGRIND_MAKE_MEM_DEFINED(bo->mem_virtual, bo->size));
776 pthread_mutex_unlock(&bufmgr->lock);
777
778 return 0;
779 }
780
781 static int
782 map_gtt(struct brw_bo *bo)
783 {
784 struct brw_bufmgr *bufmgr = bo->bufmgr;
785 int ret;
786
787 if (bo->map_count++ == 0)
788 bo_open_vma(bufmgr, bo);
789
790 /* Get a mapping of the buffer if we haven't before. */
791 if (bo->gtt_virtual == NULL) {
792 struct drm_i915_gem_mmap_gtt mmap_arg;
793
794 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
795 bo->gem_handle, bo->name, bo->map_count);
796
797 memclear(mmap_arg);
798 mmap_arg.handle = bo->gem_handle;
799
800 /* Get the fake offset back... */
801 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
802 if (ret != 0) {
803 ret = -errno;
804 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
805 __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
806 if (--bo->map_count == 0)
807 bo_close_vma(bufmgr, bo);
808 return ret;
809 }
810
811 /* and mmap it */
812 bo->gtt_virtual = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
813 MAP_SHARED, bufmgr->fd, mmap_arg.offset);
814 if (bo->gtt_virtual == MAP_FAILED) {
815 bo->gtt_virtual = NULL;
816 ret = -errno;
817 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
818 __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
819 if (--bo->map_count == 0)
820 bo_close_vma(bufmgr, bo);
821 return ret;
822 }
823 }
824
825 bo->virtual = bo->gtt_virtual;
826
827 DBG("bo_map_gtt: %d (%s) -> %p\n", bo->gem_handle, bo->name,
828 bo->gtt_virtual);
829
830 return 0;
831 }
832
833 int
834 brw_bo_map_gtt(struct brw_bo *bo)
835 {
836 struct brw_bufmgr *bufmgr = bo->bufmgr;
837 struct drm_i915_gem_set_domain set_domain;
838 int ret;
839
840 pthread_mutex_lock(&bufmgr->lock);
841
842 ret = map_gtt(bo);
843 if (ret) {
844 pthread_mutex_unlock(&bufmgr->lock);
845 return ret;
846 }
847
848 /* Now move it to the GTT domain so that the GPU and CPU
849 * caches are flushed and the GPU isn't actively using the
850 * buffer.
851 *
852 * The pagefault handler does this domain change for us when
853 * it has unbound the BO from the GTT, but it's up to us to
854 * tell it when we're about to use things if we had done
855 * rendering and it still happens to be bound to the GTT.
856 */
857 memclear(set_domain);
858 set_domain.handle = bo->gem_handle;
859 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
860 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
861 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
862 if (ret != 0) {
863 DBG("%s:%d: Error setting domain %d: %s\n",
864 __FILE__, __LINE__, bo->gem_handle, strerror(errno));
865 }
866
867 bo_mark_mmaps_incoherent(bo);
868 VG(VALGRIND_MAKE_MEM_DEFINED(bo->gtt_virtual, bo->size));
869 pthread_mutex_unlock(&bufmgr->lock);
870
871 return 0;
872 }
873
874 /**
875 * Performs a mapping of the buffer object like the normal GTT
876 * mapping, but avoids waiting for the GPU to be done reading from or
877 * rendering to the buffer.
878 *
879 * This is used in the implementation of GL_ARB_map_buffer_range: The
880 * user asks to create a buffer, then does a mapping, fills some
881 * space, runs a drawing command, then asks to map it again without
882 * synchronizing because it guarantees that it won't write over the
883 * data that the GPU is busy using (or, more specifically, that if it
884 * does write over the data, it acknowledges that rendering is
885 * undefined).
886 */
887
888 int
889 brw_bo_map_unsynchronized(struct brw_bo *bo)
890 {
891 struct brw_bufmgr *bufmgr = bo->bufmgr;
892 int ret;
893
894 /* If the CPU cache isn't coherent with the GTT, then use a
895 * regular synchronized mapping. The problem is that we don't
896 * track where the buffer was last used on the CPU side in
897 * terms of brw_bo_map vs brw_bo_map_gtt, so
898 * we would potentially corrupt the buffer even when the user
899 * does reasonable things.
900 */
901 if (!bufmgr->has_llc)
902 return brw_bo_map_gtt(bo);
903
904 pthread_mutex_lock(&bufmgr->lock);
905
906 ret = map_gtt(bo);
907 if (ret == 0) {
908 bo_mark_mmaps_incoherent(bo);
909 VG(VALGRIND_MAKE_MEM_DEFINED(bo->gtt_virtual, bo->size));
910 }
911
912 pthread_mutex_unlock(&bufmgr->lock);
913
914 return ret;
915 }
916
917 int
918 brw_bo_unmap(struct brw_bo *bo)
919 {
920 struct brw_bufmgr *bufmgr = bo->bufmgr;
921 int ret = 0;
922
923 if (bo == NULL)
924 return 0;
925
926 pthread_mutex_lock(&bufmgr->lock);
927
928 if (bo->map_count <= 0) {
929 DBG("attempted to unmap an unmapped bo\n");
930 pthread_mutex_unlock(&bufmgr->lock);
931 /* Preserve the old behaviour of just treating this as a
932 * no-op rather than reporting the error.
933 */
934 return 0;
935 }
936
937 /* We need to unmap after every innovation as we cannot track
938 * an open vma for every bo as that will exhaust the system
939 * limits and cause later failures.
940 */
941 if (--bo->map_count == 0) {
942 bo_close_vma(bufmgr, bo);
943 bo_mark_mmaps_incoherent(bo);
944 bo->virtual = NULL;
945 }
946 pthread_mutex_unlock(&bufmgr->lock);
947
948 return ret;
949 }
950
951 int
952 brw_bo_subdata(struct brw_bo *bo, unsigned long offset,
953 unsigned long size, const void *data)
954 {
955 struct brw_bufmgr *bufmgr = bo->bufmgr;
956 struct drm_i915_gem_pwrite pwrite;
957 int ret;
958
959 memclear(pwrite);
960 pwrite.handle = bo->gem_handle;
961 pwrite.offset = offset;
962 pwrite.size = size;
963 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
964 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
965 if (ret != 0) {
966 ret = -errno;
967 DBG("%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
968 __FILE__, __LINE__, bo->gem_handle, (int) offset,
969 (int) size, strerror(errno));
970 }
971
972 return ret;
973 }
974
975 int
976 brw_bo_get_subdata(struct brw_bo *bo, unsigned long offset,
977 unsigned long size, void *data)
978 {
979 struct brw_bufmgr *bufmgr = bo->bufmgr;
980 struct drm_i915_gem_pread pread;
981 int ret;
982
983 memclear(pread);
984 pread.handle = bo->gem_handle;
985 pread.offset = offset;
986 pread.size = size;
987 pread.data_ptr = (uint64_t) (uintptr_t) data;
988 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
989 if (ret != 0) {
990 ret = -errno;
991 DBG("%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
992 __FILE__, __LINE__, bo->gem_handle, (int) offset,
993 (int) size, strerror(errno));
994 }
995
996 return ret;
997 }
998
999 /** Waits for all GPU rendering with the object to have completed. */
1000 void
1001 brw_bo_wait_rendering(struct brw_bo *bo)
1002 {
1003 struct brw_bufmgr *bufmgr = bo->bufmgr;
1004 struct drm_i915_gem_set_domain set_domain;
1005 int ret;
1006
1007 memclear(set_domain);
1008 set_domain.handle = bo->gem_handle;
1009 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
1010 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
1011 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
1012 if (ret != 0) {
1013 DBG("%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
1014 __FILE__, __LINE__, bo->gem_handle,
1015 set_domain.read_domains, set_domain.write_domain, strerror(errno));
1016 }
1017 }
1018
1019 /**
1020 * Waits on a BO for the given amount of time.
1021 *
1022 * @bo: buffer object to wait for
1023 * @timeout_ns: amount of time to wait in nanoseconds.
1024 * If value is less than 0, an infinite wait will occur.
1025 *
1026 * Returns 0 if the wait was successful ie. the last batch referencing the
1027 * object has completed within the allotted time. Otherwise some negative return
1028 * value describes the error. Of particular interest is -ETIME when the wait has
1029 * failed to yield the desired result.
1030 *
1031 * Similar to brw_bo_wait_rendering except a timeout parameter allows
1032 * the operation to give up after a certain amount of time. Another subtle
1033 * difference is the internal locking semantics are different (this variant does
1034 * not hold the lock for the duration of the wait). This makes the wait subject
1035 * to a larger userspace race window.
1036 *
1037 * The implementation shall wait until the object is no longer actively
1038 * referenced within a batch buffer at the time of the call. The wait will
1039 * not guarantee that the buffer is re-issued via another thread, or an flinked
1040 * handle. Userspace must make sure this race does not occur if such precision
1041 * is important.
1042 *
1043 * Note that some kernels have broken the inifite wait for negative values
1044 * promise, upgrade to latest stable kernels if this is the case.
1045 */
1046 int
1047 brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns)
1048 {
1049 struct brw_bufmgr *bufmgr = bo->bufmgr;
1050 struct drm_i915_gem_wait wait;
1051 int ret;
1052
1053 memclear(wait);
1054 wait.bo_handle = bo->gem_handle;
1055 wait.timeout_ns = timeout_ns;
1056 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
1057 if (ret == -1)
1058 return -errno;
1059
1060 return ret;
1061 }
1062
1063 void
1064 brw_bufmgr_destroy(struct brw_bufmgr *bufmgr)
1065 {
1066 pthread_mutex_destroy(&bufmgr->lock);
1067
1068 /* Free any cached buffer objects we were going to reuse */
1069 for (int i = 0; i < bufmgr->num_buckets; i++) {
1070 struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i];
1071
1072 list_for_each_entry_safe(struct brw_bo, bo, &bucket->head, head) {
1073 list_del(&bo->head);
1074
1075 bo_free(bo);
1076 }
1077 }
1078
1079 _mesa_hash_table_destroy(bufmgr->name_table, NULL);
1080 _mesa_hash_table_destroy(bufmgr->handle_table, NULL);
1081
1082 free(bufmgr);
1083 }
1084
1085 static int
1086 bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode,
1087 uint32_t stride)
1088 {
1089 struct brw_bufmgr *bufmgr = bo->bufmgr;
1090 struct drm_i915_gem_set_tiling set_tiling;
1091 int ret;
1092
1093 if (bo->global_name == 0 &&
1094 tiling_mode == bo->tiling_mode && stride == bo->stride)
1095 return 0;
1096
1097 memset(&set_tiling, 0, sizeof(set_tiling));
1098 do {
1099 /* set_tiling is slightly broken and overwrites the
1100 * input on the error path, so we have to open code
1101 * rmIoctl.
1102 */
1103 set_tiling.handle = bo->gem_handle;
1104 set_tiling.tiling_mode = tiling_mode;
1105 set_tiling.stride = stride;
1106
1107 ret = ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1108 } while (ret == -1 && (errno == EINTR || errno == EAGAIN));
1109 if (ret == -1)
1110 return -errno;
1111
1112 bo->tiling_mode = set_tiling.tiling_mode;
1113 bo->swizzle_mode = set_tiling.swizzle_mode;
1114 bo->stride = set_tiling.stride;
1115 return 0;
1116 }
1117
1118 int
1119 brw_bo_get_tiling(struct brw_bo *bo, uint32_t *tiling_mode,
1120 uint32_t *swizzle_mode)
1121 {
1122 *tiling_mode = bo->tiling_mode;
1123 *swizzle_mode = bo->swizzle_mode;
1124 return 0;
1125 }
1126
1127 struct brw_bo *
1128 brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr, int prime_fd,
1129 int size)
1130 {
1131 int ret;
1132 uint32_t handle;
1133 struct brw_bo *bo;
1134 struct drm_i915_gem_get_tiling get_tiling;
1135
1136 pthread_mutex_lock(&bufmgr->lock);
1137 ret = drmPrimeFDToHandle(bufmgr->fd, prime_fd, &handle);
1138 if (ret) {
1139 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
1140 strerror(errno));
1141 pthread_mutex_unlock(&bufmgr->lock);
1142 return NULL;
1143 }
1144
1145 /*
1146 * See if the kernel has already returned this buffer to us. Just as
1147 * for named buffers, we must not create two bo's pointing at the same
1148 * kernel object
1149 */
1150 bo = hash_find_bo(bufmgr->handle_table, handle);
1151 if (bo) {
1152 brw_bo_reference(bo);
1153 goto out;
1154 }
1155
1156 bo = calloc(1, sizeof(*bo));
1157 if (!bo)
1158 goto out;
1159
1160 p_atomic_set(&bo->refcount, 1);
1161 list_inithead(&bo->vma_list);
1162
1163 /* Determine size of bo. The fd-to-handle ioctl really should
1164 * return the size, but it doesn't. If we have kernel 3.12 or
1165 * later, we can lseek on the prime fd to get the size. Older
1166 * kernels will just fail, in which case we fall back to the
1167 * provided (estimated or guess size). */
1168 ret = lseek(prime_fd, 0, SEEK_END);
1169 if (ret != -1)
1170 bo->size = ret;
1171 else
1172 bo->size = size;
1173
1174 bo->bufmgr = bufmgr;
1175
1176 bo->gem_handle = handle;
1177 _mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
1178
1179 bo->name = "prime";
1180 bo->reusable = false;
1181
1182 memclear(get_tiling);
1183 get_tiling.handle = bo->gem_handle;
1184 if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
1185 goto err;
1186
1187 bo->tiling_mode = get_tiling.tiling_mode;
1188 bo->swizzle_mode = get_tiling.swizzle_mode;
1189 /* XXX stride is unknown */
1190
1191 out:
1192 pthread_mutex_unlock(&bufmgr->lock);
1193 return bo;
1194
1195 err:
1196 bo_free(bo);
1197 pthread_mutex_unlock(&bufmgr->lock);
1198 return NULL;
1199 }
1200
1201 int
1202 brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd)
1203 {
1204 struct brw_bufmgr *bufmgr = bo->bufmgr;
1205
1206 if (drmPrimeHandleToFD(bufmgr->fd, bo->gem_handle,
1207 DRM_CLOEXEC, prime_fd) != 0)
1208 return -errno;
1209
1210 bo->reusable = false;
1211
1212 return 0;
1213 }
1214
1215 int
1216 brw_bo_flink(struct brw_bo *bo, uint32_t *name)
1217 {
1218 struct brw_bufmgr *bufmgr = bo->bufmgr;
1219
1220 if (!bo->global_name) {
1221 struct drm_gem_flink flink;
1222
1223 memclear(flink);
1224 flink.handle = bo->gem_handle;
1225 if (drmIoctl(bufmgr->fd, DRM_IOCTL_GEM_FLINK, &flink))
1226 return -errno;
1227
1228 pthread_mutex_lock(&bufmgr->lock);
1229 if (!bo->global_name) {
1230 bo->global_name = flink.name;
1231 bo->reusable = false;
1232
1233 _mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo);
1234 }
1235 pthread_mutex_unlock(&bufmgr->lock);
1236 }
1237
1238 *name = bo->global_name;
1239 return 0;
1240 }
1241
1242 /**
1243 * Enables unlimited caching of buffer objects for reuse.
1244 *
1245 * This is potentially very memory expensive, as the cache at each bucket
1246 * size is only bounded by how many buffers of that size we've managed to have
1247 * in flight at once.
1248 */
1249 void
1250 brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr)
1251 {
1252 bufmgr->bo_reuse = true;
1253 }
1254
1255 static void
1256 add_bucket(struct brw_bufmgr *bufmgr, int size)
1257 {
1258 unsigned int i = bufmgr->num_buckets;
1259
1260 assert(i < ARRAY_SIZE(bufmgr->cache_bucket));
1261
1262 list_inithead(&bufmgr->cache_bucket[i].head);
1263 bufmgr->cache_bucket[i].size = size;
1264 bufmgr->num_buckets++;
1265 }
1266
1267 static void
1268 init_cache_buckets(struct brw_bufmgr *bufmgr)
1269 {
1270 unsigned long size, cache_max_size = 64 * 1024 * 1024;
1271
1272 /* OK, so power of two buckets was too wasteful of memory.
1273 * Give 3 other sizes between each power of two, to hopefully
1274 * cover things accurately enough. (The alternative is
1275 * probably to just go for exact matching of sizes, and assume
1276 * that for things like composited window resize the tiled
1277 * width/height alignment and rounding of sizes to pages will
1278 * get us useful cache hit rates anyway)
1279 */
1280 add_bucket(bufmgr, 4096);
1281 add_bucket(bufmgr, 4096 * 2);
1282 add_bucket(bufmgr, 4096 * 3);
1283
1284 /* Initialize the linked lists for BO reuse cache. */
1285 for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
1286 add_bucket(bufmgr, size);
1287
1288 add_bucket(bufmgr, size + size * 1 / 4);
1289 add_bucket(bufmgr, size + size * 2 / 4);
1290 add_bucket(bufmgr, size + size * 3 / 4);
1291 }
1292 }
1293
1294 void
1295 brw_bufmgr_gem_set_vma_cache_size(struct brw_bufmgr *bufmgr, int limit)
1296 {
1297 bufmgr->vma_max = limit;
1298
1299 bo_purge_vma_cache(bufmgr);
1300 }
1301
1302 uint32_t
1303 brw_create_hw_context(struct brw_bufmgr *bufmgr)
1304 {
1305 struct drm_i915_gem_context_create create;
1306 int ret;
1307
1308 memclear(create);
1309 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create);
1310 if (ret != 0) {
1311 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno));
1312 return 0;
1313 }
1314
1315 return create.ctx_id;
1316 }
1317
1318 void
1319 brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id)
1320 {
1321 struct drm_i915_gem_context_destroy d = {.ctx_id = ctx_id };
1322
1323 if (ctx_id != 0 &&
1324 drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY, &d) != 0) {
1325 fprintf(stderr, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1326 strerror(errno));
1327 }
1328 }
1329
1330 int
1331 brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset, uint64_t *result)
1332 {
1333 struct drm_i915_reg_read reg_read;
1334 int ret;
1335
1336 memclear(reg_read);
1337 reg_read.offset = offset;
1338
1339 ret = drmIoctl(bufmgr->fd, DRM_IOCTL_I915_REG_READ, &reg_read);
1340
1341 *result = reg_read.val;
1342 return ret;
1343 }
1344
1345 void *
1346 brw_bo_map__gtt(struct brw_bo *bo)
1347 {
1348 struct brw_bufmgr *bufmgr = bo->bufmgr;
1349
1350 if (bo->gtt_virtual)
1351 return bo->gtt_virtual;
1352
1353 pthread_mutex_lock(&bufmgr->lock);
1354 if (bo->gtt_virtual == NULL) {
1355 struct drm_i915_gem_mmap_gtt mmap_arg;
1356 void *ptr;
1357
1358 DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n",
1359 bo->gem_handle, bo->name, bo->map_count);
1360
1361 if (bo->map_count++ == 0)
1362 bo_open_vma(bufmgr, bo);
1363
1364 memclear(mmap_arg);
1365 mmap_arg.handle = bo->gem_handle;
1366
1367 /* Get the fake offset back... */
1368 ptr = MAP_FAILED;
1369 if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg) == 0) {
1370 /* and mmap it */
1371 ptr = drm_mmap(0, bo->size, PROT_READ | PROT_WRITE,
1372 MAP_SHARED, bufmgr->fd, mmap_arg.offset);
1373 }
1374 if (ptr == MAP_FAILED) {
1375 if (--bo->map_count == 0)
1376 bo_close_vma(bufmgr, bo);
1377 ptr = NULL;
1378 }
1379
1380 bo->gtt_virtual = ptr;
1381 }
1382 pthread_mutex_unlock(&bufmgr->lock);
1383
1384 return bo->gtt_virtual;
1385 }
1386
1387 void *
1388 brw_bo_map__cpu(struct brw_bo *bo)
1389 {
1390 struct brw_bufmgr *bufmgr = bo->bufmgr;
1391
1392 if (bo->mem_virtual)
1393 return bo->mem_virtual;
1394
1395 pthread_mutex_lock(&bufmgr->lock);
1396 if (!bo->mem_virtual) {
1397 struct drm_i915_gem_mmap mmap_arg;
1398
1399 if (bo->map_count++ == 0)
1400 bo_open_vma(bufmgr, bo);
1401
1402 DBG("bo_map: %d (%s), map_count=%d\n",
1403 bo->gem_handle, bo->name, bo->map_count);
1404
1405 memclear(mmap_arg);
1406 mmap_arg.handle = bo->gem_handle;
1407 mmap_arg.size = bo->size;
1408 if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg)) {
1409 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1410 __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
1411 if (--bo->map_count == 0)
1412 bo_close_vma(bufmgr, bo);
1413 } else {
1414 VG(VALGRIND_MALLOCLIKE_BLOCK
1415 (mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1416 bo->mem_virtual = (void *) (uintptr_t) mmap_arg.addr_ptr;
1417 }
1418 }
1419 pthread_mutex_unlock(&bufmgr->lock);
1420
1421 return bo->mem_virtual;
1422 }
1423
1424 void *
1425 brw_bo_map__wc(struct brw_bo *bo)
1426 {
1427 struct brw_bufmgr *bufmgr = bo->bufmgr;
1428
1429 if (bo->wc_virtual)
1430 return bo->wc_virtual;
1431
1432 pthread_mutex_lock(&bufmgr->lock);
1433 if (!bo->wc_virtual) {
1434 struct drm_i915_gem_mmap mmap_arg;
1435
1436 if (bo->map_count++ == 0)
1437 bo_open_vma(bufmgr, bo);
1438
1439 DBG("bo_map: %d (%s), map_count=%d\n",
1440 bo->gem_handle, bo->name, bo->map_count);
1441
1442 memclear(mmap_arg);
1443 mmap_arg.handle = bo->gem_handle;
1444 mmap_arg.size = bo->size;
1445 mmap_arg.flags = I915_MMAP_WC;
1446 if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg)) {
1447 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1448 __FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
1449 if (--bo->map_count == 0)
1450 bo_close_vma(bufmgr, bo);
1451 } else {
1452 VG(VALGRIND_MALLOCLIKE_BLOCK
1453 (mmap_arg.addr_ptr, mmap_arg.size, 0, 1));
1454 bo->wc_virtual = (void *) (uintptr_t) mmap_arg.addr_ptr;
1455 }
1456 }
1457 pthread_mutex_unlock(&bufmgr->lock);
1458
1459 return bo->wc_virtual;
1460 }
1461
1462 /**
1463 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1464 * and manage map buffer objections.
1465 *
1466 * \param fd File descriptor of the opened DRM device.
1467 */
1468 struct brw_bufmgr *
1469 brw_bufmgr_init(struct gen_device_info *devinfo, int fd, int batch_size)
1470 {
1471 struct brw_bufmgr *bufmgr;
1472
1473 bufmgr = calloc(1, sizeof(*bufmgr));
1474 if (bufmgr == NULL)
1475 return NULL;
1476
1477 /* Handles to buffer objects belong to the device fd and are not
1478 * reference counted by the kernel. If the same fd is used by
1479 * multiple parties (threads sharing the same screen bufmgr, or
1480 * even worse the same device fd passed to multiple libraries)
1481 * ownership of those handles is shared by those independent parties.
1482 *
1483 * Don't do this! Ensure that each library/bufmgr has its own device
1484 * fd so that its namespace does not clash with another.
1485 */
1486 bufmgr->fd = fd;
1487
1488 if (pthread_mutex_init(&bufmgr->lock, NULL) != 0) {
1489 free(bufmgr);
1490 return NULL;
1491 }
1492
1493 bufmgr->has_llc = devinfo->has_llc;
1494
1495 init_cache_buckets(bufmgr);
1496
1497 list_inithead(&bufmgr->vma_cache);
1498 bufmgr->vma_max = -1; /* unlimited by default */
1499
1500 bufmgr->name_table =
1501 _mesa_hash_table_create(NULL, key_hash_uint, key_uint_equal);
1502 bufmgr->handle_table =
1503 _mesa_hash_table_create(NULL, key_hash_uint, key_uint_equal);
1504
1505 return bufmgr;
1506 }