2 * Copyright © 2007 Red Hat Inc.
3 * Copyright © 2007-2017 Intel Corporation
4 * Copyright © 2006 VMware, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * Authors: Thomas Hellström <thellstrom@vmware.com>
29 * Keith Whitwell <keithw@vmware.com>
30 * Eric Anholt <eric@anholt.net>
31 * Dave Airlie <airlied@linux.ie>
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
48 #include <sys/types.h>
53 #define ETIME ETIMEDOUT
55 #include "common/gen_clflush.h"
56 #include "common/gen_debug.h"
57 #include "common/gen_gem.h"
58 #include "dev/gen_device_info.h"
59 #include "libdrm_macros.h"
60 #include "main/macros.h"
61 #include "util/macros.h"
62 #include "util/hash_table.h"
63 #include "util/list.h"
64 #include "util/u_dynarray.h"
66 #include "brw_bufmgr.h"
67 #include "brw_context.h"
80 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
81 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
82 * leaked. All because it does not call VG(cli_free) from its
83 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
84 * and allocation, we mark it available for use upon mmapping and remove
87 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
88 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
90 #define PAGE_SIZE 4096
92 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
95 atomic_add_unless(int *v
, int add
, int unless
)
99 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
105 * i965 fixed-size bucketing VMA allocator.
107 * The BO cache maintains "cache buckets" for buffers of various sizes.
108 * All buffers in a given bucket are identically sized - when allocating,
109 * we always round up to the bucket size. This means that virtually all
110 * allocations are fixed-size; only buffers which are too large to fit in
111 * a bucket can be variably-sized.
113 * We create an allocator for each bucket. Each contains a free-list, where
114 * each node contains a <starting address, 64-bit bitmap> pair. Each bit
115 * represents a bucket-sized block of memory. (At the first level, each
116 * bit corresponds to a page. For the second bucket, bits correspond to
117 * two pages, and so on.) 1 means a block is free, and 0 means it's in-use.
118 * The lowest bit in the bitmap is for the first block.
120 * This makes allocations cheap - any bit of any node will do. We can pick
121 * the head of the list and use ffs() to find a free block. If there are
122 * none, we allocate 64 blocks from a larger allocator - either a bigger
123 * bucketing allocator, or a fallback top-level allocator for large objects.
125 struct vma_bucket_node
{
126 uint64_t start_address
;
130 struct bo_cache_bucket
{
131 /** List of cached BOs. */
132 struct list_head head
;
134 /** Size of this bucket, in bytes. */
137 /** List of vma_bucket_nodes. */
138 struct util_dynarray vma_list
[BRW_MEMZONE_COUNT
];
146 /** Array of lists of cached gem objects of power-of-two sizes */
147 struct bo_cache_bucket cache_bucket
[14 * 4];
151 struct hash_table
*name_table
;
152 struct hash_table
*handle_table
;
154 struct util_vma_heap vma_allocator
[BRW_MEMZONE_COUNT
];
160 uint64_t initial_kflags
;
163 static int bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
166 static void bo_free(struct brw_bo
*bo
);
168 static uint64_t vma_alloc(struct brw_bufmgr
*bufmgr
,
169 enum brw_memory_zone memzone
,
170 uint64_t size
, uint64_t alignment
);
173 key_hash_uint(const void *key
)
175 return _mesa_hash_data(key
, 4);
179 key_uint_equal(const void *a
, const void *b
)
181 return *((unsigned *) a
) == *((unsigned *) b
);
184 static struct brw_bo
*
185 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
187 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
188 return entry
? (struct brw_bo
*) entry
->data
: NULL
;
192 bo_tile_size(struct brw_bufmgr
*bufmgr
, uint64_t size
, uint32_t tiling
)
194 if (tiling
== I915_TILING_NONE
)
197 /* 965+ just need multiples of page size for tiling */
198 return ALIGN(size
, PAGE_SIZE
);
202 * Round a given pitch up to the minimum required for X tiling on a
203 * given chip. We use 512 as the minimum to allow for a later tiling
207 bo_tile_pitch(struct brw_bufmgr
*bufmgr
, uint32_t pitch
, uint32_t tiling
)
209 unsigned long tile_width
;
211 /* If untiled, then just align it so that we can do rendering
212 * to it with the 3D engine.
214 if (tiling
== I915_TILING_NONE
)
215 return ALIGN(pitch
, 64);
217 if (tiling
== I915_TILING_X
)
222 /* 965 is flexible */
223 return ALIGN(pitch
, tile_width
);
227 * This function finds the correct bucket fit for the input size.
228 * The function works with O(1) complexity when the requested size
229 * was queried instead of iterating the size through all the buckets.
231 static struct bo_cache_bucket
*
232 bucket_for_size(struct brw_bufmgr
*bufmgr
, uint64_t size
)
234 /* Calculating the pages and rounding up to the page size. */
235 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
237 /* Row Bucket sizes clz((x-1) | 3) Row Column
238 * in pages stride size
239 * 0: 1 2 3 4 -> 30 30 30 30 4 1
240 * 1: 5 6 7 8 -> 29 29 29 29 4 1
241 * 2: 10 12 14 16 -> 28 28 28 28 8 2
242 * 3: 20 24 28 32 -> 27 27 27 27 16 4
244 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
245 const unsigned row_max_pages
= 4 << row
;
247 /* The '& ~2' is the special case for row 1. In row 1, max pages /
248 * 2 is 2, but the previous row maximum is zero (because there is
249 * no previous row). All row maximum sizes are power of 2, so that
250 * is the only case where that bit will be set.
252 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
253 int col_size_log2
= row
- 1;
254 col_size_log2
+= (col_size_log2
< 0);
256 const unsigned col
= (pages
- prev_row_max_pages
+
257 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
259 /* Calculating the index based on the row and column. */
260 const unsigned index
= (row
* 4) + (col
- 1);
262 return (index
< bufmgr
->num_buckets
) ?
263 &bufmgr
->cache_bucket
[index
] : NULL
;
266 static enum brw_memory_zone
267 memzone_for_address(uint64_t address
)
269 const uint64_t _4GB
= 1ull << 32;
272 return BRW_MEMZONE_OTHER
;
274 return BRW_MEMZONE_LOW_4G
;
278 bucket_vma_alloc(struct brw_bufmgr
*bufmgr
,
279 struct bo_cache_bucket
*bucket
,
280 enum brw_memory_zone memzone
)
282 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
283 struct vma_bucket_node
*node
;
285 if (vma_list
->size
== 0) {
286 /* This bucket allocator is out of space - allocate a new block of
287 * memory for 64 blocks from a larger allocator (either a larger
288 * bucket or util_vma).
290 * We align the address to the node size (64 blocks) so that
291 * bucket_vma_free can easily compute the starting address of this
292 * block by rounding any address we return down to the node size.
294 * Set the first bit used, and return the start address.
296 uint64_t node_size
= 64ull * bucket
->size
;
297 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
302 uint64_t addr
= vma_alloc(bufmgr
, memzone
, node_size
, node_size
);
303 node
->start_address
= gen_48b_address(addr
);
304 node
->bitmap
= ~1ull;
305 return node
->start_address
;
308 /* Pick any bit from any node - they're all the right size and free. */
309 node
= util_dynarray_top_ptr(vma_list
, struct vma_bucket_node
);
310 int bit
= ffsll(node
->bitmap
) - 1;
311 assert(bit
>= 0 && bit
<= 63);
313 /* Reserve the memory by clearing the bit. */
314 assert((node
->bitmap
& (1ull << bit
)) != 0ull);
315 node
->bitmap
&= ~(1ull << bit
);
317 uint64_t addr
= node
->start_address
+ bit
* bucket
->size
;
319 /* If this node is now completely full, remove it from the free list. */
320 if (node
->bitmap
== 0ull) {
321 (void) util_dynarray_pop(vma_list
, struct vma_bucket_node
);
328 bucket_vma_free(struct bo_cache_bucket
*bucket
, uint64_t address
)
330 enum brw_memory_zone memzone
= memzone_for_address(address
);
331 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
332 const uint64_t node_bytes
= 64ull * bucket
->size
;
333 struct vma_bucket_node
*node
= NULL
;
335 /* bucket_vma_alloc allocates 64 blocks at a time, and aligns it to
336 * that 64 block size. So, we can round down to get the starting address.
338 uint64_t start
= (address
/ node_bytes
) * node_bytes
;
340 /* Dividing the offset from start by bucket size gives us the bit index. */
341 int bit
= (address
- start
) / bucket
->size
;
343 assert(start
+ bit
* bucket
->size
== address
);
345 util_dynarray_foreach(vma_list
, struct vma_bucket_node
, cur
) {
346 if (cur
->start_address
== start
) {
353 /* No node - the whole group of 64 blocks must have been in-use. */
354 node
= util_dynarray_grow(vma_list
, sizeof(struct vma_bucket_node
));
357 return; /* bogus, leaks some GPU VMA, but nothing we can do... */
359 node
->start_address
= start
;
363 /* Set the bit to return the memory. */
364 assert((node
->bitmap
& (1ull << bit
)) == 0ull);
365 node
->bitmap
|= 1ull << bit
;
367 /* The block might be entirely free now, and if so, we could return it
368 * to the larger allocator. But we may as well hang on to it, in case
369 * we get more allocations at this block size.
373 static struct bo_cache_bucket
*
374 get_bucket_allocator(struct brw_bufmgr
*bufmgr
, uint64_t size
)
376 /* Skip using the bucket allocator for very large sizes, as it allocates
377 * 64 of them and this can balloon rather quickly.
379 if (size
> 1024 * PAGE_SIZE
)
382 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
384 if (bucket
&& bucket
->size
== size
)
391 * Allocate a section of virtual memory for a buffer, assigning an address.
393 * This uses either the bucket allocator for the given size, or the large
394 * object allocator (util_vma).
397 vma_alloc(struct brw_bufmgr
*bufmgr
,
398 enum brw_memory_zone memzone
,
402 /* Without softpin support, we let the kernel assign addresses. */
403 assert(brw_using_softpin(bufmgr
));
405 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
409 addr
= bucket_vma_alloc(bufmgr
, bucket
, memzone
);
411 addr
= util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
,
415 assert((addr
>> 48ull) == 0);
416 assert((addr
% alignment
) == 0);
418 return gen_canonical_address(addr
);
422 * Free a virtual memory area, allowing the address to be reused.
425 vma_free(struct brw_bufmgr
*bufmgr
,
429 assert(brw_using_softpin(bufmgr
));
431 /* Un-canonicalize the address. */
432 address
= gen_48b_address(address
);
437 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
440 bucket_vma_free(bucket
, address
);
442 enum brw_memory_zone memzone
= memzone_for_address(address
);
443 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
448 brw_bo_busy(struct brw_bo
*bo
)
450 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
451 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
453 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
455 bo
->idle
= !busy
.busy
;
462 brw_bo_madvise(struct brw_bo
*bo
, int state
)
464 struct drm_i915_gem_madvise madv
= {
465 .handle
= bo
->gem_handle
,
470 drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
472 return madv
.retained
;
475 /* drop the oldest entries that have been purged by the kernel */
477 brw_bo_cache_purge_bucket(struct brw_bufmgr
*bufmgr
,
478 struct bo_cache_bucket
*bucket
)
480 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
481 if (brw_bo_madvise(bo
, I915_MADV_DONTNEED
))
489 static struct brw_bo
*
490 bo_alloc_internal(struct brw_bufmgr
*bufmgr
,
493 enum brw_memory_zone memzone
,
495 uint32_t tiling_mode
,
500 struct bo_cache_bucket
*bucket
;
501 bool alloc_from_cache
;
506 if (flags
& BO_ALLOC_BUSY
)
509 if (flags
& BO_ALLOC_ZEROED
)
512 /* BUSY does doesn't really jive with ZEROED as we have to wait for it to
513 * be idle before we can memset. Just disallow that combination.
515 assert(!(busy
&& zeroed
));
517 /* Round the allocated size up to a power of two number of pages. */
518 bucket
= bucket_for_size(bufmgr
, size
);
520 /* If we don't have caching at this size, don't actually round the
523 if (bucket
== NULL
) {
524 unsigned int page_size
= getpagesize();
525 bo_size
= size
== 0 ? page_size
: ALIGN(size
, page_size
);
527 bo_size
= bucket
->size
;
531 mtx_lock(&bufmgr
->lock
);
532 /* Get a buffer out of the cache if available */
534 alloc_from_cache
= false;
535 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
536 if (busy
&& !zeroed
) {
537 /* Allocate new render-target BOs from the tail (MRU)
538 * of the list, as it will likely be hot in the GPU
539 * cache and in the aperture for us. If the caller
540 * asked us to zero the buffer, we don't want this
541 * because we are going to mmap it.
543 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.prev
, head
);
545 alloc_from_cache
= true;
547 /* For non-render-target BOs (where we're probably
548 * going to map it first thing in order to fill it
549 * with data), check if the last BO in the cache is
550 * unbusy, and only reuse in that case. Otherwise,
551 * allocating a new buffer is probably faster than
552 * waiting for the GPU to finish.
554 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.next
, head
);
555 if (!brw_bo_busy(bo
)) {
556 alloc_from_cache
= true;
561 if (alloc_from_cache
) {
562 if (!brw_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
564 brw_bo_cache_purge_bucket(bufmgr
, bucket
);
568 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
574 void *map
= brw_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
579 memset(map
, 0, bo_size
);
584 if (alloc_from_cache
) {
585 /* If the cache BO isn't in the right memory zone, free the old
586 * memory and assign it a new address.
588 if ((bo
->kflags
& EXEC_OBJECT_PINNED
) &&
589 memzone
!= memzone_for_address(bo
->gtt_offset
)) {
590 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
591 bo
->gtt_offset
= 0ull;
594 bo
= calloc(1, sizeof(*bo
));
601 struct drm_i915_gem_create create
= { .size
= bo_size
};
603 /* All new BOs we get from the kernel are zeroed, so we don't need to
604 * worry about that here.
606 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
612 bo
->gem_handle
= create
.handle
;
616 bo
->tiling_mode
= I915_TILING_NONE
;
617 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
620 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
623 /* Calling set_domain() will allocate pages for the BO outside of the
624 * struct mutex lock in the kernel, which is more efficient than waiting
625 * to create them during the first execbuf that uses the BO.
627 struct drm_i915_gem_set_domain sd
= {
628 .handle
= bo
->gem_handle
,
629 .read_domains
= I915_GEM_DOMAIN_CPU
,
633 if (drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
638 p_atomic_set(&bo
->refcount
, 1);
640 bo
->cache_coherent
= bufmgr
->has_llc
;
642 bo
->kflags
= bufmgr
->initial_kflags
;
644 if ((bo
->kflags
& EXEC_OBJECT_PINNED
) && bo
->gtt_offset
== 0ull) {
645 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, 1);
647 if (bo
->gtt_offset
== 0ull)
651 mtx_unlock(&bufmgr
->lock
);
653 DBG("bo_create: buf %d (%s) %llub\n", bo
->gem_handle
, bo
->name
,
654 (unsigned long long) size
);
661 mtx_unlock(&bufmgr
->lock
);
666 brw_bo_alloc(struct brw_bufmgr
*bufmgr
,
667 const char *name
, uint64_t size
,
668 enum brw_memory_zone memzone
)
670 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
671 0, I915_TILING_NONE
, 0);
675 brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
, const char *name
,
676 uint64_t size
, enum brw_memory_zone memzone
,
677 uint32_t tiling_mode
, uint32_t pitch
,
680 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
681 flags
, tiling_mode
, pitch
);
685 brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
, const char *name
,
686 int x
, int y
, int cpp
, enum brw_memory_zone memzone
,
687 uint32_t tiling
, uint32_t *pitch
, unsigned flags
)
691 unsigned long aligned_y
, height_alignment
;
693 /* If we're tiled, our allocations are in 8 or 32-row blocks,
694 * so failure to align our height means that we won't allocate
697 * If we're untiled, we still have to align to 2 rows high
698 * because the data port accesses 2x2 blocks even if the
699 * bottom row isn't to be rendered, so failure to align means
700 * we could walk off the end of the GTT and fault. This is
701 * documented on 965, and may be the case on older chipsets
702 * too so we try to be careful.
705 height_alignment
= 2;
707 if (tiling
== I915_TILING_X
)
708 height_alignment
= 8;
709 else if (tiling
== I915_TILING_Y
)
710 height_alignment
= 32;
711 aligned_y
= ALIGN(y
, height_alignment
);
714 stride
= bo_tile_pitch(bufmgr
, stride
, tiling
);
715 size
= stride
* aligned_y
;
716 size
= bo_tile_size(bufmgr
, size
, tiling
);
719 if (tiling
== I915_TILING_NONE
)
722 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
723 flags
, tiling
, stride
);
727 * Returns a brw_bo wrapping the given buffer object handle.
729 * This can be used when one application needs to pass a buffer object
733 brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
734 const char *name
, unsigned int handle
)
738 /* At the moment most applications only have a few named bo.
739 * For instance, in a DRI client only the render buffers passed
740 * between X and the client are named. And since X returns the
741 * alternating names for the front/back buffer a linear search
742 * provides a sufficiently fast match.
744 mtx_lock(&bufmgr
->lock
);
745 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
747 brw_bo_reference(bo
);
751 struct drm_gem_open open_arg
= { .name
= handle
};
752 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
754 DBG("Couldn't reference %s handle 0x%08x: %s\n",
755 name
, handle
, strerror(errno
));
759 /* Now see if someone has used a prime handle to get this
760 * object from the kernel before by looking through the list
761 * again for a matching gem_handle
763 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
765 brw_bo_reference(bo
);
769 bo
= calloc(1, sizeof(*bo
));
773 p_atomic_set(&bo
->refcount
, 1);
775 bo
->size
= open_arg
.size
;
778 bo
->gem_handle
= open_arg
.handle
;
780 bo
->global_name
= handle
;
781 bo
->reusable
= false;
783 bo
->kflags
= bufmgr
->initial_kflags
;
785 if (bo
->kflags
& EXEC_OBJECT_PINNED
)
786 bo
->gtt_offset
= vma_alloc(bufmgr
, BRW_MEMZONE_OTHER
, bo
->size
, 1);
788 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
789 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
791 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
792 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
796 bo
->tiling_mode
= get_tiling
.tiling_mode
;
797 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
798 /* XXX stride is unknown */
799 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
802 mtx_unlock(&bufmgr
->lock
);
807 mtx_unlock(&bufmgr
->lock
);
812 bo_free(struct brw_bo
*bo
)
814 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
817 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
818 drm_munmap(bo
->map_cpu
, bo
->size
);
821 VG_NOACCESS(bo
->map_wc
, bo
->size
);
822 drm_munmap(bo
->map_wc
, bo
->size
);
825 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
826 drm_munmap(bo
->map_gtt
, bo
->size
);
830 struct hash_entry
*entry
;
832 if (bo
->global_name
) {
833 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
834 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
837 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
838 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
841 /* Close this object */
842 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
843 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
845 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
846 bo
->gem_handle
, bo
->name
, strerror(errno
));
849 if (bo
->kflags
& EXEC_OBJECT_PINNED
)
850 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
855 /** Frees all cached buffers significantly older than @time. */
857 cleanup_bo_cache(struct brw_bufmgr
*bufmgr
, time_t time
)
861 if (bufmgr
->time
== time
)
864 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
865 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
867 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
868 if (time
- bo
->free_time
<= 1)
881 bo_unreference_final(struct brw_bo
*bo
, time_t time
)
883 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
884 struct bo_cache_bucket
*bucket
;
886 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
888 bucket
= bucket_for_size(bufmgr
, bo
->size
);
889 /* Put the buffer into our internal cache for reuse if we can. */
890 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
891 brw_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
892 bo
->free_time
= time
;
896 list_addtail(&bo
->head
, &bucket
->head
);
903 brw_bo_unreference(struct brw_bo
*bo
)
908 assert(p_atomic_read(&bo
->refcount
) > 0);
910 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
911 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
912 struct timespec time
;
914 clock_gettime(CLOCK_MONOTONIC
, &time
);
916 mtx_lock(&bufmgr
->lock
);
918 if (p_atomic_dec_zero(&bo
->refcount
)) {
919 bo_unreference_final(bo
, time
.tv_sec
);
920 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
923 mtx_unlock(&bufmgr
->lock
);
928 bo_wait_with_stall_warning(struct brw_context
*brw
,
932 bool busy
= brw
&& brw
->perf_debug
&& !bo
->idle
;
933 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
935 brw_bo_wait_rendering(bo
);
937 if (unlikely(busy
)) {
938 elapsed
+= get_time();
939 if (elapsed
> 1e-5) /* 0.01ms */
940 perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n",
941 action
, bo
->name
, elapsed
* 1000);
946 print_flags(unsigned flags
)
948 if (flags
& MAP_READ
)
950 if (flags
& MAP_WRITE
)
952 if (flags
& MAP_ASYNC
)
954 if (flags
& MAP_PERSISTENT
)
956 if (flags
& MAP_COHERENT
)
964 brw_bo_map_cpu(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
966 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
968 /* We disallow CPU maps for writing to non-coherent buffers, as the
969 * CPU map can become invalidated when a batch is flushed out, which
970 * can happen at unpredictable times. You should use WC maps instead.
972 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
975 DBG("brw_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
977 struct drm_i915_gem_mmap mmap_arg
= {
978 .handle
= bo
->gem_handle
,
981 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
984 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
985 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
988 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
989 VG_DEFINED(map
, bo
->size
);
991 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
992 VG_NOACCESS(map
, bo
->size
);
993 drm_munmap(map
, bo
->size
);
998 DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
1002 if (!(flags
& MAP_ASYNC
)) {
1003 bo_wait_with_stall_warning(brw
, bo
, "CPU mapping");
1006 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
1007 /* If we're reusing an existing CPU mapping, the CPU caches may
1008 * contain stale data from the last time we read from that mapping.
1009 * (With the BO cache, it might even be data from a previous buffer!)
1010 * Even if it's a brand new mapping, the kernel may have zeroed the
1011 * buffer via CPU writes.
1013 * We need to invalidate those cachelines so that we see the latest
1014 * contents, and so long as we only read from the CPU mmap we do not
1015 * need to write those cachelines back afterwards.
1017 * On LLC, the emprical evidence suggests that writes from the GPU
1018 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
1019 * cachelines. (Other reads, such as the display engine, bypass the
1020 * LLC entirely requiring us to keep dirty pixels for the scanout
1021 * out of any cache.)
1023 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
1030 brw_bo_map_wc(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1032 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1034 if (!bufmgr
->has_mmap_wc
)
1038 DBG("brw_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1040 struct drm_i915_gem_mmap mmap_arg
= {
1041 .handle
= bo
->gem_handle
,
1043 .flags
= I915_MMAP_WC
,
1045 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
1048 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1049 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1053 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
1054 VG_DEFINED(map
, bo
->size
);
1056 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
1057 VG_NOACCESS(map
, bo
->size
);
1058 drm_munmap(map
, bo
->size
);
1063 DBG("brw_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1066 if (!(flags
& MAP_ASYNC
)) {
1067 bo_wait_with_stall_warning(brw
, bo
, "WC mapping");
1074 * Perform an uncached mapping via the GTT.
1076 * Write access through the GTT is not quite fully coherent. On low power
1077 * systems especially, like modern Atoms, we can observe reads from RAM before
1078 * the write via GTT has landed. A write memory barrier that flushes the Write
1079 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1080 * read after the write as the GTT write suffers a small delay through the GTT
1081 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1082 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1083 * flushes prior to execbuf submission. However, if we are not informing the
1084 * kernel about our GTT writes, it will not flush before earlier access, such
1085 * as when using the cmdparser. Similarly, we need to be careful if we should
1086 * ever issue a CPU read immediately following a GTT write.
1088 * Telling the kernel about write access also has one more important
1089 * side-effect. Upon receiving notification about the write, it cancels any
1090 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1091 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1092 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1093 * tracking is handled on the buffer exchange instead.
1096 brw_bo_map_gtt(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1098 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1100 /* Get a mapping of the buffer if we haven't before. */
1101 if (bo
->map_gtt
== NULL
) {
1102 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1104 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1106 /* Get the fake offset back... */
1107 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1109 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1110 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1115 void *map
= drm_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1116 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1117 if (map
== MAP_FAILED
) {
1118 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1119 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1123 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1124 * already intercept this mmap call. However, for consistency between
1125 * all the mmap paths, we mark the pointer as defined now and mark it
1126 * as inaccessible afterwards.
1128 VG_DEFINED(map
, bo
->size
);
1130 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1131 VG_NOACCESS(map
, bo
->size
);
1132 drm_munmap(map
, bo
->size
);
1135 assert(bo
->map_gtt
);
1137 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1140 if (!(flags
& MAP_ASYNC
)) {
1141 bo_wait_with_stall_warning(brw
, bo
, "GTT mapping");
1148 can_map_cpu(struct brw_bo
*bo
, unsigned flags
)
1150 if (bo
->cache_coherent
)
1153 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1154 * an LLC platform reads always are coherent (as they are performed via the
1155 * central system agent). It is just the writes that we need to take special
1156 * care to ensure that land in main memory and not stick in the CPU cache.
1158 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1161 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1162 * across batch flushes where the kernel will change cache domains of the
1163 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1165 * Similarly, ASYNC typically means that the buffer will be accessed via
1166 * both the CPU and the GPU simultaneously. Batches may be executed that
1167 * use the BO even while it is mapped. While OpenGL technically disallows
1168 * most drawing while non-persistent mappings are active, we may still use
1169 * the GPU for blits or other operations, causing batches to happen at
1170 * inconvenient times.
1172 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
1175 return !(flags
& MAP_WRITE
);
1179 brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1181 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1182 return brw_bo_map_gtt(brw
, bo
, flags
);
1186 if (can_map_cpu(bo
, flags
))
1187 map
= brw_bo_map_cpu(brw
, bo
, flags
);
1189 map
= brw_bo_map_wc(brw
, bo
, flags
);
1191 /* Allow the attempt to fail by falling back to the GTT where necessary.
1193 * Not every buffer can be mmaped directly using the CPU (or WC), for
1194 * example buffers that wrap stolen memory or are imported from other
1195 * devices. For those, we have little choice but to use a GTT mmapping.
1196 * However, if we use a slow GTT mmapping for reads where we expected fast
1197 * access, that order of magnitude difference in throughput will be clearly
1198 * expressed by angry users.
1200 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1202 if (!map
&& !(flags
& MAP_RAW
)) {
1204 perf_debug("Fallback GTT mapping for %s with access flags %x\n",
1207 map
= brw_bo_map_gtt(brw
, bo
, flags
);
1214 brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
1215 uint64_t size
, const void *data
)
1217 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1219 struct drm_i915_gem_pwrite pwrite
= {
1220 .handle
= bo
->gem_handle
,
1223 .data_ptr
= (uint64_t) (uintptr_t) data
,
1226 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
1229 DBG("%s:%d: Error writing data to buffer %d: "
1230 "(%"PRIu64
" %"PRIu64
") %s .\n",
1231 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
1237 /** Waits for all GPU rendering with the object to have completed. */
1239 brw_bo_wait_rendering(struct brw_bo
*bo
)
1241 /* We require a kernel recent enough for WAIT_IOCTL support.
1242 * See intel_init_bufmgr()
1244 brw_bo_wait(bo
, -1);
1248 * Waits on a BO for the given amount of time.
1250 * @bo: buffer object to wait for
1251 * @timeout_ns: amount of time to wait in nanoseconds.
1252 * If value is less than 0, an infinite wait will occur.
1254 * Returns 0 if the wait was successful ie. the last batch referencing the
1255 * object has completed within the allotted time. Otherwise some negative return
1256 * value describes the error. Of particular interest is -ETIME when the wait has
1257 * failed to yield the desired result.
1259 * Similar to brw_bo_wait_rendering except a timeout parameter allows
1260 * the operation to give up after a certain amount of time. Another subtle
1261 * difference is the internal locking semantics are different (this variant does
1262 * not hold the lock for the duration of the wait). This makes the wait subject
1263 * to a larger userspace race window.
1265 * The implementation shall wait until the object is no longer actively
1266 * referenced within a batch buffer at the time of the call. The wait will
1267 * not guarantee that the buffer is re-issued via another thread, or an flinked
1268 * handle. Userspace must make sure this race does not occur if such precision
1271 * Note that some kernels have broken the inifite wait for negative values
1272 * promise, upgrade to latest stable kernels if this is the case.
1275 brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
)
1277 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1279 /* If we know it's idle, don't bother with the kernel round trip */
1280 if (bo
->idle
&& !bo
->external
)
1283 struct drm_i915_gem_wait wait
= {
1284 .bo_handle
= bo
->gem_handle
,
1285 .timeout_ns
= timeout_ns
,
1287 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1297 brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
)
1299 mtx_destroy(&bufmgr
->lock
);
1301 /* Free any cached buffer objects we were going to reuse */
1302 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1303 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1305 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
1306 list_del(&bo
->head
);
1311 if (brw_using_softpin(bufmgr
)) {
1312 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++) {
1313 util_dynarray_fini(&bucket
->vma_list
[z
]);
1318 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1319 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1321 if (brw_using_softpin(bufmgr
)) {
1322 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++) {
1323 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1331 bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
1334 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1335 struct drm_i915_gem_set_tiling set_tiling
;
1338 if (bo
->global_name
== 0 &&
1339 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1342 memset(&set_tiling
, 0, sizeof(set_tiling
));
1344 /* set_tiling is slightly broken and overwrites the
1345 * input on the error path, so we have to open code
1348 set_tiling
.handle
= bo
->gem_handle
;
1349 set_tiling
.tiling_mode
= tiling_mode
;
1350 set_tiling
.stride
= stride
;
1352 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1353 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1357 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1358 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1359 bo
->stride
= set_tiling
.stride
;
1364 brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
1365 uint32_t *swizzle_mode
)
1367 *tiling_mode
= bo
->tiling_mode
;
1368 *swizzle_mode
= bo
->swizzle_mode
;
1372 static struct brw_bo
*
1373 brw_bo_gem_create_from_prime_internal(struct brw_bufmgr
*bufmgr
, int prime_fd
,
1374 int tiling_mode
, uint32_t stride
)
1379 mtx_lock(&bufmgr
->lock
);
1380 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1382 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
1384 mtx_unlock(&bufmgr
->lock
);
1389 * See if the kernel has already returned this buffer to us. Just as
1390 * for named buffers, we must not create two bo's pointing at the same
1393 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1395 brw_bo_reference(bo
);
1399 bo
= calloc(1, sizeof(*bo
));
1403 p_atomic_set(&bo
->refcount
, 1);
1405 /* Determine size of bo. The fd-to-handle ioctl really should
1406 * return the size, but it doesn't. If we have kernel 3.12 or
1407 * later, we can lseek on the prime fd to get the size. Older
1408 * kernels will just fail, in which case we fall back to the
1409 * provided (estimated or guess size). */
1410 ret
= lseek(prime_fd
, 0, SEEK_END
);
1414 bo
->bufmgr
= bufmgr
;
1416 bo
->gem_handle
= handle
;
1417 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1420 bo
->reusable
= false;
1421 bo
->external
= true;
1422 bo
->kflags
= bufmgr
->initial_kflags
;
1424 if (bo
->kflags
& EXEC_OBJECT_PINNED
) {
1425 assert(bo
->size
> 0);
1426 bo
->gtt_offset
= vma_alloc(bufmgr
, BRW_MEMZONE_OTHER
, bo
->size
, 1);
1429 if (tiling_mode
< 0) {
1430 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1431 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1434 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1435 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1436 /* XXX stride is unknown */
1438 bo_set_tiling_internal(bo
, tiling_mode
, stride
);
1442 mtx_unlock(&bufmgr
->lock
);
1447 mtx_unlock(&bufmgr
->lock
);
1452 brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
, int prime_fd
)
1454 return brw_bo_gem_create_from_prime_internal(bufmgr
, prime_fd
, -1, 0);
1458 brw_bo_gem_create_from_prime_tiled(struct brw_bufmgr
*bufmgr
, int prime_fd
,
1459 uint32_t tiling_mode
, uint32_t stride
)
1461 assert(tiling_mode
== I915_TILING_NONE
||
1462 tiling_mode
== I915_TILING_X
||
1463 tiling_mode
== I915_TILING_Y
);
1465 return brw_bo_gem_create_from_prime_internal(bufmgr
, prime_fd
,
1466 tiling_mode
, stride
);
1470 brw_bo_make_external(struct brw_bo
*bo
)
1472 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1474 if (!bo
->external
) {
1475 mtx_lock(&bufmgr
->lock
);
1476 if (!bo
->external
) {
1477 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1478 bo
->external
= true;
1480 mtx_unlock(&bufmgr
->lock
);
1485 brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
)
1487 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1489 brw_bo_make_external(bo
);
1491 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1492 DRM_CLOEXEC
, prime_fd
) != 0)
1495 bo
->reusable
= false;
1501 brw_bo_export_gem_handle(struct brw_bo
*bo
)
1503 brw_bo_make_external(bo
);
1505 return bo
->gem_handle
;
1509 brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
)
1511 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1513 if (!bo
->global_name
) {
1514 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1516 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1519 brw_bo_make_external(bo
);
1520 mtx_lock(&bufmgr
->lock
);
1521 if (!bo
->global_name
) {
1522 bo
->global_name
= flink
.name
;
1523 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1525 mtx_unlock(&bufmgr
->lock
);
1527 bo
->reusable
= false;
1530 *name
= bo
->global_name
;
1535 * Enables unlimited caching of buffer objects for reuse.
1537 * This is potentially very memory expensive, as the cache at each bucket
1538 * size is only bounded by how many buffers of that size we've managed to have
1539 * in flight at once.
1542 brw_bufmgr_enable_reuse(struct brw_bufmgr
*bufmgr
)
1544 bufmgr
->bo_reuse
= true;
1548 add_bucket(struct brw_bufmgr
*bufmgr
, int size
)
1550 unsigned int i
= bufmgr
->num_buckets
;
1552 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1554 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1555 if (brw_using_softpin(bufmgr
)) {
1556 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++)
1557 util_dynarray_init(&bufmgr
->cache_bucket
[i
].vma_list
[z
], NULL
);
1559 bufmgr
->cache_bucket
[i
].size
= size
;
1560 bufmgr
->num_buckets
++;
1562 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1563 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1564 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1568 init_cache_buckets(struct brw_bufmgr
*bufmgr
)
1570 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1572 /* OK, so power of two buckets was too wasteful of memory.
1573 * Give 3 other sizes between each power of two, to hopefully
1574 * cover things accurately enough. (The alternative is
1575 * probably to just go for exact matching of sizes, and assume
1576 * that for things like composited window resize the tiled
1577 * width/height alignment and rounding of sizes to pages will
1578 * get us useful cache hit rates anyway)
1580 add_bucket(bufmgr
, PAGE_SIZE
);
1581 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1582 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1584 /* Initialize the linked lists for BO reuse cache. */
1585 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1586 add_bucket(bufmgr
, size
);
1588 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1589 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1590 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1595 brw_create_hw_context(struct brw_bufmgr
*bufmgr
)
1597 struct drm_i915_gem_context_create create
= { };
1598 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1600 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1604 return create
.ctx_id
;
1608 brw_hw_context_set_priority(struct brw_bufmgr
*bufmgr
,
1612 struct drm_i915_gem_context_param p
= {
1614 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1620 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1627 brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
)
1629 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1632 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1633 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1639 brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1641 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1642 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1644 *result
= reg_read
.val
;
1649 gem_param(int fd
, int name
)
1651 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1653 struct drm_i915_getparam gp
= { .param
= name
, .value
= &v
};
1654 if (drmIoctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1661 gem_context_getparam(int fd
, uint32_t context
, uint64_t param
, uint64_t *value
)
1663 struct drm_i915_gem_context_param gp
= {
1668 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &gp
))
1677 brw_using_softpin(struct brw_bufmgr
*bufmgr
)
1679 return bufmgr
->initial_kflags
& EXEC_OBJECT_PINNED
;
1683 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1684 * and manage map buffer objections.
1686 * \param fd File descriptor of the opened DRM device.
1689 brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
)
1691 struct brw_bufmgr
*bufmgr
;
1693 bufmgr
= calloc(1, sizeof(*bufmgr
));
1697 /* Handles to buffer objects belong to the device fd and are not
1698 * reference counted by the kernel. If the same fd is used by
1699 * multiple parties (threads sharing the same screen bufmgr, or
1700 * even worse the same device fd passed to multiple libraries)
1701 * ownership of those handles is shared by those independent parties.
1703 * Don't do this! Ensure that each library/bufmgr has its own device
1704 * fd so that its namespace does not clash with another.
1708 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1714 if (gem_context_getparam(fd
, 0, I915_CONTEXT_PARAM_GTT_SIZE
, >t_size
))
1717 bufmgr
->has_llc
= devinfo
->has_llc
;
1718 bufmgr
->has_mmap_wc
= gem_param(fd
, I915_PARAM_MMAP_VERSION
) > 0;
1720 const uint64_t _4GB
= 4ull << 30;
1722 if (devinfo
->gen
>= 8 && gtt_size
> _4GB
) {
1723 bufmgr
->initial_kflags
|= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
1725 /* Allocate VMA in userspace if we have softpin and full PPGTT. */
1726 if (gem_param(fd
, I915_PARAM_HAS_EXEC_SOFTPIN
) > 0 &&
1727 gem_param(fd
, I915_PARAM_HAS_ALIASING_PPGTT
) > 1) {
1728 bufmgr
->initial_kflags
|= EXEC_OBJECT_PINNED
;
1730 util_vma_heap_init(&bufmgr
->vma_allocator
[BRW_MEMZONE_LOW_4G
],
1732 util_vma_heap_init(&bufmgr
->vma_allocator
[BRW_MEMZONE_OTHER
],
1733 1 * _4GB
, gtt_size
- 1 * _4GB
);
1734 } else if (devinfo
->gen
>= 10) {
1735 /* Softpin landed in 4.5, but GVT used an aliasing PPGTT until
1736 * kernel commit 6b3816d69628becb7ff35978aa0751798b4a940a in
1737 * 4.14. Gen10+ GVT hasn't landed yet, so it's not actually a
1738 * problem - but extending this requirement back to earlier gens
1739 * might actually mean requiring 4.14.
1741 fprintf(stderr
, "i965 requires softpin (Kernel 4.5) on Gen10+.");
1747 init_cache_buckets(bufmgr
);
1749 bufmgr
->name_table
=
1750 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1751 bufmgr
->handle_table
=
1752 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);