1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007-2012 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
42 #include <util/u_atomic.h>
50 #include <sys/ioctl.h>
52 #include <sys/types.h>
57 #define ETIME ETIMEDOUT
59 #include "common/gen_clflush.h"
60 #include "common/gen_debug.h"
61 #include "common/gen_device_info.h"
62 #include "libdrm_macros.h"
63 #include "main/macros.h"
64 #include "util/macros.h"
65 #include "util/hash_table.h"
66 #include "util/list.h"
67 #include "brw_bufmgr.h"
68 #include "brw_context.h"
81 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
82 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
83 * leaked. All because it does not call VG(cli_free) from its
84 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
85 * and allocation, we mark it available for use upon mmapping and remove
88 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
89 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
91 #define memclear(s) memset(&s, 0, sizeof(s))
93 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
96 atomic_add_unless(int *v
, int add
, int unless
)
100 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
105 struct bo_cache_bucket
{
106 struct list_head head
;
113 pthread_mutex_t lock
;
115 /** Array of lists of cached gem objects of power-of-two sizes */
116 struct bo_cache_bucket cache_bucket
[14 * 4];
120 struct hash_table
*name_table
;
121 struct hash_table
*handle_table
;
128 static int bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
131 static void bo_free(struct brw_bo
*bo
);
134 key_hash_uint(const void *key
)
136 return _mesa_hash_data(key
, 4);
140 key_uint_equal(const void *a
, const void *b
)
142 return *((unsigned *) a
) == *((unsigned *) b
);
145 static struct brw_bo
*
146 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
148 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
149 return entry
? (struct brw_bo
*) entry
->data
: NULL
;
153 bo_tile_size(struct brw_bufmgr
*bufmgr
, uint64_t size
, uint32_t tiling
)
155 if (tiling
== I915_TILING_NONE
)
158 /* 965+ just need multiples of page size for tiling */
159 return ALIGN(size
, 4096);
163 * Round a given pitch up to the minimum required for X tiling on a
164 * given chip. We use 512 as the minimum to allow for a later tiling
168 bo_tile_pitch(struct brw_bufmgr
*bufmgr
, uint32_t pitch
, uint32_t tiling
)
170 unsigned long tile_width
;
172 /* If untiled, then just align it so that we can do rendering
173 * to it with the 3D engine.
175 if (tiling
== I915_TILING_NONE
)
176 return ALIGN(pitch
, 64);
178 if (tiling
== I915_TILING_X
)
183 /* 965 is flexible */
184 return ALIGN(pitch
, tile_width
);
187 static struct bo_cache_bucket
*
188 bucket_for_size(struct brw_bufmgr
*bufmgr
, uint64_t size
)
192 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
193 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
194 if (bucket
->size
>= size
) {
203 brw_bo_reference(struct brw_bo
*bo
)
205 p_atomic_inc(&bo
->refcount
);
209 brw_bo_busy(struct brw_bo
*bo
)
211 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
212 struct drm_i915_gem_busy busy
;
216 busy
.handle
= bo
->gem_handle
;
218 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
220 bo
->idle
= !busy
.busy
;
227 brw_bo_madvise(struct brw_bo
*bo
, int state
)
229 struct drm_i915_gem_madvise madv
;
232 madv
.handle
= bo
->gem_handle
;
235 drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
237 return madv
.retained
;
240 /* drop the oldest entries that have been purged by the kernel */
242 brw_bo_cache_purge_bucket(struct brw_bufmgr
*bufmgr
,
243 struct bo_cache_bucket
*bucket
)
245 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
246 if (brw_bo_madvise(bo
, I915_MADV_DONTNEED
))
254 static struct brw_bo
*
255 bo_alloc_internal(struct brw_bufmgr
*bufmgr
,
259 uint32_t tiling_mode
,
260 uint32_t stride
, uint64_t alignment
)
263 unsigned int page_size
= getpagesize();
265 struct bo_cache_bucket
*bucket
;
266 bool alloc_from_cache
;
268 bool for_render
= false;
271 if (flags
& BO_ALLOC_FOR_RENDER
)
274 if (flags
& BO_ALLOC_ZEROED
)
277 /* FOR_RENDER really means "I'm ok with a busy BO". This doesn't really
278 * jive with ZEROED as we have to wait for it to be idle before we can
279 * memset. Just disallow that combination.
281 assert(!(for_render
&& zeroed
));
283 /* Round the allocated size up to a power of two number of pages. */
284 bucket
= bucket_for_size(bufmgr
, size
);
286 /* If we don't have caching at this size, don't actually round the
289 if (bucket
== NULL
) {
291 if (bo_size
< page_size
)
294 bo_size
= bucket
->size
;
297 pthread_mutex_lock(&bufmgr
->lock
);
298 /* Get a buffer out of the cache if available */
300 alloc_from_cache
= false;
301 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
302 if (for_render
&& !zeroed
) {
303 /* Allocate new render-target BOs from the tail (MRU)
304 * of the list, as it will likely be hot in the GPU
305 * cache and in the aperture for us. If the caller
306 * asked us to zero the buffer, we don't want this
307 * because we are going to mmap it.
309 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.prev
, head
);
311 alloc_from_cache
= true;
312 bo
->align
= alignment
;
314 assert(alignment
== 0);
315 /* For non-render-target BOs (where we're probably
316 * going to map it first thing in order to fill it
317 * with data), check if the last BO in the cache is
318 * unbusy, and only reuse in that case. Otherwise,
319 * allocating a new buffer is probably faster than
320 * waiting for the GPU to finish.
322 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.next
, head
);
323 if (!brw_bo_busy(bo
)) {
324 alloc_from_cache
= true;
329 if (alloc_from_cache
) {
330 if (!brw_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
332 brw_bo_cache_purge_bucket(bufmgr
, bucket
);
336 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
342 void *map
= brw_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
347 memset(map
, 0, bo_size
);
352 if (!alloc_from_cache
) {
353 struct drm_i915_gem_create create
;
355 bo
= calloc(1, sizeof(*bo
));
363 create
.size
= bo_size
;
365 /* All new BOs we get from the kernel are zeroed, so we don't need to
366 * worry about that here.
368 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
374 bo
->gem_handle
= create
.handle
;
375 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
378 bo
->align
= alignment
;
380 bo
->tiling_mode
= I915_TILING_NONE
;
381 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
384 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
387 /* Calling set_domain() will allocate pages for the BO outside of the
388 * struct mutex lock in the kernel, which is more efficient than waiting
389 * to create them during the first execbuf that uses the BO.
391 struct drm_i915_gem_set_domain sd
= {
392 .handle
= bo
->gem_handle
,
393 .read_domains
= I915_GEM_DOMAIN_CPU
,
397 if (drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
402 p_atomic_set(&bo
->refcount
, 1);
404 bo
->cache_coherent
= bufmgr
->has_llc
;
406 pthread_mutex_unlock(&bufmgr
->lock
);
408 DBG("bo_create: buf %d (%s) %ldb\n", bo
->gem_handle
, bo
->name
, size
);
415 pthread_mutex_unlock(&bufmgr
->lock
);
420 brw_bo_alloc(struct brw_bufmgr
*bufmgr
,
421 const char *name
, uint64_t size
, uint64_t alignment
)
423 return bo_alloc_internal(bufmgr
, name
, size
, 0, I915_TILING_NONE
, 0, 0);
427 brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
, const char *name
,
428 uint64_t size
, uint32_t tiling_mode
, uint32_t pitch
,
431 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling_mode
, pitch
, 0);
435 brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
, const char *name
,
436 int x
, int y
, int cpp
, uint32_t tiling
,
437 uint32_t *pitch
, unsigned flags
)
441 unsigned long aligned_y
, height_alignment
;
443 /* If we're tiled, our allocations are in 8 or 32-row blocks,
444 * so failure to align our height means that we won't allocate
447 * If we're untiled, we still have to align to 2 rows high
448 * because the data port accesses 2x2 blocks even if the
449 * bottom row isn't to be rendered, so failure to align means
450 * we could walk off the end of the GTT and fault. This is
451 * documented on 965, and may be the case on older chipsets
452 * too so we try to be careful.
455 height_alignment
= 2;
457 if (tiling
== I915_TILING_X
)
458 height_alignment
= 8;
459 else if (tiling
== I915_TILING_Y
)
460 height_alignment
= 32;
461 aligned_y
= ALIGN(y
, height_alignment
);
464 stride
= bo_tile_pitch(bufmgr
, stride
, tiling
);
465 size
= stride
* aligned_y
;
466 size
= bo_tile_size(bufmgr
, size
, tiling
);
469 if (tiling
== I915_TILING_NONE
)
472 return bo_alloc_internal(bufmgr
, name
, size
, flags
, tiling
, stride
, 0);
476 * Returns a brw_bo wrapping the given buffer object handle.
478 * This can be used when one application needs to pass a buffer object
482 brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
483 const char *name
, unsigned int handle
)
487 struct drm_gem_open open_arg
;
488 struct drm_i915_gem_get_tiling get_tiling
;
490 /* At the moment most applications only have a few named bo.
491 * For instance, in a DRI client only the render buffers passed
492 * between X and the client are named. And since X returns the
493 * alternating names for the front/back buffer a linear search
494 * provides a sufficiently fast match.
496 pthread_mutex_lock(&bufmgr
->lock
);
497 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
499 brw_bo_reference(bo
);
504 open_arg
.name
= handle
;
505 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
507 DBG("Couldn't reference %s handle 0x%08x: %s\n",
508 name
, handle
, strerror(errno
));
512 /* Now see if someone has used a prime handle to get this
513 * object from the kernel before by looking through the list
514 * again for a matching gem_handle
516 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
518 brw_bo_reference(bo
);
522 bo
= calloc(1, sizeof(*bo
));
526 p_atomic_set(&bo
->refcount
, 1);
528 bo
->size
= open_arg
.size
;
531 bo
->gem_handle
= open_arg
.handle
;
533 bo
->global_name
= handle
;
534 bo
->reusable
= false;
537 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
538 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
540 memclear(get_tiling
);
541 get_tiling
.handle
= bo
->gem_handle
;
542 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
546 bo
->tiling_mode
= get_tiling
.tiling_mode
;
547 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
548 /* XXX stride is unknown */
549 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
552 pthread_mutex_unlock(&bufmgr
->lock
);
557 pthread_mutex_unlock(&bufmgr
->lock
);
562 bo_free(struct brw_bo
*bo
)
564 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
565 struct drm_gem_close close
;
566 struct hash_entry
*entry
;
570 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
571 drm_munmap(bo
->map_cpu
, bo
->size
);
574 VG_NOACCESS(bo
->map_wc
, bo
->size
);
575 drm_munmap(bo
->map_wc
, bo
->size
);
578 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
579 drm_munmap(bo
->map_gtt
, bo
->size
);
582 if (bo
->global_name
) {
583 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
584 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
586 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
587 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
589 /* Close this object */
591 close
.handle
= bo
->gem_handle
;
592 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
594 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
595 bo
->gem_handle
, bo
->name
, strerror(errno
));
600 /** Frees all cached buffers significantly older than @time. */
602 cleanup_bo_cache(struct brw_bufmgr
*bufmgr
, time_t time
)
606 if (bufmgr
->time
== time
)
609 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
610 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
612 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
613 if (time
- bo
->free_time
<= 1)
626 bo_unreference_final(struct brw_bo
*bo
, time_t time
)
628 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
629 struct bo_cache_bucket
*bucket
;
631 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
633 bucket
= bucket_for_size(bufmgr
, bo
->size
);
634 /* Put the buffer into our internal cache for reuse if we can. */
635 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
636 brw_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
637 bo
->free_time
= time
;
642 list_addtail(&bo
->head
, &bucket
->head
);
649 brw_bo_unreference(struct brw_bo
*bo
)
654 assert(p_atomic_read(&bo
->refcount
) > 0);
656 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
657 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
658 struct timespec time
;
660 clock_gettime(CLOCK_MONOTONIC
, &time
);
662 pthread_mutex_lock(&bufmgr
->lock
);
664 if (p_atomic_dec_zero(&bo
->refcount
)) {
665 bo_unreference_final(bo
, time
.tv_sec
);
666 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
669 pthread_mutex_unlock(&bufmgr
->lock
);
674 bo_wait_with_stall_warning(struct brw_context
*brw
,
678 double elapsed
= unlikely(brw
&& brw
->perf_debug
) ? -get_time() : 0.0;
680 brw_bo_wait_rendering(bo
);
682 if (unlikely(brw
&& brw
->perf_debug
)) {
683 elapsed
+= get_time();
684 if (elapsed
> 1e-5) /* 0.01ms */
685 perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n",
686 action
, bo
->name
, elapsed
* 1000);
691 print_flags(unsigned flags
)
693 if (flags
& MAP_READ
)
695 if (flags
& MAP_WRITE
)
697 if (flags
& MAP_ASYNC
)
699 if (flags
& MAP_PERSISTENT
)
701 if (flags
& MAP_COHERENT
)
709 brw_bo_map_cpu(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
711 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
713 /* We disallow CPU maps for writing to non-coherent buffers, as the
714 * CPU map can become invalidated when a batch is flushed out, which
715 * can happen at unpredictable times. You should use WC maps instead.
717 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
720 struct drm_i915_gem_mmap mmap_arg
;
723 DBG("brw_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
726 mmap_arg
.handle
= bo
->gem_handle
;
727 mmap_arg
.size
= bo
->size
;
728 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
731 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
732 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
735 map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
736 VG_DEFINED(map
, bo
->size
);
738 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
739 VG_NOACCESS(map
, bo
->size
);
740 drm_munmap(map
, bo
->size
);
745 DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
749 if (!(flags
& MAP_ASYNC
)) {
750 bo_wait_with_stall_warning(brw
, bo
, "CPU mapping");
753 if (!bo
->cache_coherent
) {
754 /* If we're reusing an existing CPU mapping, the CPU caches may
755 * contain stale data from the last time we read from that mapping.
756 * (With the BO cache, it might even be data from a previous buffer!)
757 * Even if it's a brand new mapping, the kernel may have zeroed the
758 * buffer via CPU writes.
760 * We need to invalidate those cachelines so that we see the latest
761 * contents, and so long as we only read from the CPU mmap we do not
762 * need to write those cachelines back afterwards.
764 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
771 brw_bo_map_wc(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
773 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
775 if (!bufmgr
->has_mmap_wc
)
779 struct drm_i915_gem_mmap mmap_arg
;
782 DBG("brw_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
785 mmap_arg
.handle
= bo
->gem_handle
;
786 mmap_arg
.size
= bo
->size
;
787 mmap_arg
.flags
= I915_MMAP_WC
;
788 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
791 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
792 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
796 map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
797 VG_DEFINED(map
, bo
->size
);
799 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
800 VG_NOACCESS(map
, bo
->size
);
801 drm_munmap(map
, bo
->size
);
806 DBG("brw_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
809 if (!(flags
& MAP_ASYNC
)) {
810 bo_wait_with_stall_warning(brw
, bo
, "WC mapping");
817 brw_bo_map_gtt(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
819 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
821 /* Get a mapping of the buffer if we haven't before. */
822 if (bo
->map_gtt
== NULL
) {
823 struct drm_i915_gem_mmap_gtt mmap_arg
;
826 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
829 mmap_arg
.handle
= bo
->gem_handle
;
831 /* Get the fake offset back... */
832 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
834 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
835 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
840 map
= drm_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
841 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
842 if (map
== MAP_FAILED
) {
843 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
844 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
848 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
849 * already intercept this mmap call. However, for consistency between
850 * all the mmap paths, we mark the pointer as defined now and mark it
851 * as inaccessible afterwards.
853 VG_DEFINED(map
, bo
->size
);
855 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
856 VG_NOACCESS(map
, bo
->size
);
857 drm_munmap(map
, bo
->size
);
862 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
865 if (!(flags
& MAP_ASYNC
)) {
866 bo_wait_with_stall_warning(brw
, bo
, "GTT mapping");
873 can_map_cpu(struct brw_bo
*bo
, unsigned flags
)
875 if (bo
->cache_coherent
)
878 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
879 * across batch flushes where the kernel will change cache domains of the
880 * bo, invalidating continued access to the CPU mmap on non-LLC device.
882 * Similarly, ASYNC typically means that the buffer will be accessed via
883 * both the CPU and the GPU simultaneously. Batches may be executed that
884 * use the BO even while it is mapped. While OpenGL technically disallows
885 * most drawing while non-persistent mappings are active, we may still use
886 * the GPU for blits or other operations, causing batches to happen at
887 * inconvenient times.
889 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
892 return !(flags
& MAP_WRITE
);
896 brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
898 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
899 return brw_bo_map_gtt(brw
, bo
, flags
);
903 if (can_map_cpu(bo
, flags
))
904 map
= brw_bo_map_cpu(brw
, bo
, flags
);
906 map
= brw_bo_map_wc(brw
, bo
, flags
);
908 /* Allow the attempt to fail by falling back to the GTT where necessary.
910 * Not every buffer can be mmaped directly using the CPU (or WC), for
911 * example buffers that wrap stolen memory or are imported from other
912 * devices. For those, we have little choice but to use a GTT mmapping.
913 * However, if we use a slow GTT mmapping for reads where we expected fast
914 * access, that order of magnitude difference in throughput will be clearly
915 * expressed by angry users.
917 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
919 if (!map
&& !(flags
& MAP_RAW
)) {
920 perf_debug("Fallback GTT mapping for %s with access flags %x\n",
922 map
= brw_bo_map_gtt(brw
, bo
, flags
);
929 brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
930 uint64_t size
, const void *data
)
932 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
933 struct drm_i915_gem_pwrite pwrite
;
937 pwrite
.handle
= bo
->gem_handle
;
938 pwrite
.offset
= offset
;
940 pwrite
.data_ptr
= (uint64_t) (uintptr_t) data
;
941 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
944 DBG("%s:%d: Error writing data to buffer %d: "
945 "(%"PRIu64
" %"PRIu64
") %s .\n",
946 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
952 /** Waits for all GPU rendering with the object to have completed. */
954 brw_bo_wait_rendering(struct brw_bo
*bo
)
956 /* We require a kernel recent enough for WAIT_IOCTL support.
957 * See intel_init_bufmgr()
963 * Waits on a BO for the given amount of time.
965 * @bo: buffer object to wait for
966 * @timeout_ns: amount of time to wait in nanoseconds.
967 * If value is less than 0, an infinite wait will occur.
969 * Returns 0 if the wait was successful ie. the last batch referencing the
970 * object has completed within the allotted time. Otherwise some negative return
971 * value describes the error. Of particular interest is -ETIME when the wait has
972 * failed to yield the desired result.
974 * Similar to brw_bo_wait_rendering except a timeout parameter allows
975 * the operation to give up after a certain amount of time. Another subtle
976 * difference is the internal locking semantics are different (this variant does
977 * not hold the lock for the duration of the wait). This makes the wait subject
978 * to a larger userspace race window.
980 * The implementation shall wait until the object is no longer actively
981 * referenced within a batch buffer at the time of the call. The wait will
982 * not guarantee that the buffer is re-issued via another thread, or an flinked
983 * handle. Userspace must make sure this race does not occur if such precision
986 * Note that some kernels have broken the inifite wait for negative values
987 * promise, upgrade to latest stable kernels if this is the case.
990 brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
)
992 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
993 struct drm_i915_gem_wait wait
;
996 /* If we know it's idle, don't bother with the kernel round trip */
997 if (bo
->idle
&& !bo
->external
)
1001 wait
.bo_handle
= bo
->gem_handle
;
1002 wait
.timeout_ns
= timeout_ns
;
1003 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1011 brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
)
1013 pthread_mutex_destroy(&bufmgr
->lock
);
1015 /* Free any cached buffer objects we were going to reuse */
1016 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1017 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1019 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
1020 list_del(&bo
->head
);
1026 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1027 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1033 bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
1036 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1037 struct drm_i915_gem_set_tiling set_tiling
;
1040 if (bo
->global_name
== 0 &&
1041 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1044 memset(&set_tiling
, 0, sizeof(set_tiling
));
1046 /* set_tiling is slightly broken and overwrites the
1047 * input on the error path, so we have to open code
1050 set_tiling
.handle
= bo
->gem_handle
;
1051 set_tiling
.tiling_mode
= tiling_mode
;
1052 set_tiling
.stride
= stride
;
1054 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1055 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1059 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1060 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1061 bo
->stride
= set_tiling
.stride
;
1066 brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
1067 uint32_t *swizzle_mode
)
1069 *tiling_mode
= bo
->tiling_mode
;
1070 *swizzle_mode
= bo
->swizzle_mode
;
1075 brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
, int prime_fd
)
1080 struct drm_i915_gem_get_tiling get_tiling
;
1082 pthread_mutex_lock(&bufmgr
->lock
);
1083 ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1085 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
1087 pthread_mutex_unlock(&bufmgr
->lock
);
1092 * See if the kernel has already returned this buffer to us. Just as
1093 * for named buffers, we must not create two bo's pointing at the same
1096 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1098 brw_bo_reference(bo
);
1102 bo
= calloc(1, sizeof(*bo
));
1106 p_atomic_set(&bo
->refcount
, 1);
1108 /* Determine size of bo. The fd-to-handle ioctl really should
1109 * return the size, but it doesn't. If we have kernel 3.12 or
1110 * later, we can lseek on the prime fd to get the size. Older
1111 * kernels will just fail, in which case we fall back to the
1112 * provided (estimated or guess size). */
1113 ret
= lseek(prime_fd
, 0, SEEK_END
);
1117 bo
->bufmgr
= bufmgr
;
1119 bo
->gem_handle
= handle
;
1120 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1123 bo
->reusable
= false;
1124 bo
->external
= true;
1126 memclear(get_tiling
);
1127 get_tiling
.handle
= bo
->gem_handle
;
1128 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1131 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1132 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1133 /* XXX stride is unknown */
1136 pthread_mutex_unlock(&bufmgr
->lock
);
1141 pthread_mutex_unlock(&bufmgr
->lock
);
1146 brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
)
1148 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1150 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1151 DRM_CLOEXEC
, prime_fd
) != 0)
1154 bo
->reusable
= false;
1155 bo
->external
= true;
1161 brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
)
1163 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1165 if (!bo
->global_name
) {
1166 struct drm_gem_flink flink
;
1169 flink
.handle
= bo
->gem_handle
;
1170 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1173 pthread_mutex_lock(&bufmgr
->lock
);
1174 if (!bo
->global_name
) {
1175 bo
->global_name
= flink
.name
;
1176 bo
->reusable
= false;
1177 bo
->external
= true;
1179 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1181 pthread_mutex_unlock(&bufmgr
->lock
);
1184 *name
= bo
->global_name
;
1189 * Enables unlimited caching of buffer objects for reuse.
1191 * This is potentially very memory expensive, as the cache at each bucket
1192 * size is only bounded by how many buffers of that size we've managed to have
1193 * in flight at once.
1196 brw_bufmgr_enable_reuse(struct brw_bufmgr
*bufmgr
)
1198 bufmgr
->bo_reuse
= true;
1202 add_bucket(struct brw_bufmgr
*bufmgr
, int size
)
1204 unsigned int i
= bufmgr
->num_buckets
;
1206 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1208 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1209 bufmgr
->cache_bucket
[i
].size
= size
;
1210 bufmgr
->num_buckets
++;
1214 init_cache_buckets(struct brw_bufmgr
*bufmgr
)
1216 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1218 /* OK, so power of two buckets was too wasteful of memory.
1219 * Give 3 other sizes between each power of two, to hopefully
1220 * cover things accurately enough. (The alternative is
1221 * probably to just go for exact matching of sizes, and assume
1222 * that for things like composited window resize the tiled
1223 * width/height alignment and rounding of sizes to pages will
1224 * get us useful cache hit rates anyway)
1226 add_bucket(bufmgr
, 4096);
1227 add_bucket(bufmgr
, 4096 * 2);
1228 add_bucket(bufmgr
, 4096 * 3);
1230 /* Initialize the linked lists for BO reuse cache. */
1231 for (size
= 4 * 4096; size
<= cache_max_size
; size
*= 2) {
1232 add_bucket(bufmgr
, size
);
1234 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1235 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1236 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1241 brw_create_hw_context(struct brw_bufmgr
*bufmgr
)
1243 struct drm_i915_gem_context_create create
;
1247 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1249 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1253 return create
.ctx_id
;
1257 brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
)
1259 struct drm_i915_gem_context_destroy d
= {.ctx_id
= ctx_id
};
1262 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1263 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1269 brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1271 struct drm_i915_reg_read reg_read
;
1275 reg_read
.offset
= offset
;
1277 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1279 *result
= reg_read
.val
;
1284 gem_param(int fd
, int name
)
1286 drm_i915_getparam_t gp
;
1287 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1289 memset(&gp
, 0, sizeof(gp
));
1292 if (drmIoctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1299 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1300 * and manage map buffer objections.
1302 * \param fd File descriptor of the opened DRM device.
1305 brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, int batch_size
)
1307 struct brw_bufmgr
*bufmgr
;
1309 bufmgr
= calloc(1, sizeof(*bufmgr
));
1313 /* Handles to buffer objects belong to the device fd and are not
1314 * reference counted by the kernel. If the same fd is used by
1315 * multiple parties (threads sharing the same screen bufmgr, or
1316 * even worse the same device fd passed to multiple libraries)
1317 * ownership of those handles is shared by those independent parties.
1319 * Don't do this! Ensure that each library/bufmgr has its own device
1320 * fd so that its namespace does not clash with another.
1324 if (pthread_mutex_init(&bufmgr
->lock
, NULL
) != 0) {
1329 bufmgr
->has_llc
= devinfo
->has_llc
;
1330 bufmgr
->has_mmap_wc
= gem_param(fd
, I915_PARAM_MMAP_VERSION
) > 0;
1332 init_cache_buckets(bufmgr
);
1334 bufmgr
->name_table
=
1335 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1336 bufmgr
->handle_table
=
1337 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);