005ff19798e88234db49af9803b8c4507b0a3cb6
2 * Copyright © 2008-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
31 * Public definitions of Intel-specific bufmgr functions.
34 #ifndef INTEL_BUFMGR_H
35 #define INTEL_BUFMGR_H
40 #include "util/u_atomic.h"
41 #include "util/list.h"
43 #if defined(__cplusplus)
47 struct gen_device_info
;
52 * Size in bytes of the buffer object.
54 * The size may be larger than the size originally requested for the
55 * allocation, such as being aligned to page size.
60 * Alignment requirement for object
62 * Used for GTT mapping & pinning the object.
66 /** Buffer manager context associated with this buffer object */
67 struct brw_bufmgr
*bufmgr
;
69 /** The GEM handle for this buffer object. */
73 * Offset of the buffer inside the Graphics Translation Table.
75 * This is effectively our GPU address for the buffer and we use it
76 * as our base for all state pointers into the buffer. However, since the
77 * kernel may be forced to move it around during the course of the
78 * buffer's lifetime, we can only know where the buffer was on the last
79 * execbuf. We presume, and are usually right, that the buffer will not
80 * move and so we use that last offset for the next batch and by doing
81 * so we can avoid having the kernel perform a relocation fixup pass as
82 * our pointers inside the batch will be using the correct base offset.
84 * Since we do use it as a base address for the next batch of pointers,
85 * the kernel treats our offset as a request, and if possible will
86 * arrange the buffer to placed at that address (trying to balance
87 * the cost of buffer migration versus the cost of performing
88 * relocations). Furthermore, we can force the kernel to place the buffer,
89 * or report a failure if we specified a conflicting offset, at our chosen
90 * offset by specifying EXEC_OBJECT_PINNED.
92 * Note the GTT may be either per context, or shared globally across the
93 * system. On a shared system, our buffers have to contend for address
94 * space with both aperture mappings and framebuffers and so are more
95 * likely to be moved. On a full ppGTT system, each batch exists in its
96 * own GTT, and so each buffer may have their own offset within each
102 * The validation list index for this buffer, or -1 when not in a batch.
103 * Note that a single buffer may be in multiple batches (contexts), and
104 * this is a global field, which refers to the last batch using the BO.
105 * It should not be considered authoritative, but can be used to avoid a
106 * linear walk of the validation list in the common case by guessing that
107 * exec_bos[bo->index] == bo and confirming whether that's the case.
112 * Boolean of whether the GPU is definitely not accessing the buffer.
114 * This is only valid when reusable, since non-reusable
115 * buffers are those that have been shared with other
116 * processes, so we don't know their state.
126 * Kenel-assigned global name for this object
128 * List contains both flink named and prime fd'd objects
130 unsigned int global_name
;
133 * Current tiling mode
135 uint32_t tiling_mode
;
136 uint32_t swizzle_mode
;
141 /** Mapped address for the buffer, saved across map/unmap cycles */
143 /** GTT virtual address for the buffer, saved across map/unmap cycles */
145 /** WC CPU address for the buffer, saved across map/unmap cycles */
149 struct list_head head
;
152 * Boolean of whether this buffer can be re-used
157 * Boolean of whether this buffer has been shared with an external client.
162 * Boolean of whether this buffer is cache coherent
167 #define BO_ALLOC_BUSY (1<<0)
168 #define BO_ALLOC_ZEROED (1<<1)
171 * Allocate a buffer object.
173 * Buffer objects are not necessarily initially mapped into CPU virtual
174 * address space or graphics device aperture. They must be mapped
175 * using brw_bo_map() to be used by the CPU.
177 struct brw_bo
*brw_bo_alloc(struct brw_bufmgr
*bufmgr
, const char *name
,
178 uint64_t size
, uint64_t alignment
);
181 * Allocate a tiled buffer object.
183 * Alignment for tiled objects is set automatically; the 'flags'
184 * argument provides a hint about how the object will be used initially.
186 * Valid tiling formats are:
191 struct brw_bo
*brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
,
194 uint32_t tiling_mode
,
199 * Allocate a tiled buffer object.
201 * Alignment for tiled objects is set automatically; the 'flags'
202 * argument provides a hint about how the object will be used initially.
204 * Valid tiling formats are:
209 * Note the tiling format may be rejected; callers should check the
210 * 'tiling_mode' field on return, as well as the pitch value, which
211 * may have been rounded up to accommodate for tiling restrictions.
213 struct brw_bo
*brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
,
215 int x
, int y
, int cpp
,
216 uint32_t tiling_mode
,
220 /** Takes a reference on a buffer object */
222 brw_bo_reference(struct brw_bo
*bo
)
224 p_atomic_inc(&bo
->refcount
);
228 * Releases a reference on a buffer object, freeing the data if
229 * no references remain.
231 void brw_bo_unreference(struct brw_bo
*bo
);
233 /* Must match MapBufferRange interface (for convenience) */
234 #define MAP_READ GL_MAP_READ_BIT
235 #define MAP_WRITE GL_MAP_WRITE_BIT
236 #define MAP_ASYNC GL_MAP_UNSYNCHRONIZED_BIT
237 #define MAP_PERSISTENT GL_MAP_PERSISTENT_BIT
238 #define MAP_COHERENT GL_MAP_COHERENT_BIT
240 #define MAP_INTERNAL_MASK (0xff << 24)
241 #define MAP_RAW (0x01 << 24)
244 * Maps the buffer into userspace.
246 * This function will block waiting for any existing execution on the
247 * buffer to complete, first. The resulting mapping is returned.
249 MUST_CHECK
void *brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
);
252 * Reduces the refcount on the userspace mapping of the buffer
255 static inline int brw_bo_unmap(struct brw_bo
*bo
) { return 0; }
257 /** Write data into an object. */
258 int brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
259 uint64_t size
, const void *data
);
261 * Waits for rendering to an object by the GPU to have completed.
263 * This is not required for any access to the BO by bo_map,
264 * bo_subdata, etc. It is merely a way for the driver to implement
267 void brw_bo_wait_rendering(struct brw_bo
*bo
);
270 * Tears down the buffer manager instance.
272 void brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
);
275 * Get the current tiling (and resulting swizzling) mode for the bo.
277 * \param buf Buffer to get tiling mode for
278 * \param tiling_mode returned tiling mode
279 * \param swizzle_mode returned swizzling mode
281 int brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
282 uint32_t *swizzle_mode
);
285 * Create a visible name for a buffer which can be used by other apps
287 * \param buf Buffer to create a name for
288 * \param name Returned name
290 int brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
);
293 * Returns 1 if mapping the buffer for write could cause the process
294 * to block, due to the object being active in the GPU.
296 int brw_bo_busy(struct brw_bo
*bo
);
299 * Specify the volatility of the buffer.
300 * \param bo Buffer to create a name for
301 * \param madv The purgeable status
303 * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
304 * reclaimed under memory pressure. If you subsequently require the buffer,
305 * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
307 * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
308 * marked as I915_MADV_DONTNEED.
310 int brw_bo_madvise(struct brw_bo
*bo
, int madv
);
312 /* drm_bacon_bufmgr_gem.c */
313 struct brw_bufmgr
*brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
);
314 struct brw_bo
*brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
316 unsigned int handle
);
317 void brw_bufmgr_enable_reuse(struct brw_bufmgr
*bufmgr
);
319 int brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
);
321 uint32_t brw_create_hw_context(struct brw_bufmgr
*bufmgr
);
323 #define BRW_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
324 #define BRW_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
325 #define BRW_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2)
327 int brw_hw_context_set_priority(struct brw_bufmgr
*bufmgr
,
331 void brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
);
333 int brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
);
334 struct brw_bo
*brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
,
336 struct brw_bo
*brw_bo_gem_create_from_prime_tiled(struct brw_bufmgr
*bufmgr
,
338 uint32_t tiling_mode
,
341 uint32_t brw_bo_export_gem_handle(struct brw_bo
*bo
);
343 int brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
,
348 #if defined(__cplusplus)
351 #endif /* INTEL_BUFMGR_H */