i965: Port CC_VIEWPORT to genxml.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "brw_defines.h"
36 #include "brw_util.h"
37 #include "main/macros.h"
38 #include "main/stencil.h"
39 #include "intel_batchbuffer.h"
40
41 /**
42 * Modify blend function to force destination alpha to 1.0
43 *
44 * If \c function specifies a blend function that uses destination alpha,
45 * replace it with a function that hard-wires destination alpha to 1.0. This
46 * is used when rendering to xRGB targets.
47 */
48 GLenum
49 brw_fix_xRGB_alpha(GLenum function)
50 {
51 switch (function) {
52 case GL_DST_ALPHA:
53 return GL_ONE;
54
55 case GL_ONE_MINUS_DST_ALPHA:
56 case GL_SRC_ALPHA_SATURATE:
57 return GL_ZERO;
58 }
59
60 return function;
61 }
62
63 /**
64 * Creates a CC unit packet from the current blend state.
65 */
66 static void upload_cc_unit(struct brw_context *brw)
67 {
68 struct gl_context *ctx = &brw->ctx;
69 struct brw_cc_unit_state *cc;
70
71 cc = brw_state_batch(brw, sizeof(*cc), 64, &brw->cc.state_offset);
72 memset(cc, 0, sizeof(*cc));
73
74 /* _NEW_STENCIL | _NEW_BUFFERS */
75 if (ctx->Stencil._Enabled) {
76 const unsigned back = ctx->Stencil._BackFace;
77
78 cc->cc0.stencil_enable = 1;
79 cc->cc0.stencil_func =
80 intel_translate_compare_func(ctx->Stencil.Function[0]);
81 cc->cc0.stencil_fail_op =
82 intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
83 cc->cc0.stencil_pass_depth_fail_op =
84 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
85 cc->cc0.stencil_pass_depth_pass_op =
86 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
87 cc->cc1.stencil_ref = _mesa_get_stencil_ref(ctx, 0);
88 cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0];
89 cc->cc1.stencil_test_mask = ctx->Stencil.ValueMask[0];
90
91 if (ctx->Stencil._TestTwoSide) {
92 cc->cc0.bf_stencil_enable = 1;
93 cc->cc0.bf_stencil_func =
94 intel_translate_compare_func(ctx->Stencil.Function[back]);
95 cc->cc0.bf_stencil_fail_op =
96 intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
97 cc->cc0.bf_stencil_pass_depth_fail_op =
98 intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
99 cc->cc0.bf_stencil_pass_depth_pass_op =
100 intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
101 cc->cc1.bf_stencil_ref = _mesa_get_stencil_ref(ctx, back);
102 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
103 cc->cc2.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
104 }
105
106 /* Not really sure about this:
107 */
108 if (ctx->Stencil.WriteMask[0] ||
109 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back]))
110 cc->cc0.stencil_write_enable = 1;
111 }
112
113 /* _NEW_COLOR */
114 if (ctx->Color.ColorLogicOpEnabled && ctx->Color.LogicOp != GL_COPY) {
115 cc->cc2.logicop_enable = 1;
116 cc->cc5.logicop_func = intel_translate_logic_op(ctx->Color.LogicOp);
117 } else if (ctx->Color.BlendEnabled && !ctx->Color._AdvancedBlendMode) {
118 GLenum eqRGB = ctx->Color.Blend[0].EquationRGB;
119 GLenum eqA = ctx->Color.Blend[0].EquationA;
120 GLenum srcRGB = ctx->Color.Blend[0].SrcRGB;
121 GLenum dstRGB = ctx->Color.Blend[0].DstRGB;
122 GLenum srcA = ctx->Color.Blend[0].SrcA;
123 GLenum dstA = ctx->Color.Blend[0].DstA;
124
125 /* If the renderbuffer is XRGB, we have to frob the blend function to
126 * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA
127 * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
128 */
129 if (ctx->DrawBuffer->Visual.alphaBits == 0) {
130 srcRGB = brw_fix_xRGB_alpha(srcRGB);
131 srcA = brw_fix_xRGB_alpha(srcA);
132 dstRGB = brw_fix_xRGB_alpha(dstRGB);
133 dstA = brw_fix_xRGB_alpha(dstA);
134 }
135
136 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
137 srcRGB = dstRGB = GL_ONE;
138 }
139
140 if (eqA == GL_MIN || eqA == GL_MAX) {
141 srcA = dstA = GL_ONE;
142 }
143
144 cc->cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
145 cc->cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
146 cc->cc6.blend_function = brw_translate_blend_equation(eqRGB);
147
148 cc->cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
149 cc->cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA);
150 cc->cc5.ia_blend_function = brw_translate_blend_equation(eqA);
151
152 cc->cc3.blend_enable = 1;
153 cc->cc3.ia_blend_enable = (srcA != srcRGB ||
154 dstA != dstRGB ||
155 eqA != eqRGB);
156 }
157
158 /* _NEW_BUFFERS */
159 if (ctx->Color.AlphaEnabled && ctx->DrawBuffer->_NumColorDrawBuffers <= 1) {
160 cc->cc3.alpha_test = 1;
161 cc->cc3.alpha_test_func =
162 intel_translate_compare_func(ctx->Color.AlphaFunc);
163 cc->cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
164
165 UNCLAMPED_FLOAT_TO_UBYTE(cc->cc7.alpha_ref.ub[0], ctx->Color.AlphaRef);
166 }
167
168 if (ctx->Color.DitherFlag) {
169 cc->cc5.dither_enable = 1;
170 cc->cc6.y_dither_offset = 0;
171 cc->cc6.x_dither_offset = 0;
172 }
173
174 /* _NEW_DEPTH */
175 if (ctx->Depth.Test) {
176 cc->cc2.depth_test = 1;
177 cc->cc2.depth_test_function =
178 intel_translate_compare_func(ctx->Depth.Func);
179 cc->cc2.depth_write_enable = brw_depth_writes_enabled(brw);
180 }
181
182 if (brw->stats_wm)
183 cc->cc5.statistics_enable = 1;
184
185 /* BRW_NEW_CC_VP */
186 cc->cc4.cc_viewport_state_offset = (brw->batch.bo->offset64 +
187 brw->cc.vp_offset) >> 5; /* reloc */
188
189 brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
190
191 /* Emit CC viewport relocation */
192 brw_emit_reloc(&brw->batch,
193 (brw->cc.state_offset +
194 offsetof(struct brw_cc_unit_state, cc4)),
195 brw->batch.bo, brw->cc.vp_offset,
196 I915_GEM_DOMAIN_INSTRUCTION, 0);
197 }
198
199 const struct brw_tracked_state brw_cc_unit = {
200 .dirty = {
201 .mesa = _NEW_BUFFERS |
202 _NEW_COLOR |
203 _NEW_DEPTH |
204 _NEW_STENCIL,
205 .brw = BRW_NEW_BATCH |
206 BRW_NEW_BLORP |
207 BRW_NEW_CC_VP |
208 BRW_NEW_STATS_WM,
209 },
210 .emit = upload_cc_unit,
211 };
212
213 static void upload_blend_constant_color(struct brw_context *brw)
214 {
215 struct gl_context *ctx = &brw->ctx;
216
217 BEGIN_BATCH(5);
218 OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2));
219 OUT_BATCH_F(ctx->Color.BlendColorUnclamped[0]);
220 OUT_BATCH_F(ctx->Color.BlendColorUnclamped[1]);
221 OUT_BATCH_F(ctx->Color.BlendColorUnclamped[2]);
222 OUT_BATCH_F(ctx->Color.BlendColorUnclamped[3]);
223 ADVANCE_BATCH();
224 }
225
226 const struct brw_tracked_state brw_blend_constant_color = {
227 .dirty = {
228 .mesa = _NEW_COLOR,
229 .brw = BRW_NEW_CONTEXT |
230 BRW_NEW_BLORP,
231 },
232 .emit = upload_blend_constant_color
233 };