src/mesa/drivers/dri/i965/brw_cc.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "brw_util.h"
  37 #include "enums.h"
  38
  39 static void upload_cc_vp( struct brw_context *brw )
  40 {
  41    struct brw_cc_viewport ccv;
  42
  43    memset(&ccv, 0, sizeof(ccv));
  44
  45    ccv.min_depth = 0.0;
  46    ccv.max_depth = 1.0;
  47
  48    brw->cc.vp_gs_offset = brw_cache_data( &brw->cache[BRW_CC_VP], &ccv );
  49 }
  50
  51 const struct brw_tracked_state brw_cc_vp = {
  52    .dirty = {
  53       .mesa = 0,
  54       .brw = BRW_NEW_CONTEXT,
  55       .cache = 0
  56    },
  57    .update = upload_cc_vp
  58 };
  59
  60
  61 static void upload_cc_unit( struct brw_context *brw )
  62 {
  63    struct brw_cc_unit_state cc;
  64
  65    memset(&cc, 0, sizeof(cc));
  66
  67    /* _NEW_STENCIL */
  68    if (brw->attribs.Stencil->Enabled) {
  69       cc.cc0.stencil_enable = brw->attribs.Stencil->Enabled;
  70       cc.cc0.stencil_func = intel_translate_compare_func(brw->attribs.Stencil->Function[0]);
  71       cc.cc0.stencil_fail_op = intel_translate_stencil_op(brw->attribs.Stencil->FailFunc[0]);
  72       cc.cc0.stencil_pass_depth_fail_op = intel_translate_stencil_op(brw->attribs.Stencil->ZFailFunc[0]);
  73       cc.cc0.stencil_pass_depth_pass_op = intel_translate_stencil_op(brw->attribs.Stencil->ZPassFunc[0]);
  74       cc.cc1.stencil_ref = brw->attribs.Stencil->Ref[0];
  75       cc.cc1.stencil_write_mask = brw->attribs.Stencil->WriteMask[0];
  76       cc.cc1.stencil_test_mask = brw->attribs.Stencil->ValueMask[0];
  77
  78       if (brw->attribs.Stencil->TestTwoSide) {
  79          cc.cc0.bf_stencil_enable = brw->attribs.Stencil->TestTwoSide;
  80          cc.cc0.bf_stencil_func = intel_translate_compare_func(brw->attribs.Stencil->Function[1]);
  81          cc.cc0.bf_stencil_fail_op = intel_translate_stencil_op(brw->attribs.Stencil->FailFunc[1]);
  82          cc.cc0.bf_stencil_pass_depth_fail_op = intel_translate_stencil_op(brw->attribs.Stencil->ZFailFunc[1]);
  83          cc.cc0.bf_stencil_pass_depth_pass_op = intel_translate_stencil_op(brw->attribs.Stencil->ZPassFunc[1]);
  84          cc.cc1.bf_stencil_ref = brw->attribs.Stencil->Ref[1];
  85          cc.cc2.bf_stencil_write_mask = brw->attribs.Stencil->WriteMask[1];
  86          cc.cc2.bf_stencil_test_mask = brw->attribs.Stencil->ValueMask[1];
  87       }
  88
  89       /* Not really sure about this:
  90        */
  91       if (brw->attribs.Stencil->WriteMask[0] ||
  92           (brw->attribs.Stencil->TestTwoSide && brw->attribs.Stencil->WriteMask[1]))
  93          cc.cc0.stencil_write_enable = 1;
  94    }
  95
  96    /* _NEW_COLOR */
  97    if (brw->attribs.Color->_LogicOpEnabled) {
  98       cc.cc2.logicop_enable = 1;
  99       cc.cc5.logicop_func = intel_translate_logic_op( brw->attribs.Color->LogicOp );
 100    }
 101    else if (brw->attribs.Color->BlendEnabled) {
 102       GLenum eqRGB = brw->attribs.Color->BlendEquationRGB;
 103       GLenum eqA = brw->attribs.Color->BlendEquationA;
 104       GLenum srcRGB = brw->attribs.Color->BlendSrcRGB;
 105       GLenum dstRGB = brw->attribs.Color->BlendDstRGB;
 106       GLenum srcA = brw->attribs.Color->BlendSrcA;
 107       GLenum dstA = brw->attribs.Color->BlendDstA;
 108
 109       if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
 110          srcRGB = dstRGB = GL_ONE;
 111       }
 112
 113       if (eqA == GL_MIN || eqA == GL_MAX) {
 114          srcA = dstA = GL_ONE;
 115       }
 116
 117       cc.cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
 118       cc.cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
 119       cc.cc6.blend_function = brw_translate_blend_equation( eqRGB );
 120
 121       cc.cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
 122       cc.cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA);
 123       cc.cc5.ia_blend_function = brw_translate_blend_equation( eqA );
 124
 125       cc.cc3.blend_enable = 1;
 126       cc.cc3.ia_blend_enable = (srcA != srcRGB ||
 127                                 dstA != dstRGB ||
 128                                 eqA != eqRGB);
 129    }
 130
 131    if (brw->attribs.Color->AlphaEnabled) {
 132       cc.cc3.alpha_test = 1;
 133       cc.cc3.alpha_test_func = intel_translate_compare_func(brw->attribs.Color->AlphaFunc);
 134
 135       UNCLAMPED_FLOAT_TO_UBYTE(cc.cc7.alpha_ref.ub[0], brw->attribs.Color->AlphaRef);
 136
 137       cc.cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
 138    }
 139
 140    if (brw->attribs.Color->DitherFlag) {
 141       cc.cc5.dither_enable = 1;
 142       cc.cc6.y_dither_offset = 0;
 143       cc.cc6.x_dither_offset = 0;
 144    }
 145
 146    /* _NEW_DEPTH */
 147    if (brw->attribs.Depth->Test) {
 148       cc.cc2.depth_test = brw->attribs.Depth->Test;
 149       cc.cc2.depth_test_function = intel_translate_compare_func(brw->attribs.Depth->Func);
 150       cc.cc2.depth_write_enable = brw->attribs.Depth->Mask;
 151    }
 152
 153    /* CACHE_NEW_CC_VP */
 154    cc.cc4.cc_viewport_state_offset =  brw->cc.vp_gs_offset >> 5;
 155
 156    if (INTEL_DEBUG & DEBUG_STATS)
 157       cc.cc5.statistics_enable = 1;
 158
 159    brw->cc.state_gs_offset = brw_cache_data( &brw->cache[BRW_CC_UNIT], &cc );
 160 }
 161
 162 const struct brw_tracked_state brw_cc_unit = {
 163    .dirty = {
 164       .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
 165       .brw = 0,
 166       .cache = CACHE_NEW_CC_VP
 167    },
 168    .update = upload_cc_unit
 169 };
 170
 171
 172