Merge remote branch 'main/master' into radeon-rewrite
[mesa.git] / src / mesa / drivers / dri / i965 / brw_cc.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "brw_defines.h"
36 #include "brw_util.h"
37 #include "main/macros.h"
38 #include "main/enums.h"
39
40 static void prepare_cc_vp( struct brw_context *brw )
41 {
42 struct brw_cc_viewport ccv;
43
44 memset(&ccv, 0, sizeof(ccv));
45
46 ccv.min_depth = 0.0;
47 ccv.max_depth = 1.0;
48
49 dri_bo_unreference(brw->cc.vp_bo);
50 brw->cc.vp_bo = brw_cache_data( &brw->cache, BRW_CC_VP, &ccv, NULL, 0 );
51 }
52
53 const struct brw_tracked_state brw_cc_vp = {
54 .dirty = {
55 .mesa = 0,
56 .brw = BRW_NEW_CONTEXT,
57 .cache = 0
58 },
59 .prepare = prepare_cc_vp
60 };
61
62 struct brw_cc_unit_key {
63 GLboolean stencil, stencil_two_side, color_blend, alpha_enabled;
64
65 GLenum stencil_func[2], stencil_fail_op[2];
66 GLenum stencil_pass_depth_fail_op[2], stencil_pass_depth_pass_op[2];
67 GLubyte stencil_ref[2], stencil_write_mask[2], stencil_test_mask[2];
68 GLenum logic_op;
69
70 GLenum blend_eq_rgb, blend_eq_a;
71 GLenum blend_src_rgb, blend_src_a;
72 GLenum blend_dst_rgb, blend_dst_a;
73
74 GLenum alpha_func;
75 GLclampf alpha_ref;
76
77 GLboolean dither;
78
79 GLboolean depth_test, depth_write;
80 GLenum depth_func;
81 };
82
83 static void
84 cc_unit_populate_key(struct brw_context *brw, struct brw_cc_unit_key *key)
85 {
86 GLcontext *ctx = &brw->intel.ctx;
87 const unsigned back = ctx->Stencil._BackFace;
88
89 memset(key, 0, sizeof(*key));
90
91 key->stencil = ctx->Stencil._Enabled;
92 key->stencil_two_side = ctx->Stencil._TestTwoSide;
93
94 if (key->stencil) {
95 key->stencil_func[0] = ctx->Stencil.Function[0];
96 key->stencil_fail_op[0] = ctx->Stencil.FailFunc[0];
97 key->stencil_pass_depth_fail_op[0] = ctx->Stencil.ZFailFunc[0];
98 key->stencil_pass_depth_pass_op[0] = ctx->Stencil.ZPassFunc[0];
99 key->stencil_ref[0] = ctx->Stencil.Ref[0];
100 key->stencil_write_mask[0] = ctx->Stencil.WriteMask[0];
101 key->stencil_test_mask[0] = ctx->Stencil.ValueMask[0];
102 }
103 if (key->stencil_two_side) {
104 key->stencil_func[1] = ctx->Stencil.Function[back];
105 key->stencil_fail_op[1] = ctx->Stencil.FailFunc[back];
106 key->stencil_pass_depth_fail_op[1] = ctx->Stencil.ZFailFunc[back];
107 key->stencil_pass_depth_pass_op[1] = ctx->Stencil.ZPassFunc[back];
108 key->stencil_ref[1] = ctx->Stencil.Ref[back];
109 key->stencil_write_mask[1] = ctx->Stencil.WriteMask[back];
110 key->stencil_test_mask[1] = ctx->Stencil.ValueMask[back];
111 }
112
113 if (ctx->Color._LogicOpEnabled)
114 key->logic_op = ctx->Color.LogicOp;
115 else
116 key->logic_op = GL_COPY;
117
118 key->color_blend = ctx->Color.BlendEnabled;
119 if (key->color_blend) {
120 key->blend_eq_rgb = ctx->Color.BlendEquationRGB;
121 key->blend_eq_a = ctx->Color.BlendEquationA;
122 key->blend_src_rgb = ctx->Color.BlendSrcRGB;
123 key->blend_dst_rgb = ctx->Color.BlendDstRGB;
124 key->blend_src_a = ctx->Color.BlendSrcA;
125 key->blend_dst_a = ctx->Color.BlendDstA;
126 }
127
128 key->alpha_enabled = ctx->Color.AlphaEnabled;
129 if (key->alpha_enabled) {
130 key->alpha_func = ctx->Color.AlphaFunc;
131 key->alpha_ref = ctx->Color.AlphaRef;
132 }
133
134 key->dither = ctx->Color.DitherFlag;
135
136 key->depth_test = ctx->Depth.Test;
137 if (key->depth_test) {
138 key->depth_func = ctx->Depth.Func;
139 key->depth_write = ctx->Depth.Mask;
140 }
141 }
142
143 /**
144 * Creates the state cache entry for the given CC unit key.
145 */
146 static dri_bo *
147 cc_unit_create_from_key(struct brw_context *brw, struct brw_cc_unit_key *key)
148 {
149 struct brw_cc_unit_state cc;
150 dri_bo *bo;
151
152 memset(&cc, 0, sizeof(cc));
153
154 /* _NEW_STENCIL */
155 if (key->stencil) {
156 cc.cc0.stencil_enable = 1;
157 cc.cc0.stencil_func =
158 intel_translate_compare_func(key->stencil_func[0]);
159 cc.cc0.stencil_fail_op =
160 intel_translate_stencil_op(key->stencil_fail_op[0]);
161 cc.cc0.stencil_pass_depth_fail_op =
162 intel_translate_stencil_op(key->stencil_pass_depth_fail_op[0]);
163 cc.cc0.stencil_pass_depth_pass_op =
164 intel_translate_stencil_op(key->stencil_pass_depth_pass_op[0]);
165 cc.cc1.stencil_ref = key->stencil_ref[0];
166 cc.cc1.stencil_write_mask = key->stencil_write_mask[0];
167 cc.cc1.stencil_test_mask = key->stencil_test_mask[0];
168
169 if (key->stencil_two_side) {
170 cc.cc0.bf_stencil_enable = 1;
171 cc.cc0.bf_stencil_func =
172 intel_translate_compare_func(key->stencil_func[1]);
173 cc.cc0.bf_stencil_fail_op =
174 intel_translate_stencil_op(key->stencil_fail_op[1]);
175 cc.cc0.bf_stencil_pass_depth_fail_op =
176 intel_translate_stencil_op(key->stencil_pass_depth_fail_op[1]);
177 cc.cc0.bf_stencil_pass_depth_pass_op =
178 intel_translate_stencil_op(key->stencil_pass_depth_pass_op[1]);
179 cc.cc1.bf_stencil_ref = key->stencil_ref[1];
180 cc.cc2.bf_stencil_write_mask = key->stencil_write_mask[1];
181 cc.cc2.bf_stencil_test_mask = key->stencil_test_mask[1];
182 }
183
184 /* Not really sure about this:
185 */
186 if (key->stencil_write_mask[0] ||
187 (key->stencil_two_side && key->stencil_write_mask[1]))
188 cc.cc0.stencil_write_enable = 1;
189 }
190
191 /* _NEW_COLOR */
192 if (key->logic_op != GL_COPY) {
193 cc.cc2.logicop_enable = 1;
194 cc.cc5.logicop_func = intel_translate_logic_op(key->logic_op);
195 } else if (key->color_blend) {
196 GLenum eqRGB = key->blend_eq_rgb;
197 GLenum eqA = key->blend_eq_a;
198 GLenum srcRGB = key->blend_src_rgb;
199 GLenum dstRGB = key->blend_dst_rgb;
200 GLenum srcA = key->blend_src_a;
201 GLenum dstA = key->blend_dst_a;
202
203 if (eqRGB == GL_MIN || eqRGB == GL_MAX) {
204 srcRGB = dstRGB = GL_ONE;
205 }
206
207 if (eqA == GL_MIN || eqA == GL_MAX) {
208 srcA = dstA = GL_ONE;
209 }
210
211 cc.cc6.dest_blend_factor = brw_translate_blend_factor(dstRGB);
212 cc.cc6.src_blend_factor = brw_translate_blend_factor(srcRGB);
213 cc.cc6.blend_function = brw_translate_blend_equation(eqRGB);
214
215 cc.cc5.ia_dest_blend_factor = brw_translate_blend_factor(dstA);
216 cc.cc5.ia_src_blend_factor = brw_translate_blend_factor(srcA);
217 cc.cc5.ia_blend_function = brw_translate_blend_equation(eqA);
218
219 cc.cc3.blend_enable = 1;
220 cc.cc3.ia_blend_enable = (srcA != srcRGB ||
221 dstA != dstRGB ||
222 eqA != eqRGB);
223 }
224
225 if (key->alpha_enabled) {
226 cc.cc3.alpha_test = 1;
227 cc.cc3.alpha_test_func = intel_translate_compare_func(key->alpha_func);
228 cc.cc3.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8;
229
230 UNCLAMPED_FLOAT_TO_UBYTE(cc.cc7.alpha_ref.ub[0], key->alpha_ref);
231 }
232
233 if (key->dither) {
234 cc.cc5.dither_enable = 1;
235 cc.cc6.y_dither_offset = 0;
236 cc.cc6.x_dither_offset = 0;
237 }
238
239 /* _NEW_DEPTH */
240 if (key->depth_test) {
241 cc.cc2.depth_test = 1;
242 cc.cc2.depth_test_function = intel_translate_compare_func(key->depth_func);
243 cc.cc2.depth_write_enable = key->depth_write;
244 }
245
246 /* CACHE_NEW_CC_VP */
247 cc.cc4.cc_viewport_state_offset = brw->cc.vp_bo->offset >> 5; /* reloc */
248
249 if (INTEL_DEBUG & DEBUG_STATS)
250 cc.cc5.statistics_enable = 1;
251
252 bo = brw_upload_cache(&brw->cache, BRW_CC_UNIT,
253 key, sizeof(*key),
254 &brw->cc.vp_bo, 1,
255 &cc, sizeof(cc),
256 NULL, NULL);
257
258 /* Emit CC viewport relocation */
259 dri_bo_emit_reloc(bo,
260 I915_GEM_DOMAIN_INSTRUCTION,
261 0,
262 0,
263 offsetof(struct brw_cc_unit_state, cc4),
264 brw->cc.vp_bo);
265
266 return bo;
267 }
268
269 static void prepare_cc_unit( struct brw_context *brw )
270 {
271 struct brw_cc_unit_key key;
272
273 cc_unit_populate_key(brw, &key);
274
275 dri_bo_unreference(brw->cc.state_bo);
276 brw->cc.state_bo = brw_search_cache(&brw->cache, BRW_CC_UNIT,
277 &key, sizeof(key),
278 &brw->cc.vp_bo, 1,
279 NULL);
280
281 if (brw->cc.state_bo == NULL)
282 brw->cc.state_bo = cc_unit_create_from_key(brw, &key);
283 }
284
285 const struct brw_tracked_state brw_cc_unit = {
286 .dirty = {
287 .mesa = _NEW_STENCIL | _NEW_COLOR | _NEW_DEPTH,
288 .brw = 0,
289 .cache = CACHE_NEW_CC_VP
290 },
291 .prepare = prepare_cc_unit,
292 };
293
294
295