2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "brw_defines.h"
37 #include "main/macros.h"
40 brw_update_cc_vp(struct brw_context
*brw
)
42 struct gl_context
*ctx
= &brw
->intel
.ctx
;
43 struct brw_cc_viewport ccv
;
45 memset(&ccv
, 0, sizeof(ccv
));
48 if (ctx
->Transform
.DepthClamp
) {
50 ccv
.min_depth
= MIN2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
51 ccv
.max_depth
= MAX2(ctx
->Viewport
.Near
, ctx
->Viewport
.Far
);
57 drm_intel_bo_unreference(brw
->cc
.vp_bo
);
58 brw
->cc
.vp_bo
= brw_cache_data(&brw
->cache
, BRW_CC_VP
, &ccv
, sizeof(ccv
));
62 * Modify blend function to force destination alpha to 1.0
64 * If \c function specifies a blend function that uses destination alpha,
65 * replace it with a function that hard-wires destination alpha to 1.0. This
66 * is used when rendering to xRGB targets.
69 fix_xRGB_alpha(GLenum function
)
75 case GL_ONE_MINUS_DST_ALPHA
:
76 case GL_SRC_ALPHA_SATURATE
:
83 static void prepare_cc_unit(struct brw_context
*brw
)
85 brw_add_validated_bo(brw
, brw
->cc
.vp_bo
);
89 * Creates the state cache entry for the given CC unit key.
91 static void upload_cc_unit(struct brw_context
*brw
)
93 struct intel_context
*intel
= &brw
->intel
;
94 struct gl_context
*ctx
= &brw
->intel
.ctx
;
95 struct brw_cc_unit_state cc
;
98 memset(&cc
, 0, sizeof(cc
));
101 if (ctx
->Stencil
._Enabled
) {
102 const unsigned back
= ctx
->Stencil
._BackFace
;
104 cc
.cc0
.stencil_enable
= 1;
105 cc
.cc0
.stencil_func
=
106 intel_translate_compare_func(ctx
->Stencil
.Function
[0]);
107 cc
.cc0
.stencil_fail_op
=
108 intel_translate_stencil_op(ctx
->Stencil
.FailFunc
[0]);
109 cc
.cc0
.stencil_pass_depth_fail_op
=
110 intel_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]);
111 cc
.cc0
.stencil_pass_depth_pass_op
=
112 intel_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]);
113 cc
.cc1
.stencil_ref
= ctx
->Stencil
.Ref
[0];
114 cc
.cc1
.stencil_write_mask
= ctx
->Stencil
.WriteMask
[0];
115 cc
.cc1
.stencil_test_mask
= ctx
->Stencil
.ValueMask
[0];
117 if (ctx
->Stencil
._TestTwoSide
) {
118 cc
.cc0
.bf_stencil_enable
= 1;
119 cc
.cc0
.bf_stencil_func
=
120 intel_translate_compare_func(ctx
->Stencil
.Function
[back
]);
121 cc
.cc0
.bf_stencil_fail_op
=
122 intel_translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]);
123 cc
.cc0
.bf_stencil_pass_depth_fail_op
=
124 intel_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]);
125 cc
.cc0
.bf_stencil_pass_depth_pass_op
=
126 intel_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]);
127 cc
.cc1
.bf_stencil_ref
= ctx
->Stencil
.Ref
[back
];
128 cc
.cc2
.bf_stencil_write_mask
= ctx
->Stencil
.WriteMask
[back
];
129 cc
.cc2
.bf_stencil_test_mask
= ctx
->Stencil
.ValueMask
[back
];
132 /* Not really sure about this:
134 if (ctx
->Stencil
.WriteMask
[0] ||
135 (ctx
->Stencil
._TestTwoSide
&& ctx
->Stencil
.WriteMask
[back
]))
136 cc
.cc0
.stencil_write_enable
= 1;
140 if (ctx
->Color
._LogicOpEnabled
&& ctx
->Color
.LogicOp
!= GL_COPY
) {
141 cc
.cc2
.logicop_enable
= 1;
142 cc
.cc5
.logicop_func
= intel_translate_logic_op(ctx
->Color
.LogicOp
);
143 } else if (ctx
->Color
.BlendEnabled
) {
144 GLenum eqRGB
= ctx
->Color
.Blend
[0].EquationRGB
;
145 GLenum eqA
= ctx
->Color
.Blend
[0].EquationA
;
146 GLenum srcRGB
= ctx
->Color
.Blend
[0].SrcRGB
;
147 GLenum dstRGB
= ctx
->Color
.Blend
[0].DstRGB
;
148 GLenum srcA
= ctx
->Color
.Blend
[0].SrcA
;
149 GLenum dstA
= ctx
->Color
.Blend
[0].DstA
;
151 /* If the renderbuffer is XRGB, we have to frob the blend function to
152 * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA
153 * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
155 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0) {
156 srcRGB
= fix_xRGB_alpha(srcRGB
);
157 srcA
= fix_xRGB_alpha(srcA
);
158 dstRGB
= fix_xRGB_alpha(dstRGB
);
159 dstA
= fix_xRGB_alpha(dstA
);
162 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
) {
163 srcRGB
= dstRGB
= GL_ONE
;
166 if (eqA
== GL_MIN
|| eqA
== GL_MAX
) {
167 srcA
= dstA
= GL_ONE
;
170 cc
.cc6
.dest_blend_factor
= brw_translate_blend_factor(dstRGB
);
171 cc
.cc6
.src_blend_factor
= brw_translate_blend_factor(srcRGB
);
172 cc
.cc6
.blend_function
= brw_translate_blend_equation(eqRGB
);
174 cc
.cc5
.ia_dest_blend_factor
= brw_translate_blend_factor(dstA
);
175 cc
.cc5
.ia_src_blend_factor
= brw_translate_blend_factor(srcA
);
176 cc
.cc5
.ia_blend_function
= brw_translate_blend_equation(eqA
);
178 cc
.cc3
.blend_enable
= 1;
179 cc
.cc3
.ia_blend_enable
= (srcA
!= srcRGB
||
184 if (ctx
->Color
.AlphaEnabled
) {
185 cc
.cc3
.alpha_test
= 1;
186 cc
.cc3
.alpha_test_func
=
187 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
188 cc
.cc3
.alpha_test_format
= BRW_ALPHATEST_FORMAT_UNORM8
;
190 UNCLAMPED_FLOAT_TO_UBYTE(cc
.cc7
.alpha_ref
.ub
[0], ctx
->Color
.AlphaRef
);
193 if (ctx
->Color
.DitherFlag
) {
194 cc
.cc5
.dither_enable
= 1;
195 cc
.cc6
.y_dither_offset
= 0;
196 cc
.cc6
.x_dither_offset
= 0;
200 if (ctx
->Depth
.Test
) {
201 cc
.cc2
.depth_test
= 1;
202 cc
.cc2
.depth_test_function
=
203 intel_translate_compare_func(ctx
->Depth
.Func
);
204 cc
.cc2
.depth_write_enable
= ctx
->Depth
.Mask
;
207 if (intel
->stats_wm
|| unlikely(INTEL_DEBUG
& DEBUG_STATS
))
208 cc
.cc5
.statistics_enable
= 1;
210 /* CACHE_NEW_CC_VP */
211 cc
.cc4
.cc_viewport_state_offset
= brw
->cc
.vp_bo
->offset
>> 5; /* reloc */
213 map
= brw_state_batch(brw
, sizeof(cc
), 64,
214 &brw
->cc
.state_bo
, &brw
->cc
.state_offset
);
215 memcpy(map
, &cc
, sizeof(cc
));
216 brw
->state
.dirty
.cache
|= CACHE_NEW_CC_UNIT
;
218 /* Emit CC viewport relocation */
219 drm_intel_bo_emit_reloc(brw
->cc
.state_bo
, (brw
->cc
.state_offset
+
220 offsetof(struct brw_cc_unit_state
,
223 I915_GEM_DOMAIN_INSTRUCTION
, 0);
226 const struct brw_tracked_state brw_cc_unit
= {
228 .mesa
= _NEW_STENCIL
| _NEW_COLOR
| _NEW_DEPTH
,
229 .brw
= BRW_NEW_BATCH
,
230 .cache
= CACHE_NEW_CC_VP
232 .prepare
= prepare_cc_unit
,
233 .emit
= upload_cc_unit
,
236 static void upload_blend_constant_color(struct brw_context
*brw
)
238 struct gl_context
*ctx
= &brw
->intel
.ctx
;
239 struct brw_blend_constant_color bcc
;
241 memset(&bcc
, 0, sizeof(bcc
));
242 bcc
.header
.opcode
= _3DSTATE_BLEND_CONSTANT_COLOR
;
243 bcc
.header
.length
= sizeof(bcc
)/4-2;
244 bcc
.blend_constant_color
[0] = ctx
->Color
.BlendColor
[0];
245 bcc
.blend_constant_color
[1] = ctx
->Color
.BlendColor
[1];
246 bcc
.blend_constant_color
[2] = ctx
->Color
.BlendColor
[2];
247 bcc
.blend_constant_color
[3] = ctx
->Color
.BlendColor
[3];
249 BRW_CACHED_BATCH_STRUCT(brw
, &bcc
);
252 const struct brw_tracked_state brw_blend_constant_color
= {
255 .brw
= BRW_NEW_CONTEXT
,
258 .emit
= upload_blend_constant_color