2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "brw_context.h"
34 #include "brw_state.h"
35 #include "brw_defines.h"
37 #include "main/macros.h"
38 #include "main/stencil.h"
39 #include "intel_batchbuffer.h"
42 brw_upload_cc_vp(struct brw_context
*brw
)
44 struct gl_context
*ctx
= &brw
->ctx
;
45 struct brw_cc_viewport
*ccv
;
47 ccv
= brw_state_batch(brw
, AUB_TRACE_CC_VP_STATE
,
48 sizeof(*ccv
) * ctx
->Const
.MaxViewports
, 32,
52 for (unsigned i
= 0; i
< ctx
->Const
.MaxViewports
; i
++) {
53 if (ctx
->Transform
.DepthClamp
) {
55 ccv
[i
].min_depth
= MIN2(ctx
->ViewportArray
[i
].Near
,
56 ctx
->ViewportArray
[i
].Far
);
57 ccv
[i
].max_depth
= MAX2(ctx
->ViewportArray
[i
].Near
,
58 ctx
->ViewportArray
[i
].Far
);
60 ccv
[i
].min_depth
= 0.0;
61 ccv
[i
].max_depth
= 1.0;
65 brw
->state
.dirty
.cache
|= CACHE_NEW_CC_VP
;
68 const struct brw_tracked_state brw_cc_vp
= {
70 .mesa
= _NEW_TRANSFORM
|
75 .emit
= brw_upload_cc_vp
79 * Modify blend function to force destination alpha to 1.0
81 * If \c function specifies a blend function that uses destination alpha,
82 * replace it with a function that hard-wires destination alpha to 1.0. This
83 * is used when rendering to xRGB targets.
86 brw_fix_xRGB_alpha(GLenum function
)
92 case GL_ONE_MINUS_DST_ALPHA
:
93 case GL_SRC_ALPHA_SATURATE
:
101 * Creates a CC unit packet from the current blend state.
103 static void upload_cc_unit(struct brw_context
*brw
)
105 struct gl_context
*ctx
= &brw
->ctx
;
106 struct brw_cc_unit_state
*cc
;
108 cc
= brw_state_batch(brw
, AUB_TRACE_CC_STATE
,
109 sizeof(*cc
), 64, &brw
->cc
.state_offset
);
110 memset(cc
, 0, sizeof(*cc
));
112 /* _NEW_STENCIL | _NEW_BUFFERS */
113 if (ctx
->Stencil
._Enabled
) {
114 const unsigned back
= ctx
->Stencil
._BackFace
;
116 cc
->cc0
.stencil_enable
= 1;
117 cc
->cc0
.stencil_func
=
118 intel_translate_compare_func(ctx
->Stencil
.Function
[0]);
119 cc
->cc0
.stencil_fail_op
=
120 intel_translate_stencil_op(ctx
->Stencil
.FailFunc
[0]);
121 cc
->cc0
.stencil_pass_depth_fail_op
=
122 intel_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[0]);
123 cc
->cc0
.stencil_pass_depth_pass_op
=
124 intel_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[0]);
125 cc
->cc1
.stencil_ref
= _mesa_get_stencil_ref(ctx
, 0);
126 cc
->cc1
.stencil_write_mask
= ctx
->Stencil
.WriteMask
[0];
127 cc
->cc1
.stencil_test_mask
= ctx
->Stencil
.ValueMask
[0];
129 if (ctx
->Stencil
._TestTwoSide
) {
130 cc
->cc0
.bf_stencil_enable
= 1;
131 cc
->cc0
.bf_stencil_func
=
132 intel_translate_compare_func(ctx
->Stencil
.Function
[back
]);
133 cc
->cc0
.bf_stencil_fail_op
=
134 intel_translate_stencil_op(ctx
->Stencil
.FailFunc
[back
]);
135 cc
->cc0
.bf_stencil_pass_depth_fail_op
=
136 intel_translate_stencil_op(ctx
->Stencil
.ZFailFunc
[back
]);
137 cc
->cc0
.bf_stencil_pass_depth_pass_op
=
138 intel_translate_stencil_op(ctx
->Stencil
.ZPassFunc
[back
]);
139 cc
->cc1
.bf_stencil_ref
= _mesa_get_stencil_ref(ctx
, back
);
140 cc
->cc2
.bf_stencil_write_mask
= ctx
->Stencil
.WriteMask
[back
];
141 cc
->cc2
.bf_stencil_test_mask
= ctx
->Stencil
.ValueMask
[back
];
144 /* Not really sure about this:
146 if (ctx
->Stencil
.WriteMask
[0] ||
147 (ctx
->Stencil
._TestTwoSide
&& ctx
->Stencil
.WriteMask
[back
]))
148 cc
->cc0
.stencil_write_enable
= 1;
152 if (ctx
->Color
.ColorLogicOpEnabled
&& ctx
->Color
.LogicOp
!= GL_COPY
) {
153 cc
->cc2
.logicop_enable
= 1;
154 cc
->cc5
.logicop_func
= intel_translate_logic_op(ctx
->Color
.LogicOp
);
155 } else if (ctx
->Color
.BlendEnabled
) {
156 GLenum eqRGB
= ctx
->Color
.Blend
[0].EquationRGB
;
157 GLenum eqA
= ctx
->Color
.Blend
[0].EquationA
;
158 GLenum srcRGB
= ctx
->Color
.Blend
[0].SrcRGB
;
159 GLenum dstRGB
= ctx
->Color
.Blend
[0].DstRGB
;
160 GLenum srcA
= ctx
->Color
.Blend
[0].SrcA
;
161 GLenum dstA
= ctx
->Color
.Blend
[0].DstA
;
163 /* If the renderbuffer is XRGB, we have to frob the blend function to
164 * force the destination alpha to 1.0. This means replacing GL_DST_ALPHA
165 * with GL_ONE and GL_ONE_MINUS_DST_ALPHA with GL_ZERO.
167 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0) {
168 srcRGB
= brw_fix_xRGB_alpha(srcRGB
);
169 srcA
= brw_fix_xRGB_alpha(srcA
);
170 dstRGB
= brw_fix_xRGB_alpha(dstRGB
);
171 dstA
= brw_fix_xRGB_alpha(dstA
);
174 if (eqRGB
== GL_MIN
|| eqRGB
== GL_MAX
) {
175 srcRGB
= dstRGB
= GL_ONE
;
178 if (eqA
== GL_MIN
|| eqA
== GL_MAX
) {
179 srcA
= dstA
= GL_ONE
;
182 cc
->cc6
.dest_blend_factor
= brw_translate_blend_factor(dstRGB
);
183 cc
->cc6
.src_blend_factor
= brw_translate_blend_factor(srcRGB
);
184 cc
->cc6
.blend_function
= brw_translate_blend_equation(eqRGB
);
186 cc
->cc5
.ia_dest_blend_factor
= brw_translate_blend_factor(dstA
);
187 cc
->cc5
.ia_src_blend_factor
= brw_translate_blend_factor(srcA
);
188 cc
->cc5
.ia_blend_function
= brw_translate_blend_equation(eqA
);
190 cc
->cc3
.blend_enable
= 1;
191 cc
->cc3
.ia_blend_enable
= (srcA
!= srcRGB
||
197 if (ctx
->Color
.AlphaEnabled
&& ctx
->DrawBuffer
->_NumColorDrawBuffers
<= 1) {
198 cc
->cc3
.alpha_test
= 1;
199 cc
->cc3
.alpha_test_func
=
200 intel_translate_compare_func(ctx
->Color
.AlphaFunc
);
201 cc
->cc3
.alpha_test_format
= BRW_ALPHATEST_FORMAT_UNORM8
;
203 UNCLAMPED_FLOAT_TO_UBYTE(cc
->cc7
.alpha_ref
.ub
[0], ctx
->Color
.AlphaRef
);
206 if (ctx
->Color
.DitherFlag
) {
207 cc
->cc5
.dither_enable
= 1;
208 cc
->cc6
.y_dither_offset
= 0;
209 cc
->cc6
.x_dither_offset
= 0;
213 if (ctx
->Depth
.Test
) {
214 cc
->cc2
.depth_test
= 1;
215 cc
->cc2
.depth_test_function
=
216 intel_translate_compare_func(ctx
->Depth
.Func
);
217 cc
->cc2
.depth_write_enable
= ctx
->Depth
.Mask
;
220 if (brw
->stats_wm
|| unlikely(INTEL_DEBUG
& DEBUG_STATS
))
221 cc
->cc5
.statistics_enable
= 1;
223 /* CACHE_NEW_CC_VP */
224 cc
->cc4
.cc_viewport_state_offset
= (brw
->batch
.bo
->offset64
+
225 brw
->cc
.vp_offset
) >> 5; /* reloc */
227 brw
->state
.dirty
.cache
|= CACHE_NEW_CC_UNIT
;
229 /* Emit CC viewport relocation */
230 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
231 (brw
->cc
.state_offset
+
232 offsetof(struct brw_cc_unit_state
, cc4
)),
233 brw
->batch
.bo
, brw
->cc
.vp_offset
,
234 I915_GEM_DOMAIN_INSTRUCTION
, 0);
237 const struct brw_tracked_state brw_cc_unit
= {
239 .mesa
= _NEW_BUFFERS
|
243 .brw
= BRW_NEW_BATCH
|
245 .cache
= CACHE_NEW_CC_VP
247 .emit
= upload_cc_unit
,
250 static void upload_blend_constant_color(struct brw_context
*brw
)
252 struct gl_context
*ctx
= &brw
->ctx
;
255 OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR
<< 16 | (5-2));
256 OUT_BATCH_F(ctx
->Color
.BlendColorUnclamped
[0]);
257 OUT_BATCH_F(ctx
->Color
.BlendColorUnclamped
[1]);
258 OUT_BATCH_F(ctx
->Color
.BlendColorUnclamped
[2]);
259 OUT_BATCH_F(ctx
->Color
.BlendColorUnclamped
[3]);
263 const struct brw_tracked_state brw_blend_constant_color
= {
266 .brw
= BRW_NEW_CONTEXT
,
269 .emit
= upload_blend_constant_color