1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
4 * Copyright 2009, 2012 Intel Corporation.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
29 #include "main/glheader.h"
30 #include "main/mtypes.h"
31 #include "main/condrender.h"
32 #include "swrast/swrast.h"
33 #include "drivers/common/meta.h"
35 #include "intel_batchbuffer.h"
36 #include "intel_blit.h"
37 #include "intel_fbo.h"
38 #include "intel_mipmap_tree.h"
39 #include "intel_regions.h"
41 #include "brw_context.h"
42 #include "brw_blorp.h"
44 #define FILE_DEBUG_FLAG DEBUG_BLIT
46 static const char *buffer_names
[] = {
47 [BUFFER_FRONT_LEFT
] = "front",
48 [BUFFER_BACK_LEFT
] = "back",
49 [BUFFER_FRONT_RIGHT
] = "front right",
50 [BUFFER_BACK_RIGHT
] = "back right",
51 [BUFFER_DEPTH
] = "depth",
52 [BUFFER_STENCIL
] = "stencil",
53 [BUFFER_ACCUM
] = "accum",
54 [BUFFER_AUX0
] = "aux0",
55 [BUFFER_COLOR0
] = "color0",
56 [BUFFER_COLOR1
] = "color1",
57 [BUFFER_COLOR2
] = "color2",
58 [BUFFER_COLOR3
] = "color3",
59 [BUFFER_COLOR4
] = "color4",
60 [BUFFER_COLOR5
] = "color5",
61 [BUFFER_COLOR6
] = "color6",
62 [BUFFER_COLOR7
] = "color7",
66 debug_mask(const char *name
, GLbitfield mask
)
70 if (unlikely(INTEL_DEBUG
& DEBUG_BLIT
)) {
71 DBG("%s clear:", name
);
72 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
74 DBG(" %s", buffer_names
[i
]);
81 * Returns true if the scissor is a noop (cuts out nothing).
84 noop_scissor(struct gl_context
*ctx
, struct gl_framebuffer
*fb
)
86 return ctx
->Scissor
.ScissorArray
[0].X
<= 0 &&
87 ctx
->Scissor
.ScissorArray
[0].Y
<= 0 &&
88 ctx
->Scissor
.ScissorArray
[0].Width
>= fb
->Width
&&
89 ctx
->Scissor
.ScissorArray
[0].Height
>= fb
->Height
;
93 * Implements fast depth clears on gen6+.
95 * Fast clears basically work by setting a flag in each of the subspans
96 * represented in the HiZ buffer that says "When you need the depth values for
97 * this subspan, it's the hardware's current clear value." Then later rendering
98 * can just use the static clear value instead of referencing memory.
100 * The tricky part of the implementation is that you have to have the clear
101 * value that was used on the depth buffer in place for all further rendering,
102 * at least until a resolve to the real depth buffer happens.
105 brw_fast_clear_depth(struct gl_context
*ctx
)
107 struct brw_context
*brw
= brw_context(ctx
);
108 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
109 struct intel_renderbuffer
*depth_irb
=
110 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
111 struct intel_mipmap_tree
*mt
= depth_irb
->mt
;
112 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
117 if (!intel_renderbuffer_has_hiz(depth_irb
))
120 /* We only handle full buffer clears -- otherwise you'd have to track whether
121 * a previous clear had happened at a different clear value and resolve it
124 if ((ctx
->Scissor
.EnableFlags
& 1) && !noop_scissor(ctx
, fb
)) {
125 perf_debug("Failed to fast clear depth due to scissor being enabled. "
126 "Possible 5%% performance win if avoided.\n");
130 uint32_t depth_clear_value
;
131 switch (mt
->format
) {
132 case MESA_FORMAT_Z32_FLOAT_S8X24_UINT
:
133 case MESA_FORMAT_Z24_UNORM_S8_UINT
:
134 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
136 * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
137 * enabled (the legacy method of clearing must be performed):
139 * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
144 case MESA_FORMAT_Z_FLOAT32
:
145 depth_clear_value
= float_as_int(ctx
->Depth
.Clear
);
148 case MESA_FORMAT_Z_UNORM16
:
149 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
151 * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
152 * enabled (the legacy method of clearing must be performed):
154 * - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
155 * width of the map (LOD0) is not multiple of 16, fast clear
156 * optimization must be disabled.
159 (minify(mt
->physical_width0
,
160 depth_irb
->mt_level
- mt
->first_level
) % 16) != 0)
166 depth_clear_value
= float_as_int(ctx
->Depth
.Clear
);
168 depth_clear_value
= fb
->_DepthMax
* ctx
->Depth
.Clear
;
172 /* If we're clearing to a new clear value, then we need to resolve any clear
173 * flags out of the HiZ buffer into the real depth buffer.
175 if (mt
->depth_clear_value
!= depth_clear_value
) {
176 intel_miptree_all_slices_resolve_depth(brw
, mt
);
177 mt
->depth_clear_value
= depth_clear_value
;
180 /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
182 * "If other rendering operations have preceded this clear, a
183 * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
184 * must be issued before the rectangle primitive used for the depth
185 * buffer clear operation.
187 intel_batchbuffer_emit_mi_flush(brw
);
189 if (fb
->MaxNumLayers
> 0) {
190 unsigned num_layers
= depth_irb
->mt
->level
[depth_irb
->mt_level
].depth
;
191 for (unsigned layer
= 0; layer
< num_layers
; layer
++) {
192 intel_hiz_exec(brw
, mt
, depth_irb
->mt_level
, layer
,
193 GEN6_HIZ_OP_DEPTH_CLEAR
);
196 intel_hiz_exec(brw
, mt
, depth_irb
->mt_level
, depth_irb
->mt_layer
,
197 GEN6_HIZ_OP_DEPTH_CLEAR
);
201 /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
203 * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
204 * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
205 * followed by Depth FLUSH'
207 intel_batchbuffer_emit_mi_flush(brw
);
210 /* Now, the HiZ buffer contains data that needs to be resolved to the depth
213 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
219 * Called by ctx->Driver.Clear.
222 brw_clear(struct gl_context
*ctx
, GLbitfield mask
)
224 struct brw_context
*brw
= brw_context(ctx
);
225 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
226 bool partial_clear
= ctx
->Scissor
.EnableFlags
&& !noop_scissor(ctx
, fb
);
228 if (!_mesa_check_conditional_render(ctx
))
231 if (mask
& (BUFFER_BIT_FRONT_LEFT
| BUFFER_BIT_FRONT_RIGHT
)) {
232 brw
->front_buffer_dirty
= true;
235 intel_prepare_render(brw
);
236 brw_workaround_depthstencil_alignment(brw
, partial_clear
? 0 : mask
);
238 if (mask
& BUFFER_BIT_DEPTH
) {
239 if (brw_fast_clear_depth(ctx
)) {
240 DBG("fast clear: depth\n");
241 mask
&= ~BUFFER_BIT_DEPTH
;
245 /* BLORP is currently only supported on Gen6+. */
246 if (brw
->gen
>= 6 && brw
->gen
< 8) {
247 if (mask
& BUFFER_BITS_COLOR
) {
248 if (brw_blorp_clear_color(brw
, fb
, partial_clear
)) {
249 debug_mask("blorp color", mask
& BUFFER_BITS_COLOR
);
250 mask
&= ~BUFFER_BITS_COLOR
;
255 GLbitfield tri_mask
= mask
& (BUFFER_BITS_COLOR
|
260 debug_mask("tri", tri_mask
);
263 if (ctx
->API
== API_OPENGLES
) {
264 _mesa_meta_Clear(&brw
->ctx
, tri_mask
);
266 _mesa_meta_glsl_Clear(&brw
->ctx
, tri_mask
);
270 /* Any strange buffers get passed off to swrast */
272 debug_mask("swrast", mask
);
273 _swrast_Clear(ctx
, mask
);
279 intelInitClearFuncs(struct dd_function_table
*functions
)
281 functions
->Clear
= brw_clear
;