src/mesa/drivers/dri/i965/brw_clear.c

   1 /*
   2  * Copyright 2003 VMware, Inc.
   3  * Copyright 2009, 2012 Intel Corporation.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "main/condrender.h"
  29 #include "swrast/swrast.h"
  30 #include "drivers/common/meta.h"
  31
  32 #include "intel_batchbuffer.h"
  33 #include "intel_blit.h"
  34 #include "intel_fbo.h"
  35 #include "intel_mipmap_tree.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_blorp.h"
  39 #include "brw_defines.h"
  40
  41 #define FILE_DEBUG_FLAG DEBUG_BLIT
  42
  43 static const char *buffer_names[] = {
  44    [BUFFER_FRONT_LEFT] = "front",
  45    [BUFFER_BACK_LEFT] = "back",
  46    [BUFFER_FRONT_RIGHT] = "front right",
  47    [BUFFER_BACK_RIGHT] = "back right",
  48    [BUFFER_DEPTH] = "depth",
  49    [BUFFER_STENCIL] = "stencil",
  50    [BUFFER_ACCUM] = "accum",
  51    [BUFFER_AUX0] = "aux0",
  52    [BUFFER_COLOR0] = "color0",
  53    [BUFFER_COLOR1] = "color1",
  54    [BUFFER_COLOR2] = "color2",
  55    [BUFFER_COLOR3] = "color3",
  56    [BUFFER_COLOR4] = "color4",
  57    [BUFFER_COLOR5] = "color5",
  58    [BUFFER_COLOR6] = "color6",
  59    [BUFFER_COLOR7] = "color7",
  60 };
  61
  62 static void
  63 debug_mask(const char *name, GLbitfield mask)
  64 {
  65    GLuint i;
  66
  67    if (unlikely(INTEL_DEBUG & DEBUG_BLIT)) {
  68       DBG("%s clear:", name);
  69       for (i = 0; i < BUFFER_COUNT; i++) {
  70          if (mask & (1 << i))
  71             DBG(" %s", buffer_names[i]);
  72       }
  73       DBG("\n");
  74    }
  75 }
  76
  77 /**
  78  * Returns true if the scissor is a noop (cuts out nothing).
  79  */
  80 static bool
  81 noop_scissor(struct gl_framebuffer *fb)
  82 {
  83    return fb->_Xmin <= 0 &&
  84           fb->_Ymin <= 0 &&
  85           fb->_Xmax >= fb->Width &&
  86           fb->_Ymax >= fb->Height;
  87 }
  88
  89 /**
  90  * Implements fast depth clears on gen6+.
  91  *
  92  * Fast clears basically work by setting a flag in each of the subspans
  93  * represented in the HiZ buffer that says "When you need the depth values for
  94  * this subspan, it's the hardware's current clear value."  Then later rendering
  95  * can just use the static clear value instead of referencing memory.
  96  *
  97  * The tricky part of the implementation is that you have to have the clear
  98  * value that was used on the depth buffer in place for all further rendering,
  99  * at least until a resolve to the real depth buffer happens.
 100  */
 101 static bool
 102 brw_fast_clear_depth(struct gl_context *ctx)
 103 {
 104    struct brw_context *brw = brw_context(ctx);
 105    struct gl_framebuffer *fb = ctx->DrawBuffer;
 106    struct intel_renderbuffer *depth_irb =
 107       intel_get_renderbuffer(fb, BUFFER_DEPTH);
 108    struct intel_mipmap_tree *mt = depth_irb->mt;
 109    struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
 110
 111    if (brw->gen < 6)
 112       return false;
 113
 114    if (!intel_renderbuffer_has_hiz(depth_irb))
 115       return false;
 116
 117    /* We only handle full buffer clears -- otherwise you'd have to track whether
 118     * a previous clear had happened at a different clear value and resolve it
 119     * first.
 120     */
 121    if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
 122       perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
 123                  "Possible 5%% performance win if avoided.\n",
 124                  mt->logical_width0, mt->logical_height0);
 125       return false;
 126    }
 127
 128    switch (mt->format) {
 129    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
 130    case MESA_FORMAT_Z24_UNORM_S8_UINT:
 131       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
 132        *
 133        *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
 134        *      enabled (the legacy method of clearing must be performed):
 135        *
 136        *      - If the depth buffer format is D32_FLOAT_S8X24_UINT or
 137        *        D24_UNORM_S8_UINT.
 138        */
 139       return false;
 140
 141    case MESA_FORMAT_Z_UNORM16:
 142       /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
 143        *
 144        *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
 145        *      enabled (the legacy method of clearing must be performed):
 146        *
 147        *      - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
 148        *        width of the map (LOD0) is not multiple of 16, fast clear
 149        *        optimization must be disabled.
 150        */
 151       if (brw->gen == 6 &&
 152           (minify(mt->physical_width0,
 153                   depth_irb->mt_level - mt->first_level) % 16) != 0)
 154          return false;
 155       break;
 156
 157    default:
 158       break;
 159    }
 160
 161    /* If we're clearing to a new clear value, then we need to resolve any clear
 162     * flags out of the HiZ buffer into the real depth buffer.
 163     */
 164    if (mt->fast_clear_color.f32[0] != ctx->Depth.Clear) {
 165       intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
 166                                    0, INTEL_REMAINING_LAYERS, true, false);
 167       mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
 168    }
 169
 170    if (depth_att->Layered) {
 171       intel_hiz_exec(brw, mt, depth_irb->mt_level,
 172                      depth_irb->mt_layer, depth_irb->layer_count,
 173                      BLORP_HIZ_OP_DEPTH_CLEAR);
 174    } else {
 175       intel_hiz_exec(brw, mt, depth_irb->mt_level, depth_irb->mt_layer, 1,
 176                      BLORP_HIZ_OP_DEPTH_CLEAR);
 177    }
 178
 179    /* Now, the HiZ buffer contains data that needs to be resolved to the depth
 180     * buffer.
 181     */
 182    if (depth_att->Layered) {
 183       intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
 184                                   depth_irb->mt_layer, depth_irb->layer_count,
 185                                   ISL_AUX_STATE_CLEAR);
 186    } else {
 187       intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
 188                                   depth_irb->mt_layer, 1,
 189                                   ISL_AUX_STATE_CLEAR);
 190    }
 191
 192    return true;
 193 }
 194
 195 /**
 196  * Called by ctx->Driver.Clear.
 197  */
 198 static void
 199 brw_clear(struct gl_context *ctx, GLbitfield mask)
 200 {
 201    struct brw_context *brw = brw_context(ctx);
 202    struct gl_framebuffer *fb = ctx->DrawBuffer;
 203    bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
 204
 205    if (!_mesa_check_conditional_render(ctx))
 206       return;
 207
 208    if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
 209       brw->front_buffer_dirty = true;
 210    }
 211
 212    intel_prepare_render(brw);
 213    brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
 214
 215    if (mask & BUFFER_BIT_DEPTH) {
 216       if (brw_fast_clear_depth(ctx)) {
 217          DBG("fast clear: depth\n");
 218          mask &= ~BUFFER_BIT_DEPTH;
 219       }
 220    }
 221
 222    if (mask & BUFFER_BIT_STENCIL) {
 223       struct intel_renderbuffer *stencil_irb =
 224          intel_get_renderbuffer(fb, BUFFER_STENCIL);
 225       struct intel_mipmap_tree *mt = stencil_irb->mt;
 226       if (mt && mt->stencil_mt)
 227          mt->stencil_mt->r8stencil_needs_update = true;
 228    }
 229
 230    if (mask & BUFFER_BITS_COLOR) {
 231       brw_blorp_clear_color(brw, fb, mask, partial_clear,
 232                             ctx->Color.sRGBEnabled);
 233       debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
 234       mask &= ~BUFFER_BITS_COLOR;
 235    }
 236
 237    if (brw->gen >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
 238       brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
 239       debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
 240       mask &= ~BUFFER_BITS_DEPTH_STENCIL;
 241    }
 242
 243    GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
 244                                  BUFFER_BIT_DEPTH);
 245
 246    if (tri_mask) {
 247       debug_mask("tri", tri_mask);
 248       mask &= ~tri_mask;
 249       _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
 250    }
 251
 252    /* Any strange buffers get passed off to swrast.  The only thing that
 253     * should be left at this point is the accumulation buffer.
 254     */
 255    assert((mask & ~BUFFER_BIT_ACCUM) == 0);
 256    if (mask) {
 257       debug_mask("swrast", mask);
 258       _swrast_Clear(ctx, mask);
 259    }
 260 }
 261
 262
 263 void
 264 intelInitClearFuncs(struct dd_function_table *functions)
 265 {
 266    functions->Clear = brw_clear;
 267 }