i965: Clarify nomenclature: vert_result -> varying
[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_line.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "main/glheader.h"
33 #include "main/macros.h"
34 #include "main/enums.h"
35 #include "program/program.h"
36
37 #include "intel_batchbuffer.h"
38
39 #include "brw_defines.h"
40 #include "brw_context.h"
41 #include "brw_eu.h"
42 #include "brw_clip.h"
43
44
45
46 static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
47 {
48 struct intel_context *intel = &c->func.brw->intel;
49 GLuint i = 0,j;
50
51 /* Register usage is static, precompute here:
52 */
53 c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
54
55 if (c->key.nr_userclip) {
56 c->reg.fixed_planes = brw_vec4_grf(i, 0);
57 i += (6 + c->key.nr_userclip + 1) / 2;
58
59 c->prog_data.curb_read_length = (6 + c->key.nr_userclip + 1) / 2;
60 }
61 else
62 c->prog_data.curb_read_length = 0;
63
64
65 /* Payload vertices plus space for more generated vertices:
66 */
67 for (j = 0; j < 4; j++) {
68 c->reg.vertex[j] = brw_vec4_grf(i, 0);
69 i += c->nr_regs;
70 }
71
72 c->reg.t = brw_vec1_grf(i, 0);
73 c->reg.t0 = brw_vec1_grf(i, 1);
74 c->reg.t1 = brw_vec1_grf(i, 2);
75 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD);
76 c->reg.plane_equation = brw_vec4_grf(i, 4);
77 i++;
78
79 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */
80 c->reg.dp1 = brw_vec1_grf(i, 4);
81 i++;
82
83 if (!c->key.nr_userclip) {
84 c->reg.fixed_planes = brw_vec8_grf(i, 0);
85 i++;
86 }
87
88 if (intel->needs_ff_sync) {
89 c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD);
90 i++;
91 }
92
93 c->first_tmp = i;
94 c->last_tmp = i;
95
96 c->prog_data.urb_read_length = c->nr_regs; /* ? */
97 c->prog_data.total_grf = i;
98 }
99
100
101
102 /* Line clipping, more or less following the following algorithm:
103 *
104 * for (p=0;p<MAX_PLANES;p++) {
105 * if (clipmask & (1 << p)) {
106 * GLfloat dp0 = DOTPROD( vtx0, plane[p] );
107 * GLfloat dp1 = DOTPROD( vtx1, plane[p] );
108 *
109 * if (IS_NEGATIVE(dp1)) {
110 * GLfloat t = dp1 / (dp1 - dp0);
111 * if (t > t1) t1 = t;
112 * } else {
113 * GLfloat t = dp0 / (dp0 - dp1);
114 * if (t > t0) t0 = t;
115 * }
116 *
117 * if (t0 + t1 >= 1.0)
118 * return;
119 * }
120 * }
121 *
122 * interp( ctx, newvtx0, vtx0, vtx1, t0 );
123 * interp( ctx, newvtx1, vtx1, vtx0, t1 );
124 *
125 */
126 static void clip_and_emit_line( struct brw_clip_compile *c )
127 {
128 struct brw_compile *p = &c->func;
129 struct brw_context *brw = p->brw;
130 struct brw_indirect vtx0 = brw_indirect(0, 0);
131 struct brw_indirect vtx1 = brw_indirect(1, 0);
132 struct brw_indirect newvtx0 = brw_indirect(2, 0);
133 struct brw_indirect newvtx1 = brw_indirect(3, 0);
134 struct brw_indirect plane_ptr = brw_indirect(4, 0);
135 struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
136 GLuint hpos_offset = brw_varying_to_offset(&c->vue_map, VARYING_SLOT_POS);
137
138 brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0]));
139 brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1]));
140 brw_MOV(p, get_addr_reg(newvtx0), brw_address(c->reg.vertex[2]));
141 brw_MOV(p, get_addr_reg(newvtx1), brw_address(c->reg.vertex[3]));
142 brw_MOV(p, get_addr_reg(plane_ptr), brw_clip_plane0_address(c));
143
144 /* Note: init t0, t1 together:
145 */
146 brw_MOV(p, vec2(c->reg.t0), brw_imm_f(0));
147
148 brw_clip_init_planes(c);
149 brw_clip_init_clipmask(c);
150
151 /* -ve rhw workaround */
152 if (brw->has_negative_rhw_bug) {
153 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
154 brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
155 brw_imm_ud(1<<20));
156 brw_OR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(0x3f));
157 }
158
159 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
160
161 brw_DO(p, BRW_EXECUTE_1);
162 {
163 /* if (planemask & 1)
164 */
165 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
166 brw_AND(p, v1_null_ud, c->reg.planemask, brw_imm_ud(1));
167
168 brw_IF(p, BRW_EXECUTE_1);
169 {
170 if (c->key.nr_userclip)
171 brw_MOV(p, c->reg.plane_equation, deref_4f(plane_ptr, 0));
172 else
173 brw_MOV(p, c->reg.plane_equation, deref_4b(plane_ptr, 0));
174
175 /* dp = DP4(vtx->position, plane)
176 */
177 brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, hpos_offset), c->reg.plane_equation);
178
179 /* if (IS_NEGATIVE(dp1))
180 */
181 brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
182 brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, hpos_offset), c->reg.plane_equation);
183 brw_IF(p, BRW_EXECUTE_1);
184 {
185 /*
186 * Both can be negative on GM965/G965 due to RHW workaround
187 * if so, this object should be rejected.
188 */
189 if (brw->has_negative_rhw_bug) {
190 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
191 brw_IF(p, BRW_EXECUTE_1);
192 {
193 brw_clip_kill_thread(c);
194 }
195 brw_ENDIF(p);
196 }
197
198 brw_ADD(p, c->reg.t, c->reg.dp1, negate(c->reg.dp0));
199 brw_math_invert(p, c->reg.t, c->reg.t);
200 brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp1);
201
202 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t1 );
203 brw_MOV(p, c->reg.t1, c->reg.t);
204 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
205 }
206 brw_ELSE(p);
207 {
208 /* Coming back in. We know that both cannot be negative
209 * because the line would have been culled in that case.
210 */
211
212 /* If both are positive, do nothing */
213 /* Only on GM965/G965 */
214 if (brw->has_negative_rhw_bug) {
215 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
216 brw_IF(p, BRW_EXECUTE_1);
217 }
218
219 {
220 brw_ADD(p, c->reg.t, c->reg.dp0, negate(c->reg.dp1));
221 brw_math_invert(p, c->reg.t, c->reg.t);
222 brw_MUL(p, c->reg.t, c->reg.t, c->reg.dp0);
223
224 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_G, c->reg.t, c->reg.t0 );
225 brw_MOV(p, c->reg.t0, c->reg.t);
226 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
227 }
228
229 if (brw->has_negative_rhw_bug) {
230 brw_ENDIF(p);
231 }
232 }
233 brw_ENDIF(p);
234 }
235 brw_ENDIF(p);
236
237 /* plane_ptr++;
238 */
239 brw_ADD(p, get_addr_reg(plane_ptr), get_addr_reg(plane_ptr), brw_clip_plane_stride(c));
240
241 /* while (planemask>>=1) != 0
242 */
243 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
244 brw_SHR(p, c->reg.planemask, c->reg.planemask, brw_imm_ud(1));
245 }
246 brw_WHILE(p);
247
248 brw_ADD(p, c->reg.t, c->reg.t0, c->reg.t1);
249 brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0));
250 brw_IF(p, BRW_EXECUTE_1);
251 {
252 brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, false);
253 brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, false);
254
255 brw_clip_emit_vue(c, newvtx0, 1, 0,
256 (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
257 | URB_WRITE_PRIM_START);
258 brw_clip_emit_vue(c, newvtx1, 0, 1,
259 (_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
260 | URB_WRITE_PRIM_END);
261 }
262 brw_ENDIF(p);
263 brw_clip_kill_thread(c);
264 }
265
266
267
268 void brw_emit_line_clip( struct brw_clip_compile *c )
269 {
270 brw_clip_line_alloc_regs(c);
271 brw_clip_init_ff_sync(c);
272
273 if (c->key.do_flat_shading) {
274 if (c->key.pv_first)
275 brw_clip_copy_colors(c, 1, 0);
276 else
277 brw_clip_copy_colors(c, 0, 1);
278 }
279
280 clip_and_emit_line(c);
281 }