src/mesa/drivers/dri/i965/brw_clip_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35
  36 static void
  37 brw_prepare_clip_unit(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    struct gl_context *ctx = &intel->ctx;
  41    struct brw_clip_unit_state *clip;
  42
  43    clip = brw_state_batch(brw, sizeof(*clip), 32, &brw->clip.state_offset);
  44    memset(clip, 0, sizeof(*clip));
  45
  46    /* CACHE_NEW_CLIP_PROG */
  47    clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
  48                                  16 - 1);
  49    /* reloc */
  50    clip->thread0.kernel_start_pointer = brw->clip.prog_bo->offset >> 6;
  51
  52    clip->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  53    clip->thread1.single_program_flow = 1;
  54
  55    clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
  56    clip->thread3.const_urb_entry_read_length =
  57       brw->clip.prog_data->curb_read_length;
  58
  59    /* BRW_NEW_CURBE_OFFSETS */
  60    clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  61    clip->thread3.dispatch_grf_start_reg = 1;
  62    clip->thread3.urb_entry_read_offset = 0;
  63
  64    /* BRW_NEW_URB_FENCE */
  65    clip->thread4.nr_urb_entries = brw->urb.nr_clip_entries;
  66    clip->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
  67    /* If we have enough clip URB entries to run two threads, do so.
  68     */
  69    if (brw->urb.nr_clip_entries >= 10) {
  70       /* Half of the URB entries go to each thread, and it has to be an
  71        * even number.
  72        */
  73       assert(brw->urb.nr_clip_entries % 2 == 0);
  74
  75       /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
  76        * only 2 threads can output VUEs at a time.
  77        */
  78       if (intel->gen == 5)
  79          clip->thread4.max_threads = 16 - 1;
  80       else
  81          clip->thread4.max_threads = 2 - 1;
  82    } else {
  83       assert(brw->urb.nr_clip_entries >= 5);
  84       clip->thread4.max_threads = 1 - 1;
  85    }
  86
  87    if (unlikely(INTEL_DEBUG & DEBUG_SINGLE_THREAD))
  88       clip->thread4.max_threads = 0;
  89
  90    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
  91       clip->thread4.stats_enable = 1;
  92
  93    clip->clip5.userclip_enable_flags = 0x7f;
  94    clip->clip5.userclip_must_clip = 1;
  95    clip->clip5.guard_band_enable = 0;
  96    /* _NEW_TRANSOFORM */
  97    if (!ctx->Transform.DepthClamp)
  98       clip->clip5.viewport_z_clip_enable = 1;
  99    clip->clip5.viewport_xy_clip_enable = 1;
 100    clip->clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
 101    clip->clip5.api_mode = BRW_CLIP_API_OGL;
 102    clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
 103
 104    if (intel->is_g4x)
 105       clip->clip5.negative_w_clip_test = 1;
 106
 107    clip->clip6.clipper_viewport_state_ptr = 0;
 108    clip->viewport_xmin = -1;
 109    clip->viewport_xmax = 1;
 110    clip->viewport_ymin = -1;
 111    clip->viewport_ymax = 1;
 112
 113    /* Emit clip program relocation */
 114    assert(brw->clip.prog_bo);
 115    drm_intel_bo_emit_reloc(intel->batch.bo,
 116                            (brw->clip.state_offset +
 117                             offsetof(struct brw_clip_unit_state, thread0)),
 118                            brw->clip.prog_bo, clip->thread0.grf_reg_count << 1,
 119                            I915_GEM_DOMAIN_INSTRUCTION, 0);
 120
 121    brw->state.dirty.cache |= CACHE_NEW_CLIP_UNIT;
 122 }
 123
 124 const struct brw_tracked_state brw_clip_unit = {
 125    .dirty = {
 126       .mesa  = _NEW_TRANSFORM,
 127       .brw   = (BRW_NEW_BATCH |
 128                 BRW_NEW_CURBE_OFFSETS |
 129                 BRW_NEW_URB_FENCE),
 130       .cache = CACHE_NEW_CLIP_PROG
 131    },
 132    .prepare = brw_prepare_clip_unit,
 133 };