2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
32 #include "brw_context.h"
33 #include "brw_state.h"
34 #include "brw_defines.h"
36 struct brw_clip_unit_key
{
37 unsigned int total_grf
;
38 unsigned int urb_entry_read_length
;
39 unsigned int curb_entry_read_length
;
40 unsigned int clip_mode
;
42 unsigned int curbe_offset
;
44 unsigned int nr_urb_entries
, urb_size
;
46 GLboolean depth_clamp
;
50 clip_unit_populate_key(struct brw_context
*brw
, struct brw_clip_unit_key
*key
)
52 struct gl_context
*ctx
= &brw
->intel
.ctx
;
53 memset(key
, 0, sizeof(*key
));
55 /* CACHE_NEW_CLIP_PROG */
56 key
->total_grf
= brw
->clip
.prog_data
->total_grf
;
57 key
->urb_entry_read_length
= brw
->clip
.prog_data
->urb_read_length
;
58 key
->curb_entry_read_length
= brw
->clip
.prog_data
->curb_read_length
;
59 key
->clip_mode
= brw
->clip
.prog_data
->clip_mode
;
61 /* BRW_NEW_CURBE_OFFSETS */
62 key
->curbe_offset
= brw
->curbe
.clip_start
;
64 /* BRW_NEW_URB_FENCE */
65 key
->nr_urb_entries
= brw
->urb
.nr_clip_entries
;
66 key
->urb_size
= brw
->urb
.vsize
;
69 key
->depth_clamp
= ctx
->Transform
.DepthClamp
;
73 clip_unit_create_from_key(struct brw_context
*brw
,
74 struct brw_clip_unit_key
*key
)
76 struct intel_context
*intel
= &brw
->intel
;
77 struct brw_clip_unit_state clip
;
80 memset(&clip
, 0, sizeof(clip
));
82 clip
.thread0
.grf_reg_count
= ALIGN(key
->total_grf
, 16) / 16 - 1;
84 clip
.thread0
.kernel_start_pointer
= brw
->clip
.prog_bo
->offset
>> 6;
86 clip
.thread1
.floating_point_mode
= BRW_FLOATING_POINT_NON_IEEE_754
;
87 clip
.thread1
.single_program_flow
= 1;
89 clip
.thread3
.urb_entry_read_length
= key
->urb_entry_read_length
;
90 clip
.thread3
.const_urb_entry_read_length
= key
->curb_entry_read_length
;
91 clip
.thread3
.const_urb_entry_read_offset
= key
->curbe_offset
* 2;
92 clip
.thread3
.dispatch_grf_start_reg
= 1;
93 clip
.thread3
.urb_entry_read_offset
= 0;
95 clip
.thread4
.nr_urb_entries
= key
->nr_urb_entries
;
96 clip
.thread4
.urb_entry_allocation_size
= key
->urb_size
- 1;
97 /* If we have enough clip URB entries to run two threads, do so.
99 if (key
->nr_urb_entries
>= 10) {
100 /* Half of the URB entries go to each thread, and it has to be an
103 assert(key
->nr_urb_entries
% 2 == 0);
105 /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
106 * only 2 threads can output VUEs at a time.
109 clip
.thread4
.max_threads
= 16 - 1;
111 clip
.thread4
.max_threads
= 2 - 1;
113 assert(key
->nr_urb_entries
>= 5);
114 clip
.thread4
.max_threads
= 1 - 1;
117 if (unlikely(INTEL_DEBUG
& DEBUG_SINGLE_THREAD
))
118 clip
.thread4
.max_threads
= 0;
120 if (unlikely(INTEL_DEBUG
& DEBUG_STATS
))
121 clip
.thread4
.stats_enable
= 1;
123 clip
.clip5
.userclip_enable_flags
= 0x7f;
124 clip
.clip5
.userclip_must_clip
= 1;
125 clip
.clip5
.guard_band_enable
= 0;
126 if (!key
->depth_clamp
)
127 clip
.clip5
.viewport_z_clip_enable
= 1;
128 clip
.clip5
.viewport_xy_clip_enable
= 1;
129 clip
.clip5
.vertex_position_space
= BRW_CLIP_NDCSPACE
;
130 clip
.clip5
.api_mode
= BRW_CLIP_API_OGL
;
131 clip
.clip5
.clip_mode
= key
->clip_mode
;
134 clip
.clip5
.negative_w_clip_test
= 1;
136 clip
.clip6
.clipper_viewport_state_ptr
= 0;
137 clip
.viewport_xmin
= -1;
138 clip
.viewport_xmax
= 1;
139 clip
.viewport_ymin
= -1;
140 clip
.viewport_ymax
= 1;
142 bo
= brw_upload_cache(&brw
->cache
, BRW_CLIP_UNIT
,
144 &brw
->clip
.prog_bo
, 1,
145 &clip
, sizeof(clip
));
147 /* Emit clip program relocation */
148 assert(brw
->clip
.prog_bo
);
149 drm_intel_bo_emit_reloc(bo
, offsetof(struct brw_clip_unit_state
, thread0
),
150 brw
->clip
.prog_bo
, clip
.thread0
.grf_reg_count
<< 1,
151 I915_GEM_DOMAIN_INSTRUCTION
, 0);
156 static void upload_clip_unit( struct brw_context
*brw
)
158 struct brw_clip_unit_key key
;
160 clip_unit_populate_key(brw
, &key
);
162 drm_intel_bo_unreference(brw
->clip
.state_bo
);
163 brw
->clip
.state_bo
= brw_search_cache(&brw
->cache
, BRW_CLIP_UNIT
,
165 &brw
->clip
.prog_bo
, 1,
167 if (brw
->clip
.state_bo
== NULL
) {
168 brw
->clip
.state_bo
= clip_unit_create_from_key(brw
, &key
);
172 const struct brw_tracked_state brw_clip_unit
= {
174 .mesa
= _NEW_TRANSFORM
,
175 .brw
= (BRW_NEW_CURBE_OFFSETS
|
177 .cache
= CACHE_NEW_CLIP_PROG
179 .prepare
= upload_clip_unit
,