src/mesa/drivers/dri/i965/brw_clip_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #include "intel_batchbuffer.h"
  33 #include "brw_context.h"
  34 #include "brw_state.h"
  35 #include "brw_defines.h"
  36 #include "main/framebuffer.h"
  37
  38 static void
  39 brw_upload_clip_unit(struct brw_context *brw)
  40 {
  41    struct gl_context *ctx = &brw->ctx;
  42    struct brw_clip_unit_state *clip;
  43
  44    clip = brw_state_batch(brw, sizeof(*clip), 32, &brw->clip.state_offset);
  45    memset(clip, 0, sizeof(*clip));
  46
  47    /* BRW_NEW_PROGRAM_CACHE | BRW_NEW_CLIP_PROG_DATA */
  48    clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
  49                                  16 - 1);
  50    clip->thread0.kernel_start_pointer =
  51       brw_program_reloc(brw,
  52                         brw->clip.state_offset +
  53                         offsetof(struct brw_clip_unit_state, thread0),
  54                         brw->clip.prog_offset +
  55                         (clip->thread0.grf_reg_count << 1)) >> 6;
  56
  57    clip->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  58    clip->thread1.single_program_flow = 1;
  59
  60    clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
  61    clip->thread3.const_urb_entry_read_length =
  62       brw->clip.prog_data->curb_read_length;
  63
  64    /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
  65    clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  66    clip->thread3.dispatch_grf_start_reg = 1;
  67    clip->thread3.urb_entry_read_offset = 0;
  68
  69    /* BRW_NEW_URB_FENCE */
  70    clip->thread4.nr_urb_entries = brw->urb.nr_clip_entries;
  71    clip->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
  72    /* If we have enough clip URB entries to run two threads, do so.
  73     */
  74    if (brw->urb.nr_clip_entries >= 10) {
  75       /* Half of the URB entries go to each thread, and it has to be an
  76        * even number.
  77        */
  78       assert(brw->urb.nr_clip_entries % 2 == 0);
  79
  80       /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
  81        * only 2 threads can output VUEs at a time.
  82        */
  83       if (brw->gen == 5)
  84          clip->thread4.max_threads = 16 - 1;
  85       else
  86          clip->thread4.max_threads = 2 - 1;
  87    } else {
  88       assert(brw->urb.nr_clip_entries >= 5);
  89       clip->thread4.max_threads = 1 - 1;
  90    }
  91
  92    /* _NEW_TRANSFORM */
  93    if (brw->gen == 5 || brw->is_g4x)
  94       clip->clip5.userclip_enable_flags = ctx->Transform.ClipPlanesEnabled;
  95    else
  96       /* Up to 6 actual clip flags, plus the 7th for negative RHW workaround. */
  97       clip->clip5.userclip_enable_flags = (ctx->Transform.ClipPlanesEnabled & 0x3f) | 0x40;
  98
  99    clip->clip5.userclip_must_clip = 1;
 100
 101    /* enable guardband clipping if we can */
 102    clip->clip5.guard_band_enable = 1;
 103    clip->clip6.clipper_viewport_state_ptr =
 104       (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
 105
 106    /* emit clip viewport relocation */
 107    brw_emit_reloc(&brw->batch,
 108                   (brw->clip.state_offset +
 109                    offsetof(struct brw_clip_unit_state, clip6)),
 110                   brw->batch.bo, brw->clip.vp_offset,
 111                   I915_GEM_DOMAIN_INSTRUCTION, 0);
 112
 113    /* _NEW_TRANSFORM */
 114    if (!ctx->Transform.DepthClamp)
 115       clip->clip5.viewport_z_clip_enable = 1;
 116    clip->clip5.viewport_xy_clip_enable = 1;
 117    clip->clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
 118    if (ctx->Transform.ClipDepthMode == GL_ZERO_TO_ONE)
 119       clip->clip5.api_mode = BRW_CLIP_API_DX;
 120    else
 121       clip->clip5.api_mode = BRW_CLIP_API_OGL;
 122    clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
 123
 124    if (brw->is_g4x)
 125       clip->clip5.negative_w_clip_test = 1;
 126
 127    clip->viewport_xmin = -1;
 128    clip->viewport_xmax = 1;
 129    clip->viewport_ymin = -1;
 130    clip->viewport_ymax = 1;
 131
 132    brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
 133 }
 134
 135 const struct brw_tracked_state brw_clip_unit = {
 136    .dirty = {
 137       .mesa  = _NEW_TRANSFORM |
 138                _NEW_VIEWPORT,
 139       .brw   = BRW_NEW_BATCH |
 140                BRW_NEW_BLORP |
 141                BRW_NEW_CLIP_PROG_DATA |
 142                BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 143                BRW_NEW_PROGRAM_CACHE |
 144                BRW_NEW_URB_FENCE,
 145    },
 146    .emit = brw_upload_clip_unit,
 147 };