src/mesa/drivers/dri/i965/brw_clip_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35
  36 static void
  37 upload_clip_vp(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    struct gl_context *ctx = &intel->ctx;
  41    struct brw_clipper_viewport *vp;
  42
  43    vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
  44                         sizeof(*vp), 32, &brw->clip.vp_offset);
  45
  46    const float maximum_post_clamp_delta = 4096;
  47    float gbx = maximum_post_clamp_delta / (float) ctx->Viewport.Width;
  48    float gby = maximum_post_clamp_delta / (float) ctx->Viewport.Height;
  49
  50    vp->xmin = -gbx;
  51    vp->xmax = gbx;
  52    vp->ymin = -gby;
  53    vp->ymax = gby;
  54 }
  55
  56 static void
  57 brw_upload_clip_unit(struct brw_context *brw)
  58 {
  59    struct intel_context *intel = &brw->intel;
  60    struct gl_context *ctx = &intel->ctx;
  61    struct brw_clip_unit_state *clip;
  62
  63    /* _NEW_BUFFERS */
  64    struct gl_framebuffer *fb = ctx->DrawBuffer;
  65
  66    upload_clip_vp(brw);
  67
  68    clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
  69                           sizeof(*clip), 32, &brw->clip.state_offset);
  70    memset(clip, 0, sizeof(*clip));
  71
  72    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_CLIP_PROG */
  73    clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
  74                                  16 - 1);
  75    clip->thread0.kernel_start_pointer =
  76       brw_program_reloc(brw,
  77                         brw->clip.state_offset +
  78                         offsetof(struct brw_clip_unit_state, thread0),
  79                         brw->clip.prog_offset +
  80                         (clip->thread0.grf_reg_count << 1)) >> 6;
  81
  82    clip->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  83    clip->thread1.single_program_flow = 1;
  84
  85    clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
  86    clip->thread3.const_urb_entry_read_length =
  87       brw->clip.prog_data->curb_read_length;
  88
  89    /* BRW_NEW_CURBE_OFFSETS */
  90    clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  91    clip->thread3.dispatch_grf_start_reg = 1;
  92    clip->thread3.urb_entry_read_offset = 0;
  93
  94    /* BRW_NEW_URB_FENCE */
  95    clip->thread4.nr_urb_entries = brw->urb.nr_clip_entries;
  96    clip->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
  97    /* If we have enough clip URB entries to run two threads, do so.
  98     */
  99    if (brw->urb.nr_clip_entries >= 10) {
 100       /* Half of the URB entries go to each thread, and it has to be an
 101        * even number.
 102        */
 103       assert(brw->urb.nr_clip_entries % 2 == 0);
 104
 105       /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
 106        * only 2 threads can output VUEs at a time.
 107        */
 108       if (intel->gen == 5)
 109          clip->thread4.max_threads = 16 - 1;
 110       else
 111          clip->thread4.max_threads = 2 - 1;
 112    } else {
 113       assert(brw->urb.nr_clip_entries >= 5);
 114       clip->thread4.max_threads = 1 - 1;
 115    }
 116
 117    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 118       clip->thread4.stats_enable = 1;
 119
 120    clip->clip5.userclip_enable_flags = 0x7f;
 121    clip->clip5.userclip_must_clip = 1;
 122
 123    /* enable guardband clipping if we can */
 124    if (ctx->Viewport.X == 0 &&
 125        ctx->Viewport.Y == 0 &&
 126        ctx->Viewport.Width == fb->Width &&
 127        ctx->Viewport.Height == fb->Height)
 128    {
 129       clip->clip5.guard_band_enable = 1;
 130       clip->clip6.clipper_viewport_state_ptr =
 131          (brw->batch.bo->offset + brw->clip.vp_offset) >> 5;
 132
 133       /* emit clip viewport relocation */
 134       drm_intel_bo_emit_reloc(brw->batch.bo,
 135                               (brw->clip.state_offset +
 136                                offsetof(struct brw_clip_unit_state, clip6)),
 137                               brw->batch.bo, brw->clip.vp_offset,
 138                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 139    }
 140
 141    /* _NEW_TRANSFORM */
 142    if (!ctx->Transform.DepthClamp)
 143       clip->clip5.viewport_z_clip_enable = 1;
 144    clip->clip5.viewport_xy_clip_enable = 1;
 145    clip->clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
 146    clip->clip5.api_mode = BRW_CLIP_API_OGL;
 147    clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
 148
 149    if (intel->is_g4x)
 150       clip->clip5.negative_w_clip_test = 1;
 151
 152    clip->viewport_xmin = -1;
 153    clip->viewport_xmax = 1;
 154    clip->viewport_ymin = -1;
 155    clip->viewport_ymax = 1;
 156
 157    brw->state.dirty.cache |= CACHE_NEW_CLIP_UNIT;
 158 }
 159
 160 const struct brw_tracked_state brw_clip_unit = {
 161    .dirty = {
 162       .mesa  = _NEW_TRANSFORM | _NEW_BUFFERS | _NEW_VIEWPORT,
 163       .brw   = (BRW_NEW_BATCH |
 164                 BRW_NEW_PROGRAM_CACHE |
 165                 BRW_NEW_CURBE_OFFSETS |
 166                 BRW_NEW_URB_FENCE),
 167       .cache = CACHE_NEW_CLIP_PROG
 168    },
 169    .emit = brw_upload_clip_unit,
 170 };