Merge remote branch 'origin/master' into lp-binning
[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #include "brw_context.h"
33 #include "brw_state.h"
34 #include "brw_defines.h"
35 #include "main/macros.h"
36
37 struct brw_clip_unit_key {
38 unsigned int total_grf;
39 unsigned int urb_entry_read_length;
40 unsigned int curb_entry_read_length;
41 unsigned int clip_mode;
42
43 unsigned int curbe_offset;
44
45 unsigned int nr_urb_entries, urb_size;
46
47 GLboolean depth_clamp;
48 };
49
50 static void
51 clip_unit_populate_key(struct brw_context *brw, struct brw_clip_unit_key *key)
52 {
53 GLcontext *ctx = &brw->intel.ctx;
54 memset(key, 0, sizeof(*key));
55
56 /* CACHE_NEW_CLIP_PROG */
57 key->total_grf = brw->clip.prog_data->total_grf;
58 key->urb_entry_read_length = brw->clip.prog_data->urb_read_length;
59 key->curb_entry_read_length = brw->clip.prog_data->curb_read_length;
60 key->clip_mode = brw->clip.prog_data->clip_mode;
61
62 /* BRW_NEW_CURBE_OFFSETS */
63 key->curbe_offset = brw->curbe.clip_start;
64
65 /* BRW_NEW_URB_FENCE */
66 key->nr_urb_entries = brw->urb.nr_clip_entries;
67 key->urb_size = brw->urb.vsize;
68
69 /* _NEW_TRANSOFORM */
70 key->depth_clamp = ctx->Transform.DepthClamp;
71 }
72
73 static dri_bo *
74 clip_unit_create_from_key(struct brw_context *brw,
75 struct brw_clip_unit_key *key)
76 {
77 struct intel_context *intel = &brw->intel;
78 struct brw_clip_unit_state clip;
79 dri_bo *bo;
80
81 memset(&clip, 0, sizeof(clip));
82
83 clip.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
84 /* reloc */
85 clip.thread0.kernel_start_pointer = brw->clip.prog_bo->offset >> 6;
86
87 clip.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
88 clip.thread1.single_program_flow = 1;
89
90 clip.thread3.urb_entry_read_length = key->urb_entry_read_length;
91 clip.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
92 clip.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
93 clip.thread3.dispatch_grf_start_reg = 1;
94 clip.thread3.urb_entry_read_offset = 0;
95
96 clip.thread4.nr_urb_entries = key->nr_urb_entries;
97 clip.thread4.urb_entry_allocation_size = key->urb_size - 1;
98 /* If we have enough clip URB entries to run two threads, do so.
99 */
100 if (key->nr_urb_entries >= 10) {
101 /* Half of the URB entries go to each thread, and it has to be an
102 * even number.
103 */
104 assert(key->nr_urb_entries % 2 == 0);
105
106 /* Although up to 16 concurrent Clip threads are allowed on IGDNG,
107 * only 2 threads can output VUEs at a time.
108 */
109 if (intel->is_ironlake)
110 clip.thread4.max_threads = 16 - 1;
111 else
112 clip.thread4.max_threads = 2 - 1;
113 } else {
114 assert(key->nr_urb_entries >= 5);
115 clip.thread4.max_threads = 1 - 1;
116 }
117
118 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
119 clip.thread4.max_threads = 0;
120
121 if (INTEL_DEBUG & DEBUG_STATS)
122 clip.thread4.stats_enable = 1;
123
124 clip.clip5.userclip_enable_flags = 0x7f;
125 clip.clip5.userclip_must_clip = 1;
126 clip.clip5.guard_band_enable = 0;
127 if (!key->depth_clamp)
128 clip.clip5.viewport_z_clip_enable = 1;
129 clip.clip5.viewport_xy_clip_enable = 1;
130 clip.clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
131 clip.clip5.api_mode = BRW_CLIP_API_OGL;
132 clip.clip5.clip_mode = key->clip_mode;
133
134 if (intel->is_g4x)
135 clip.clip5.negative_w_clip_test = 1;
136
137 clip.clip6.clipper_viewport_state_ptr = 0;
138 clip.viewport_xmin = -1;
139 clip.viewport_xmax = 1;
140 clip.viewport_ymin = -1;
141 clip.viewport_ymax = 1;
142
143 bo = brw_upload_cache(&brw->cache, BRW_CLIP_UNIT,
144 key, sizeof(*key),
145 &brw->clip.prog_bo, 1,
146 &clip, sizeof(clip),
147 NULL, NULL);
148
149 /* Emit clip program relocation */
150 assert(brw->clip.prog_bo);
151 dri_bo_emit_reloc(bo,
152 I915_GEM_DOMAIN_INSTRUCTION,
153 0,
154 clip.thread0.grf_reg_count << 1,
155 offsetof(struct brw_clip_unit_state, thread0),
156 brw->clip.prog_bo);
157
158 return bo;
159 }
160
161 static void upload_clip_unit( struct brw_context *brw )
162 {
163 struct brw_clip_unit_key key;
164
165 clip_unit_populate_key(brw, &key);
166
167 dri_bo_unreference(brw->clip.state_bo);
168 brw->clip.state_bo = brw_search_cache(&brw->cache, BRW_CLIP_UNIT,
169 &key, sizeof(key),
170 &brw->clip.prog_bo, 1,
171 NULL);
172 if (brw->clip.state_bo == NULL) {
173 brw->clip.state_bo = clip_unit_create_from_key(brw, &key);
174 }
175 }
176
177 const struct brw_tracked_state brw_clip_unit = {
178 .dirty = {
179 .mesa = _NEW_TRANSFORM,
180 .brw = (BRW_NEW_CURBE_OFFSETS |
181 BRW_NEW_URB_FENCE),
182 .cache = CACHE_NEW_CLIP_PROG
183 },
184 .prepare = upload_clip_unit,
185 };