src/mesa/drivers/dri/i965/brw_clip_util.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36 #include "program/program.h"
  37
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_clip.h"
  44
  45
  46
  47
  48 struct brw_reg get_tmp( struct brw_clip_compile *c )
  49 {
  50    struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
  51
  52    if (++c->last_tmp > c->prog_data.total_grf)
  53       c->prog_data.total_grf = c->last_tmp;
  54
  55    return tmp;
  56 }
  57
  58 static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp )
  59 {
  60    if (tmp.nr == c->last_tmp-1)
  61       c->last_tmp--;
  62 }
  63
  64
  65 static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w)
  66 {
  67    return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x);
  68 }
  69
  70
  71 void brw_clip_init_planes( struct brw_clip_compile *c )
  72 {
  73    struct brw_compile *p = &c->func;
  74
  75    if (!c->key.nr_userclip) {
  76       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0,    0, 0xff, 1));
  77       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0,    0,    1, 1));
  78       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff,    0, 1));
  79       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0,    1,    0, 1));
  80       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff,  0,    0, 1));
  81       brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1,    0,    0, 1));
  82    }
  83 }
  84
  85
  86
  87 #define W 3
  88
  89 /* Project 'pos' to screen space (or back again), overwrite with results:
  90  */
  91 void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
  92 {
  93    struct brw_compile *p = &c->func;
  94
  95    /* calc rhw
  96     */
  97    brw_math_invert(p, get_element(pos, W), get_element(pos, W));
  98
  99    /* value.xyz *= value.rhw
 100     */
 101    brw_set_access_mode(p, BRW_ALIGN_16);
 102    brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, brw_swizzle1(pos, W));
 103    brw_set_access_mode(p, BRW_ALIGN_1);
 104 }
 105
 106
 107 static void brw_clip_project_vertex( struct brw_clip_compile *c,
 108                                      struct brw_indirect vert_addr )
 109 {
 110    struct brw_compile *p = &c->func;
 111    struct brw_reg tmp = get_tmp(c);
 112    GLuint hpos_offset = brw_vert_result_to_offset(&c->vue_map,
 113                                                   VERT_RESULT_HPOS);
 114    GLuint ndc_offset = brw_vert_result_to_offset(&c->vue_map,
 115                                                  BRW_VERT_RESULT_NDC);
 116
 117    /* Fixup position.  Extract from the original vertex and re-project
 118     * to screen space:
 119     */
 120    brw_MOV(p, tmp, deref_4f(vert_addr, hpos_offset));
 121    brw_clip_project_position(c, tmp);
 122    brw_MOV(p, deref_4f(vert_addr, ndc_offset), tmp);
 123
 124    release_tmp(c, tmp);
 125 }
 126
 127
 128
 129
 130 /* Interpolate between two vertices and put the result into a0.0.
 131  * Increment a0.0 accordingly.
 132  */
 133 void brw_clip_interp_vertex( struct brw_clip_compile *c,
 134                              struct brw_indirect dest_ptr,
 135                              struct brw_indirect v0_ptr, /* from */
 136                              struct brw_indirect v1_ptr, /* to */
 137                              struct brw_reg t0,
 138                              GLboolean force_edgeflag)
 139 {
 140    struct brw_compile *p = &c->func;
 141    struct brw_reg tmp = get_tmp(c);
 142    GLuint i;
 143
 144    /* Just copy the vertex header:
 145     */
 146    /*
 147     * After CLIP stage, only first 256 bits of the VUE are read
 148     * back on Ironlake, so needn't change it
 149     */
 150    brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
 151
 152    /* Iterate over each attribute (could be done in pairs?)
 153     */
 154    for (i = 0; i < c->nr_attrs; i++) {
 155       GLuint delta = c->offset[c->idx_to_attr[i]];
 156
 157       if (c->idx_to_attr[i] == VERT_RESULT_EDGE) {
 158          if (force_edgeflag)
 159             brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
 160          else
 161             brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
 162       }
 163       else {
 164          /* Interpolate:
 165           *
 166           *        New = attr0 + t*attr1 - t*attr0
 167           */
 168          brw_MUL(p,
 169                  vec4(brw_null_reg()),
 170                  deref_4f(v1_ptr, delta),
 171                  t0);
 172
 173          brw_MAC(p,
 174                  tmp,
 175                  negate(deref_4f(v0_ptr, delta)),
 176                  t0);
 177
 178          brw_ADD(p,
 179                  deref_4f(dest_ptr, delta),
 180                  deref_4f(v0_ptr, delta),
 181                  tmp);
 182       }
 183    }
 184
 185    if (i & 1) {
 186       GLuint delta = c->offset[c->idx_to_attr[c->nr_attrs - 1]] + ATTR_SIZE;
 187
 188       brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
 189    }
 190
 191    release_tmp(c, tmp);
 192
 193    /* Recreate the projected (NDC) coordinate in the new vertex
 194     * header:
 195     */
 196    brw_clip_project_vertex(c, dest_ptr );
 197 }
 198
 199 void brw_clip_emit_vue(struct brw_clip_compile *c,
 200                        struct brw_indirect vert,
 201                        GLboolean allocate,
 202                        GLboolean eot,
 203                        GLuint header)
 204 {
 205    struct brw_compile *p = &c->func;
 206
 207    brw_clip_ff_sync(c);
 208
 209    assert(!(allocate && eot));
 210
 211    /* Copy the vertex from vertn into m1..mN+1:
 212     */
 213    brw_copy_from_indirect(p, brw_message_reg(1), vert, c->nr_regs);
 214
 215    /* Overwrite PrimType and PrimStart in the message header, for
 216     * each vertex in turn:
 217     */
 218    brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
 219
 220
 221    /* Send each vertex as a seperate write to the urb.  This
 222     * is different to the concept in brw_sf_emit.c, where
 223     * subsequent writes are used to build up a single urb
 224     * entry.  Each of these writes instantiates a seperate
 225     * urb entry - (I think... what about 'allocate'?)
 226     */
 227    brw_urb_WRITE(p,
 228                  allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 229                  0,
 230                  c->reg.R0,
 231                  allocate,
 232                  1,             /* used */
 233                  c->nr_regs + 1, /* msg length */
 234                  allocate ? 1 : 0, /* response_length */
 235                  eot,           /* eot */
 236                  1,             /* writes_complete */
 237                  0,             /* urb offset */
 238                  BRW_URB_SWIZZLE_NONE);
 239 }
 240
 241
 242
 243 void brw_clip_kill_thread(struct brw_clip_compile *c)
 244 {
 245    struct brw_compile *p = &c->func;
 246
 247    brw_clip_ff_sync(c);
 248    /* Send an empty message to kill the thread and release any
 249     * allocated urb entry:
 250     */
 251    brw_urb_WRITE(p,
 252                  retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 253                  0,
 254                  c->reg.R0,
 255                  0,             /* allocate */
 256                  0,             /* used */
 257                  1,             /* msg len */
 258                  0,             /* response len */
 259                  1,             /* eot */
 260                  1,             /* writes complete */
 261                  0,
 262                  BRW_URB_SWIZZLE_NONE);
 263 }
 264
 265
 266
 267
 268 struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
 269 {
 270    return brw_address(c->reg.fixed_planes);
 271 }
 272
 273
 274 struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c )
 275 {
 276    if (c->key.nr_userclip) {
 277       return brw_imm_uw(16);
 278    }
 279    else {
 280       return brw_imm_uw(4);
 281    }
 282 }
 283
 284
 285 /* If flatshading, distribute color from provoking vertex prior to
 286  * clipping.
 287  */
 288 void brw_clip_copy_colors( struct brw_clip_compile *c,
 289                            GLuint to, GLuint from )
 290 {
 291    struct brw_compile *p = &c->func;
 292
 293    if (c->offset[VERT_RESULT_COL0])
 294       brw_MOV(p,
 295               byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL0]),
 296               byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL0]));
 297
 298    if (c->offset[VERT_RESULT_COL1])
 299       brw_MOV(p,
 300               byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL1]),
 301               byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL1]));
 302
 303    if (c->offset[VERT_RESULT_BFC0])
 304       brw_MOV(p,
 305               byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC0]),
 306               byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC0]));
 307
 308    if (c->offset[VERT_RESULT_BFC1])
 309       brw_MOV(p,
 310               byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC1]),
 311               byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC1]));
 312 }
 313
 314
 315
 316 void brw_clip_init_clipmask( struct brw_clip_compile *c )
 317 {
 318    struct brw_compile *p = &c->func;
 319    struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
 320
 321    /* Shift so that lowest outcode bit is rightmost:
 322     */
 323    brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
 324
 325    if (c->key.nr_userclip) {
 326       struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
 327
 328       /* Rearrange userclip outcodes so that they come directly after
 329        * the fixed plane bits.
 330        */
 331       brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
 332       brw_SHR(p, tmp, tmp, brw_imm_ud(8));
 333       brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);
 334
 335       release_tmp(c, tmp);
 336    }
 337 }
 338
 339 void brw_clip_ff_sync(struct brw_clip_compile *c)
 340 {
 341     struct intel_context *intel = &c->func.brw->intel;
 342
 343     if (intel->needs_ff_sync) {
 344         struct brw_compile *p = &c->func;
 345
 346         brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
 347         brw_AND(p, brw_null_reg(), c->reg.ff_sync, brw_imm_ud(0x1));
 348         brw_IF(p, BRW_EXECUTE_1);
 349         {
 350             brw_OR(p, c->reg.ff_sync, c->reg.ff_sync, brw_imm_ud(0x1));
 351             brw_ff_sync(p,
 352                         c->reg.R0,
 353                         0,
 354                         c->reg.R0,
 355                         1, /* allocate */
 356                         1, /* response length */
 357                         0 /* eot */);
 358         }
 359         brw_ENDIF(p);
 360         brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 361     }
 362 }
 363
 364 void brw_clip_init_ff_sync(struct brw_clip_compile *c)
 365 {
 366     struct intel_context *intel = &c->func.brw->intel;
 367
 368     if (intel->needs_ff_sync) {
 369         struct brw_compile *p = &c->func;
 370
 371         brw_MOV(p, c->reg.ff_sync, brw_imm_ud(0));
 372     }
 373 }