Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / i965 / brw_clip_util.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33 #include "main/glheader.h"
34 #include "main/macros.h"
35 #include "main/enums.h"
36 #include "shader/program.h"
37
38 #include "intel_batchbuffer.h"
39
40 #include "brw_defines.h"
41 #include "brw_context.h"
42 #include "brw_eu.h"
43 #include "brw_util.h"
44 #include "brw_clip.h"
45
46
47
48
49 struct brw_reg get_tmp( struct brw_clip_compile *c )
50 {
51 struct brw_reg tmp = brw_vec4_grf(c->last_tmp, 0);
52
53 if (++c->last_tmp > c->prog_data.total_grf)
54 c->prog_data.total_grf = c->last_tmp;
55
56 return tmp;
57 }
58
59 static void release_tmp( struct brw_clip_compile *c, struct brw_reg tmp )
60 {
61 if (tmp.nr == c->last_tmp-1)
62 c->last_tmp--;
63 }
64
65
66 static struct brw_reg make_plane_ud(GLuint x, GLuint y, GLuint z, GLuint w)
67 {
68 return brw_imm_ud((w<<24) | (z<<16) | (y<<8) | x);
69 }
70
71
72 void brw_clip_init_planes( struct brw_clip_compile *c )
73 {
74 struct brw_compile *p = &c->func;
75
76 if (!c->key.nr_userclip) {
77 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 0), make_plane_ud( 0, 0, 0xff, 1));
78 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 1), make_plane_ud( 0, 0, 1, 1));
79 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 2), make_plane_ud( 0, 0xff, 0, 1));
80 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 3), make_plane_ud( 0, 1, 0, 1));
81 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 4), make_plane_ud(0xff, 0, 0, 1));
82 brw_MOV(p, get_element_ud(c->reg.fixed_planes, 5), make_plane_ud( 1, 0, 0, 1));
83 }
84 }
85
86
87
88 #define W 3
89
90 /* Project 'pos' to screen space (or back again), overwrite with results:
91 */
92 void brw_clip_project_position(struct brw_clip_compile *c, struct brw_reg pos )
93 {
94 struct brw_compile *p = &c->func;
95
96 /* calc rhw
97 */
98 brw_math_invert(p, get_element(pos, W), get_element(pos, W));
99
100 /* value.xyz *= value.rhw
101 */
102 brw_set_access_mode(p, BRW_ALIGN_16);
103 brw_MUL(p, brw_writemask(pos, WRITEMASK_XYZ), pos, brw_swizzle1(pos, W));
104 brw_set_access_mode(p, BRW_ALIGN_1);
105 }
106
107
108 static void brw_clip_project_vertex( struct brw_clip_compile *c,
109 struct brw_indirect vert_addr )
110 {
111 struct brw_compile *p = &c->func;
112 struct brw_reg tmp = get_tmp(c);
113
114 /* Fixup position. Extract from the original vertex and re-project
115 * to screen space:
116 */
117 brw_MOV(p, tmp, deref_4f(vert_addr, c->offset[VERT_RESULT_HPOS]));
118 brw_clip_project_position(c, tmp);
119 brw_MOV(p, deref_4f(vert_addr, c->header_position_offset), tmp);
120
121 release_tmp(c, tmp);
122 }
123
124
125
126
127 /* Interpolate between two vertices and put the result into a0.0.
128 * Increment a0.0 accordingly.
129 */
130 void brw_clip_interp_vertex( struct brw_clip_compile *c,
131 struct brw_indirect dest_ptr,
132 struct brw_indirect v0_ptr, /* from */
133 struct brw_indirect v1_ptr, /* to */
134 struct brw_reg t0,
135 GLboolean force_edgeflag)
136 {
137 struct brw_compile *p = &c->func;
138 struct brw_reg tmp = get_tmp(c);
139 GLuint i;
140
141 /* Just copy the vertex header:
142 */
143 /*
144 * After CLIP stage, only first 256 bits of the VUE are read
145 * back on IGDNG, so needn't change it
146 */
147 brw_copy_indirect_to_indirect(p, dest_ptr, v0_ptr, 1);
148
149 /* Iterate over each attribute (could be done in pairs?)
150 */
151 for (i = 0; i < c->nr_attrs; i++) {
152 GLuint delta = i*16 + 32;
153
154 if (BRW_IS_IGDNG(p->brw))
155 delta = i * 16 + 32 * 3;
156
157 if (delta == c->offset[VERT_RESULT_EDGE]) {
158 if (force_edgeflag)
159 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
160 else
161 brw_MOV(p, deref_4f(dest_ptr, delta), deref_4f(v0_ptr, delta));
162 }
163 else {
164 /* Interpolate:
165 *
166 * New = attr0 + t*attr1 - t*attr0
167 */
168 brw_MUL(p,
169 vec4(brw_null_reg()),
170 deref_4f(v1_ptr, delta),
171 t0);
172
173 brw_MAC(p,
174 tmp,
175 negate(deref_4f(v0_ptr, delta)),
176 t0);
177
178 brw_ADD(p,
179 deref_4f(dest_ptr, delta),
180 deref_4f(v0_ptr, delta),
181 tmp);
182 }
183 }
184
185 if (i & 1) {
186 GLuint delta = i*16 + 32;
187
188 if (BRW_IS_IGDNG(p->brw))
189 delta = i * 16 + 32 * 3;
190
191 brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
192 }
193
194 release_tmp(c, tmp);
195
196 /* Recreate the projected (NDC) coordinate in the new vertex
197 * header:
198 */
199 brw_clip_project_vertex(c, dest_ptr );
200 }
201
202
203
204
205 #define MAX_MRF 16
206
207 void brw_clip_emit_vue(struct brw_clip_compile *c,
208 struct brw_indirect vert,
209 GLboolean allocate,
210 GLboolean eot,
211 GLuint header)
212 {
213 struct brw_compile *p = &c->func;
214 GLuint start = c->last_mrf;
215
216 assert(!(allocate && eot));
217
218 /* Cycle through mrf regs - probably futile as we have to wait for
219 * the allocation response anyway. Also, the order this function
220 * is invoked doesn't correspond to the order the instructions will
221 * be executed, so it won't have any effect in many cases.
222 */
223 #if 0
224 if (start + c->nr_regs + 1 >= MAX_MRF)
225 start = 0;
226
227 c->last_mrf = start + c->nr_regs + 1;
228 #endif
229
230 /* Copy the vertex from vertn into m1..mN+1:
231 */
232 brw_copy_from_indirect(p, brw_message_reg(start+1), vert, c->nr_regs);
233
234 /* Overwrite PrimType and PrimStart in the message header, for
235 * each vertex in turn:
236 */
237 brw_MOV(p, get_element_ud(c->reg.R0, 2), brw_imm_ud(header));
238
239
240 /* Send each vertex as a seperate write to the urb. This
241 * is different to the concept in brw_sf_emit.c, where
242 * subsequent writes are used to build up a single urb
243 * entry. Each of these writes instantiates a seperate
244 * urb entry - (I think... what about 'allocate'?)
245 */
246 brw_urb_WRITE(p,
247 allocate ? c->reg.R0 : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
248 start,
249 c->reg.R0,
250 allocate,
251 1, /* used */
252 c->nr_regs + 1, /* msg length */
253 allocate ? 1 : 0, /* response_length */
254 eot, /* eot */
255 1, /* writes_complete */
256 0, /* urb offset */
257 BRW_URB_SWIZZLE_NONE);
258 }
259
260
261
262 void brw_clip_kill_thread(struct brw_clip_compile *c)
263 {
264 struct brw_compile *p = &c->func;
265
266 /* Send an empty message to kill the thread and release any
267 * allocated urb entry:
268 */
269 brw_urb_WRITE(p,
270 retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
271 0,
272 c->reg.R0,
273 0, /* allocate */
274 0, /* used */
275 1, /* msg len */
276 0, /* response len */
277 1, /* eot */
278 1, /* writes complete */
279 0,
280 BRW_URB_SWIZZLE_NONE);
281 }
282
283
284
285
286 struct brw_reg brw_clip_plane0_address( struct brw_clip_compile *c )
287 {
288 return brw_address(c->reg.fixed_planes);
289 }
290
291
292 struct brw_reg brw_clip_plane_stride( struct brw_clip_compile *c )
293 {
294 if (c->key.nr_userclip) {
295 return brw_imm_uw(16);
296 }
297 else {
298 return brw_imm_uw(4);
299 }
300 }
301
302
303 /* If flatshading, distribute color from provoking vertex prior to
304 * clipping.
305 */
306 void brw_clip_copy_colors( struct brw_clip_compile *c,
307 GLuint to, GLuint from )
308 {
309 struct brw_compile *p = &c->func;
310
311 if (c->offset[VERT_RESULT_COL0])
312 brw_MOV(p,
313 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL0]),
314 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL0]));
315
316 if (c->offset[VERT_RESULT_COL1])
317 brw_MOV(p,
318 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL1]),
319 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL1]));
320
321 if (c->offset[VERT_RESULT_BFC0])
322 brw_MOV(p,
323 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC0]),
324 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC0]));
325
326 if (c->offset[VERT_RESULT_BFC1])
327 brw_MOV(p,
328 byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC1]),
329 byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC1]));
330 }
331
332
333
334 void brw_clip_init_clipmask( struct brw_clip_compile *c )
335 {
336 struct brw_compile *p = &c->func;
337 struct brw_reg incoming = get_element_ud(c->reg.R0, 2);
338
339 /* Shift so that lowest outcode bit is rightmost:
340 */
341 brw_SHR(p, c->reg.planemask, incoming, brw_imm_ud(26));
342
343 if (c->key.nr_userclip) {
344 struct brw_reg tmp = retype(vec1(get_tmp(c)), BRW_REGISTER_TYPE_UD);
345
346 /* Rearrange userclip outcodes so that they come directly after
347 * the fixed plane bits.
348 */
349 brw_AND(p, tmp, incoming, brw_imm_ud(0x3f<<14));
350 brw_SHR(p, tmp, tmp, brw_imm_ud(8));
351 brw_OR(p, c->reg.planemask, c->reg.planemask, tmp);
352
353 release_tmp(c, tmp);
354 }
355 }
356
357 void brw_clip_ff_sync(struct brw_clip_compile *c)
358 {
359 struct brw_compile *p = &c->func;
360 brw_ff_sync(p,
361 c->reg.R0,
362 0,
363 c->reg.R0,
364 1,
365 1, /* used */
366 1, /* msg length */
367 1, /* response length */
368 0, /* eot */
369 1, /* write compelete */
370 0, /* urb offset */
371 BRW_URB_SWIZZLE_NONE);
372 }