src/mesa/drivers/dri/i965/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_context.h"
  26 #include "compiler/nir/nir.h"
  27 #include "main/errors.h"
  28 #include "util/debug.h"
  29
  30 static void
  31 shader_debug_log_mesa(void *data, const char *fmt, ...)
  32 {
  33    struct brw_context *brw = (struct brw_context *)data;
  34    va_list args;
  35
  36    va_start(args, fmt);
  37    GLuint msg_id = 0;
  38    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  39                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  40                    MESA_DEBUG_TYPE_OTHER,
  41                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  42    va_end(args);
  43 }
  44
  45 static void
  46 shader_perf_log_mesa(void *data, const char *fmt, ...)
  47 {
  48    struct brw_context *brw = (struct brw_context *)data;
  49
  50    va_list args;
  51    va_start(args, fmt);
  52
  53    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  54       va_list args_copy;
  55       va_copy(args_copy, args);
  56       vfprintf(stderr, fmt, args_copy);
  57       va_end(args_copy);
  58    }
  59
  60    if (brw->perf_debug) {
  61       GLuint msg_id = 0;
  62       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  63                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  64                       MESA_DEBUG_TYPE_PERFORMANCE,
  65                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  66    }
  67    va_end(args);
  68 }
  69
  70 #define COMMON_OPTIONS                                                        \
  71    .lower_sub = true,                                                         \
  72    .lower_fdiv = true,                                                        \
  73    .lower_scmp = true,                                                        \
  74    .lower_fmod32 = true,                                                      \
  75    .lower_fmod64 = false,                                                     \
  76    .lower_bitfield_extract = true,                                            \
  77    .lower_bitfield_insert = true,                                             \
  78    .lower_uadd_carry = true,                                                  \
  79    .lower_usub_borrow = true,                                                 \
  80    .lower_fdiv = true,                                                        \
  81    .lower_flrp64 = true,                                                      \
  82    .native_integers = true,                                                   \
  83    .vertex_id_zero_based = true
  84
  85 static const struct nir_shader_compiler_options scalar_nir_options = {
  86    COMMON_OPTIONS,
  87    .lower_pack_half_2x16 = true,
  88    .lower_pack_snorm_2x16 = true,
  89    .lower_pack_snorm_4x8 = true,
  90    .lower_pack_unorm_2x16 = true,
  91    .lower_pack_unorm_4x8 = true,
  92    .lower_unpack_half_2x16 = true,
  93    .lower_unpack_snorm_2x16 = true,
  94    .lower_unpack_snorm_4x8 = true,
  95    .lower_unpack_unorm_2x16 = true,
  96    .lower_unpack_unorm_4x8 = true,
  97 };
  98
  99 static const struct nir_shader_compiler_options vector_nir_options = {
 100    COMMON_OPTIONS,
 101
 102    /* In the vec4 backend, our dpN instruction replicates its result to all the
 103     * components of a vec4.  We would like NIR to give us replicated fdot
 104     * instructions because it can optimize better for us.
 105     */
 106    .fdot_replicates = true,
 107
 108    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
 109    .lower_flrp32 = true,
 110
 111    .lower_pack_snorm_2x16 = true,
 112    .lower_pack_unorm_2x16 = true,
 113    .lower_unpack_snorm_2x16 = true,
 114    .lower_unpack_unorm_2x16 = true,
 115    .lower_extract_byte = true,
 116    .lower_extract_word = true,
 117 };
 118
 119 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
 120    COMMON_OPTIONS,
 121
 122    /* In the vec4 backend, our dpN instruction replicates its result to all the
 123     * components of a vec4.  We would like NIR to give us replicated fdot
 124     * instructions because it can optimize better for us.
 125     */
 126    .fdot_replicates = true,
 127
 128    .lower_pack_snorm_2x16 = true,
 129    .lower_pack_unorm_2x16 = true,
 130    .lower_unpack_snorm_2x16 = true,
 131    .lower_unpack_unorm_2x16 = true,
 132    .lower_extract_byte = true,
 133    .lower_extract_word = true,
 134 };
 135
 136 struct brw_compiler *
 137 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
 138 {
 139    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 140
 141    compiler->devinfo = devinfo;
 142    compiler->shader_debug_log = shader_debug_log_mesa;
 143    compiler->shader_perf_log = shader_perf_log_mesa;
 144
 145    brw_fs_alloc_reg_sets(compiler);
 146    brw_vec4_alloc_reg_set(compiler);
 147
 148    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 149
 150    compiler->scalar_stage[MESA_SHADER_VERTEX] =
 151       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
 152    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 153       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 154    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 155       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 156    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 157       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 158    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 159    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 160
 161    /* We want the GLSL compiler to emit code that uses condition codes */
 162    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 163       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 164       compiler->glsl_compiler_options[i].MaxIfDepth =
 165          devinfo->gen < 6 ? 16 : UINT_MAX;
 166
 167       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 168       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 169       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 170       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 171       compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = true;
 172
 173       bool is_scalar = compiler->scalar_stage[i];
 174
 175       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 176       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 177       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 178
 179       /* !ARB_gpu_shader5 */
 180       if (devinfo->gen < 7)
 181          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 182
 183       if (is_scalar) {
 184          compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
 185       } else {
 186          compiler->glsl_compiler_options[i].NirOptions =
 187             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 188       }
 189
 190       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 191    }
 192
 193    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 194    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 195    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 196
 197    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 198       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 199
 200    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 201       .LowerShaderSharedVariables = true;
 202
 203    return compiler;
 204 }