src/mesa/drivers/dri/i965/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_context.h"
  26 #include "compiler/nir/nir.h"
  27 #include "main/errors.h"
  28 #include "util/debug.h"
  29
  30 #define COMMON_OPTIONS                                                        \
  31    .lower_sub = true,                                                         \
  32    .lower_fdiv = true,                                                        \
  33    .lower_scmp = true,                                                        \
  34    .lower_fmod32 = true,                                                      \
  35    .lower_fmod64 = false,                                                     \
  36    .lower_bitfield_extract = true,                                            \
  37    .lower_bitfield_insert = true,                                             \
  38    .lower_uadd_carry = true,                                                  \
  39    .lower_usub_borrow = true,                                                 \
  40    .lower_fdiv = true,                                                        \
  41    .lower_flrp64 = true,                                                      \
  42    .native_integers = true,                                                   \
  43    .use_interpolated_input_intrinsics = true,                                 \
  44    .vertex_id_zero_based = true
  45
  46 static const struct nir_shader_compiler_options scalar_nir_options = {
  47    COMMON_OPTIONS,
  48    .lower_pack_half_2x16 = true,
  49    .lower_pack_snorm_2x16 = true,
  50    .lower_pack_snorm_4x8 = true,
  51    .lower_pack_unorm_2x16 = true,
  52    .lower_pack_unorm_4x8 = true,
  53    .lower_unpack_half_2x16 = true,
  54    .lower_unpack_snorm_2x16 = true,
  55    .lower_unpack_snorm_4x8 = true,
  56    .lower_unpack_unorm_2x16 = true,
  57    .lower_unpack_unorm_4x8 = true,
  58 };
  59
  60 static const struct nir_shader_compiler_options vector_nir_options = {
  61    COMMON_OPTIONS,
  62
  63    /* In the vec4 backend, our dpN instruction replicates its result to all the
  64     * components of a vec4.  We would like NIR to give us replicated fdot
  65     * instructions because it can optimize better for us.
  66     */
  67    .fdot_replicates = true,
  68
  69    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  70    .lower_flrp32 = true,
  71
  72    .lower_pack_snorm_2x16 = true,
  73    .lower_pack_unorm_2x16 = true,
  74    .lower_unpack_snorm_2x16 = true,
  75    .lower_unpack_unorm_2x16 = true,
  76    .lower_extract_byte = true,
  77    .lower_extract_word = true,
  78 };
  79
  80 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  81    COMMON_OPTIONS,
  82
  83    /* In the vec4 backend, our dpN instruction replicates its result to all the
  84     * components of a vec4.  We would like NIR to give us replicated fdot
  85     * instructions because it can optimize better for us.
  86     */
  87    .fdot_replicates = true,
  88
  89    .lower_pack_snorm_2x16 = true,
  90    .lower_pack_unorm_2x16 = true,
  91    .lower_unpack_snorm_2x16 = true,
  92    .lower_unpack_unorm_2x16 = true,
  93    .lower_extract_byte = true,
  94    .lower_extract_word = true,
  95 };
  96
  97 struct brw_compiler *
  98 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
  99 {
 100    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 101
 102    compiler->devinfo = devinfo;
 103
 104    brw_fs_alloc_reg_sets(compiler);
 105    brw_vec4_alloc_reg_set(compiler);
 106
 107    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 108
 109    compiler->scalar_stage[MESA_SHADER_VERTEX] =
 110       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
 111    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 112       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 113    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 114       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 115    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 116       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 117    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 118    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 119
 120    /* We want the GLSL compiler to emit code that uses condition codes */
 121    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 122       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 123       compiler->glsl_compiler_options[i].MaxIfDepth =
 124          devinfo->gen < 6 ? 16 : UINT_MAX;
 125
 126       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 127       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 128       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 129       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 130       compiler->glsl_compiler_options[i].LowerCombinedClipCullDistance = true;
 131
 132       bool is_scalar = compiler->scalar_stage[i];
 133
 134       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 135       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 136       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 137
 138       /* !ARB_gpu_shader5 */
 139       if (devinfo->gen < 7)
 140          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 141
 142       if (is_scalar) {
 143          compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
 144       } else {
 145          compiler->glsl_compiler_options[i].NirOptions =
 146             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 147       }
 148
 149       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 150       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 151    }
 152
 153    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 154    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 155    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 156
 157    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 158       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 159
 160    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE]
 161       .LowerShaderSharedVariables = true;
 162
 163    return compiler;
 164 }