src/mesa/drivers/dri/i965/brw_compiler.c

   1 /*
   2  * Copyright © 2015-2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_compiler.h"
  25 #include "brw_shader.h"
  26 #include "common/gen_debug.h"
  27 #include "compiler/nir/nir.h"
  28 #include "main/errors.h"
  29 #include "util/debug.h"
  30
  31 #define COMMON_OPTIONS                                                        \
  32    .lower_sub = true,                                                         \
  33    .lower_fdiv = true,                                                        \
  34    .lower_scmp = true,                                                        \
  35    .lower_fmod32 = true,                                                      \
  36    .lower_fmod64 = false,                                                     \
  37    .lower_bitfield_extract = true,                                            \
  38    .lower_bitfield_insert = true,                                             \
  39    .lower_uadd_carry = true,                                                  \
  40    .lower_usub_borrow = true,                                                 \
  41    .lower_fdiv = true,                                                        \
  42    .lower_flrp64 = true,                                                      \
  43    .native_integers = true,                                                   \
  44    .use_interpolated_input_intrinsics = true,                                 \
  45    .vertex_id_zero_based = true
  46
  47 static const struct nir_shader_compiler_options scalar_nir_options = {
  48    COMMON_OPTIONS,
  49    .lower_pack_half_2x16 = true,
  50    .lower_pack_snorm_2x16 = true,
  51    .lower_pack_snorm_4x8 = true,
  52    .lower_pack_unorm_2x16 = true,
  53    .lower_pack_unorm_4x8 = true,
  54    .lower_unpack_half_2x16 = true,
  55    .lower_unpack_snorm_2x16 = true,
  56    .lower_unpack_snorm_4x8 = true,
  57    .lower_unpack_unorm_2x16 = true,
  58    .lower_unpack_unorm_4x8 = true,
  59    .max_unroll_iterations = 32,
  60 };
  61
  62 static const struct nir_shader_compiler_options vector_nir_options = {
  63    COMMON_OPTIONS,
  64
  65    /* In the vec4 backend, our dpN instruction replicates its result to all the
  66     * components of a vec4.  We would like NIR to give us replicated fdot
  67     * instructions because it can optimize better for us.
  68     */
  69    .fdot_replicates = true,
  70
  71    /* Prior to Gen6, there are no three source operations for SIMD4x2. */
  72    .lower_flrp32 = true,
  73
  74    .lower_pack_snorm_2x16 = true,
  75    .lower_pack_unorm_2x16 = true,
  76    .lower_unpack_snorm_2x16 = true,
  77    .lower_unpack_unorm_2x16 = true,
  78    .lower_extract_byte = true,
  79    .lower_extract_word = true,
  80    .max_unroll_iterations = 32,
  81 };
  82
  83 static const struct nir_shader_compiler_options vector_nir_options_gen6 = {
  84    COMMON_OPTIONS,
  85
  86    /* In the vec4 backend, our dpN instruction replicates its result to all the
  87     * components of a vec4.  We would like NIR to give us replicated fdot
  88     * instructions because it can optimize better for us.
  89     */
  90    .fdot_replicates = true,
  91
  92    .lower_pack_snorm_2x16 = true,
  93    .lower_pack_unorm_2x16 = true,
  94    .lower_unpack_snorm_2x16 = true,
  95    .lower_unpack_unorm_2x16 = true,
  96    .lower_extract_byte = true,
  97    .lower_extract_word = true,
  98    .max_unroll_iterations = 32,
  99 };
 100
 101 struct brw_compiler *
 102 brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
 103 {
 104    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
 105
 106    compiler->devinfo = devinfo;
 107
 108    brw_fs_alloc_reg_sets(compiler);
 109    brw_vec4_alloc_reg_set(compiler);
 110
 111    compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
 112
 113    compiler->scalar_stage[MESA_SHADER_VERTEX] =
 114       devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
 115    compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
 116       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TCS", true);
 117    compiler->scalar_stage[MESA_SHADER_TESS_EVAL] =
 118       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_TES", true);
 119    compiler->scalar_stage[MESA_SHADER_GEOMETRY] =
 120       devinfo->gen >= 8 && env_var_as_boolean("INTEL_SCALAR_GS", true);
 121    compiler->scalar_stage[MESA_SHADER_FRAGMENT] = true;
 122    compiler->scalar_stage[MESA_SHADER_COMPUTE] = true;
 123
 124    /* We want the GLSL compiler to emit code that uses condition codes */
 125    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 126       compiler->glsl_compiler_options[i].MaxUnrollIterations = 0;
 127       compiler->glsl_compiler_options[i].MaxIfDepth =
 128          devinfo->gen < 6 ? 16 : UINT_MAX;
 129
 130       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 131       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 132
 133       bool is_scalar = compiler->scalar_stage[i];
 134
 135       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 136       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 137       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 138
 139       if (is_scalar) {
 140          compiler->glsl_compiler_options[i].NirOptions = &scalar_nir_options;
 141       } else {
 142          compiler->glsl_compiler_options[i].NirOptions =
 143             devinfo->gen < 6 ? &vector_nir_options : &vector_nir_options_gen6;
 144       }
 145
 146       compiler->glsl_compiler_options[i].LowerBufferInterfaceBlocks = true;
 147       compiler->glsl_compiler_options[i].ClampBlockIndicesToArrayBounds = true;
 148    }
 149
 150    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectInput = false;
 151    compiler->glsl_compiler_options[MESA_SHADER_TESS_EVAL].EmitNoIndirectInput = false;
 152    compiler->glsl_compiler_options[MESA_SHADER_TESS_CTRL].EmitNoIndirectOutput = false;
 153
 154    if (compiler->scalar_stage[MESA_SHADER_GEOMETRY])
 155       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].EmitNoIndirectInput = false;
 156
 157    return compiler;
 158 }