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27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
29 #include "main/macros.h"
37 struct brw_geometry_program
;
38 union gl_constant_value
;
41 const struct brw_device_info
*devinfo
;
47 * Array of the ra classes for the unaligned contiguous register
53 * Mapping for register-allocated objects in *regs to the first
54 * GRF for that object.
56 uint8_t *ra_reg_to_grf
;
63 * Array of the ra classes for the unaligned contiguous register
64 * block sizes used, indexed by register size.
69 * Mapping from classes to ra_reg ranges. Each of the per-size
70 * classes corresponds to a range of ra_reg nodes. This array stores
71 * those ranges in the form of first ra_reg in each class and the
72 * total number of ra_reg elements in the last array element. This
73 * way the range of the i'th class is given by:
74 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
76 int class_to_ra_reg_range
[17];
79 * Mapping for register-allocated objects in *regs to the first
80 * GRF for that object.
82 uint8_t *ra_reg_to_grf
;
85 * ra class for the aligned pairs we use for PLN, which doesn't
88 int aligned_pairs_class
;
91 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
92 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
94 bool scalar_stage
[MESA_SHADER_STAGES
];
95 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
98 * Apply workarounds for SIN and COS output range problems.
99 * This can negatively impact performance.
106 * Program key structures.
108 * When drawing, we look for the currently bound shaders in the program
109 * cache. This is essentially a hash table lookup, and these are the keys.
111 * Sometimes OpenGL features specified as state need to be simulated via
112 * shader code, due to a mismatch between the API and the hardware. This
113 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
114 * in the program key so it's considered when searching for a program. If
115 * we haven't seen a particular combination before, we have to recompile a
116 * new specialized version.
118 * Shader compilation should not look up state in gl_context directly, but
119 * instead use the copy in the program key. This guarantees recompiles will
125 enum PACKED gen6_gather_sampler_wa
{
126 WA_SIGN
= 1, /* whether we need to sign extend */
127 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
128 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
132 * Sampler information needed by VS, WM, and GS program cache keys.
134 struct brw_sampler_prog_key_data
{
136 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
138 uint16_t swizzles
[MAX_SAMPLERS
];
140 uint32_t gl_clamp_mask
[3];
143 * For RG32F, gather4's channel select is broken.
145 uint32_t gather_channel_quirk_mask
;
148 * Whether this sampler uses the compressed multisample surface layout.
150 uint32_t compressed_multisample_layout_mask
;
153 * Whether this sampler is using 16x multisampling. If so fetching from
154 * this sampler will be handled with a different instruction, ld2dms_w
160 * For Sandybridge, which shader w/a we need for gather quirks.
162 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
165 * Texture units that have a YUV image bound.
167 uint32_t y_u_v_image_mask
;
168 uint32_t y_uv_image_mask
;
169 uint32_t yx_xuxv_image_mask
;
173 /** The program key for Vertex Shaders. */
174 struct brw_vs_prog_key
{
175 unsigned program_string_id
;
178 * Per-attribute workaround flags
180 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
182 bool copy_edgeflag
:1;
184 bool clamp_vertex_color
:1;
187 * How many user clipping planes are being uploaded to the vertex shader as
190 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
193 unsigned nr_userclip_plane_consts
:4;
196 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
197 * are going to be replaced with point coordinates (as a consequence of a
198 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
199 * our SF thread requires exact matching between VS outputs and FS inputs,
200 * these texture coordinates will need to be unconditionally included in
201 * the VUE, even if they aren't written by the vertex shader.
203 uint8_t point_coord_replace
;
205 struct brw_sampler_prog_key_data tex
;
208 /** The program key for Tessellation Control Shaders. */
209 struct brw_tcs_prog_key
211 unsigned program_string_id
;
213 GLenum tes_primitive_mode
;
215 unsigned input_vertices
;
217 /** A bitfield of per-patch outputs written. */
218 uint32_t patch_outputs_written
;
220 /** A bitfield of per-vertex outputs written. */
221 uint64_t outputs_written
;
223 struct brw_sampler_prog_key_data tex
;
226 /** The program key for Tessellation Evaluation Shaders. */
227 struct brw_tes_prog_key
229 unsigned program_string_id
;
231 /** A bitfield of per-patch inputs read. */
232 uint32_t patch_inputs_read
;
234 /** A bitfield of per-vertex inputs read. */
235 uint64_t inputs_read
;
237 struct brw_sampler_prog_key_data tex
;
240 /** The program key for Geometry Shaders. */
241 struct brw_gs_prog_key
243 unsigned program_string_id
;
245 struct brw_sampler_prog_key_data tex
;
248 /** The program key for Fragment/Pixel Shaders. */
249 struct brw_wm_prog_key
{
253 unsigned nr_color_regions
:5;
254 bool replicate_alpha
:1;
255 bool clamp_fragment_color
:1;
256 bool persample_interp
:1;
257 bool multisample_fbo
:1;
259 bool high_quality_derivatives
:1;
260 bool force_dual_color_blend
:1;
262 uint16_t drawable_height
;
263 uint64_t input_slots_valid
;
264 unsigned program_string_id
;
265 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
266 float alpha_test_ref
;
268 struct brw_sampler_prog_key_data tex
;
271 struct brw_cs_prog_key
{
272 uint32_t program_string_id
;
273 struct brw_sampler_prog_key_data tex
;
277 * Image metadata structure as laid out in the shader parameter
278 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
279 * able to use them. That's okay because the padding and any unused
280 * entries [most of them except when we're doing untyped surface
281 * access] will be removed by the uniform packing pass.
283 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
284 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
285 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
286 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
287 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
288 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
289 #define BRW_IMAGE_PARAM_SIZE 24
291 struct brw_image_param
{
292 /** Surface binding table index. */
293 uint32_t surface_idx
;
295 /** Offset applied to the X and Y surface coordinates. */
298 /** Surface X, Y and Z dimensions. */
301 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
302 * pixels, vertical slice stride in pixels.
306 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
310 * Right shift to apply for bit 6 address swizzling. Two different
311 * swizzles can be specified and will be applied one after the other. The
312 * resulting address will be:
314 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
315 * (addr >> swizzling[1])))
317 * Use \c 0xff if any of the swizzles is not required.
319 uint32_t swizzling
[2];
322 struct brw_stage_prog_data
{
324 /** size of our binding table. */
328 * surface indices for the various groups of surfaces
330 uint32_t pull_constants_start
;
331 uint32_t texture_start
;
332 uint32_t gather_texture_start
;
336 uint32_t image_start
;
337 uint32_t shader_time_start
;
338 uint32_t plane_start
[3];
342 GLuint nr_params
; /**< number of float params/constants */
343 GLuint nr_pull_params
;
344 unsigned nr_image_params
;
346 unsigned curb_read_length
;
347 unsigned total_scratch
;
348 unsigned total_shared
;
351 * Register where the thread expects to find input data from the URB
352 * (typically uniforms, followed by vertex or fragment attributes).
354 unsigned dispatch_grf_start_reg
;
356 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
358 /* Pointers to tracked values (only valid once
359 * _mesa_load_state_parameters has been called at runtime).
361 const union gl_constant_value
**param
;
362 const union gl_constant_value
**pull_param
;
364 /** Image metadata passed to the shader as uniforms. */
365 struct brw_image_param
*image_param
;
368 /* Data about a particular attempt to compile a program. Note that
369 * there can be many of these, each in a different GL state
370 * corresponding to a different brw_wm_prog_key struct, with different
373 struct brw_wm_prog_data
{
374 struct brw_stage_prog_data base
;
376 GLuint num_varying_inputs
;
378 uint8_t reg_blocks_0
;
379 uint8_t reg_blocks_2
;
381 uint8_t dispatch_grf_start_reg_2
;
382 uint32_t prog_offset_2
;
386 * surface indices the WM-specific surfaces
388 uint32_t render_target_start
;
392 uint8_t computed_depth_mode
;
393 bool computed_stencil
;
395 bool early_fragment_tests
;
399 bool persample_dispatch
;
400 bool uses_pos_offset
;
405 bool uses_sample_mask
;
406 bool has_side_effects
;
410 * Mask of which interpolation modes are required by the fragment shader.
411 * Used in hardware setup on gen6+.
413 uint32_t barycentric_interp_modes
;
416 * Mask of which FS inputs are marked flat by the shader source. This is
417 * needed for setting up 3DSTATE_SF/SBE.
419 uint32_t flat_inputs
;
422 * Map from gl_varying_slot to the position within the FS setup data
423 * payload where the varying's attribute vertex deltas should be delivered.
424 * For varying slots that are not used by the FS, the value is -1.
426 int urb_setup
[VARYING_SLOT_MAX
];
429 struct brw_push_const_block
{
430 unsigned dwords
; /* Dword count, not reg aligned */
432 unsigned size
; /* Bytes, register aligned */
435 struct brw_cs_prog_data
{
436 struct brw_stage_prog_data base
;
438 GLuint dispatch_grf_start_reg_16
;
439 unsigned local_size
[3];
443 bool uses_num_work_groups
;
444 int thread_local_id_index
;
447 struct brw_push_const_block cross_thread
;
448 struct brw_push_const_block per_thread
;
449 struct brw_push_const_block total
;
454 * surface indices the CS-specific surfaces
456 uint32_t work_groups_start
;
462 * Enum representing the i965-specific vertex results that don't correspond
463 * exactly to any element of gl_varying_slot. The values of this enum are
464 * assigned such that they don't conflict with gl_varying_slot.
468 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
469 BRW_VARYING_SLOT_PAD
,
471 * Technically this is not a varying but just a placeholder that
472 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
473 * builtin variable to be compiled correctly. see compile_sf_prog() for
476 BRW_VARYING_SLOT_PNTC
,
477 BRW_VARYING_SLOT_COUNT
481 * Data structure recording the relationship between the gl_varying_slot enum
482 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
483 * single octaword within the VUE (128 bits).
485 * Note that each BRW register contains 256 bits (2 octawords), so when
486 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
487 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
488 * in a vertex shader), each register corresponds to a single VUE slot, since
489 * it contains data for two separate vertices.
493 * Bitfield representing all varying slots that are (a) stored in this VUE
494 * map, and (b) actually written by the shader. Does not include any of
495 * the additional varying slots defined in brw_varying_slot.
497 GLbitfield64 slots_valid
;
500 * Is this VUE map for a separate shader pipeline?
502 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
503 * without the linker having a chance to dead code eliminate unused varyings.
505 * This means that we have to use a fixed slot layout, based on the output's
506 * location field, rather than assigning slots in a compact contiguous block.
511 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
512 * not stored in a slot (because they are not written, or because
513 * additional processing is applied before storing them in the VUE), the
516 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
519 * Map from VUE slot to gl_varying_slot value. For slots that do not
520 * directly correspond to a gl_varying_slot, the value comes from
523 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
525 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
528 * Total number of VUE slots in use
533 * Number of per-patch VUE slots. Only valid for tessellation control
534 * shader outputs and tessellation evaluation shader inputs.
536 int num_per_patch_slots
;
539 * Number of per-vertex VUE slots. Only valid for tessellation control
540 * shader outputs and tessellation evaluation shader inputs.
542 int num_per_vertex_slots
;
545 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
548 * Convert a VUE slot number into a byte offset within the VUE.
550 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
556 * Convert a vertex output (brw_varying_slot) into a byte offset within the
560 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
562 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
565 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
566 struct brw_vue_map
*vue_map
,
567 GLbitfield64 slots_valid
,
568 bool separate_shader
);
570 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
571 const GLbitfield64 slots_valid
,
572 const GLbitfield is_patch
);
574 enum shader_dispatch_mode
{
575 DISPATCH_MODE_4X1_SINGLE
= 0,
576 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
577 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
578 DISPATCH_MODE_SIMD8
= 3,
582 * @defgroup Tessellator parameter enumerations.
584 * These correspond to the hardware values in 3DSTATE_TE, and are provided
585 * as part of the tessellation evaluation shader.
589 enum brw_tess_partitioning
{
590 BRW_TESS_PARTITIONING_INTEGER
= 0,
591 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
592 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
595 enum brw_tess_output_topology
{
596 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
597 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
598 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
599 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
602 enum brw_tess_domain
{
603 BRW_TESS_DOMAIN_QUAD
= 0,
604 BRW_TESS_DOMAIN_TRI
= 1,
605 BRW_TESS_DOMAIN_ISOLINE
= 2,
609 struct brw_vue_prog_data
{
610 struct brw_stage_prog_data base
;
611 struct brw_vue_map vue_map
;
613 /** Should the hardware deliver input VUE handles for URB pull loads? */
614 bool include_vue_handles
;
616 GLuint urb_read_length
;
619 uint32_t cull_distance_mask
;
621 /* Used for calculating urb partitions. In the VS, this is the size of the
622 * URB entry used for both input and output to the thread. In the GS, this
623 * is the size of the URB entry used for output.
625 GLuint urb_entry_size
;
627 enum shader_dispatch_mode dispatch_mode
;
630 struct brw_vs_prog_data
{
631 struct brw_vue_prog_data base
;
633 GLbitfield64 inputs_read
;
635 unsigned nr_attributes
;
636 unsigned nr_attribute_slots
;
639 bool uses_instanceid
;
640 bool uses_basevertex
;
641 bool uses_baseinstance
;
645 struct brw_tcs_prog_data
647 struct brw_vue_prog_data base
;
649 /** Number vertices in output patch */
654 struct brw_tes_prog_data
656 struct brw_vue_prog_data base
;
658 enum brw_tess_partitioning partitioning
;
659 enum brw_tess_output_topology output_topology
;
660 enum brw_tess_domain domain
;
663 struct brw_gs_prog_data
665 struct brw_vue_prog_data base
;
667 unsigned vertices_in
;
670 * Size of an output vertex, measured in HWORDS (32 bytes).
672 unsigned output_vertex_size_hwords
;
674 unsigned output_topology
;
677 * Size of the control data (cut bits or StreamID bits), in hwords (32
678 * bytes). 0 if there is no control data.
680 unsigned control_data_header_size_hwords
;
683 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
684 * if the control data is StreamID bits, or
685 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
686 * Ignored if control_data_header_size is 0.
688 unsigned control_data_format
;
690 bool include_primitive_id
;
693 * The number of vertices emitted, if constant - otherwise -1.
695 int static_vertex_count
;
700 * Gen6 transform feedback enabled flag.
702 bool gen6_xfb_enabled
;
705 * Gen6: Provoking vertex convention for odd-numbered triangles
711 * Gen6: Number of varyings that are output to transform feedback.
713 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
716 * Gen6: Map from the index of a transform feedback binding table entry to the
717 * gl_varying_slot that should be streamed out through that binding table
720 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
723 * Gen6: Map from the index of a transform feedback binding table entry to the
724 * swizzles that should be used when streaming out data through that
725 * binding table entry.
727 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
733 struct brw_compiler
*
734 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
737 * Compile a vertex shader.
739 * Returns the final assembly and the program's size.
742 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
744 const struct brw_vs_prog_key
*key
,
745 struct brw_vs_prog_data
*prog_data
,
746 const struct nir_shader
*shader
,
747 gl_clip_plane
*clip_planes
,
748 bool use_legacy_snorm_formula
,
749 int shader_time_index
,
750 unsigned *final_assembly_size
,
754 * Compile a tessellation control shader.
756 * Returns the final assembly and the program's size.
759 brw_compile_tcs(const struct brw_compiler
*compiler
,
762 const struct brw_tcs_prog_key
*key
,
763 struct brw_tcs_prog_data
*prog_data
,
764 const struct nir_shader
*nir
,
765 int shader_time_index
,
766 unsigned *final_assembly_size
,
770 * Compile a tessellation evaluation shader.
772 * Returns the final assembly and the program's size.
775 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
777 const struct brw_tes_prog_key
*key
,
778 struct brw_tes_prog_data
*prog_data
,
779 const struct nir_shader
*shader
,
780 struct gl_shader_program
*shader_prog
,
781 int shader_time_index
,
782 unsigned *final_assembly_size
,
786 * Compile a vertex shader.
788 * Returns the final assembly and the program's size.
791 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
793 const struct brw_gs_prog_key
*key
,
794 struct brw_gs_prog_data
*prog_data
,
795 const struct nir_shader
*shader
,
796 struct gl_shader_program
*shader_prog
,
797 int shader_time_index
,
798 unsigned *final_assembly_size
,
802 * Compile a fragment shader.
804 * Returns the final assembly and the program's size.
807 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
809 const struct brw_wm_prog_key
*key
,
810 struct brw_wm_prog_data
*prog_data
,
811 const struct nir_shader
*shader
,
812 struct gl_program
*prog
,
813 int shader_time_index8
,
814 int shader_time_index16
,
817 unsigned *final_assembly_size
,
821 * Compile a compute shader.
823 * Returns the final assembly and the program's size.
826 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
828 const struct brw_cs_prog_key
*key
,
829 struct brw_cs_prog_data
*prog_data
,
830 const struct nir_shader
*shader
,
831 int shader_time_index
,
832 unsigned *final_assembly_size
,
835 static inline uint32_t
836 encode_slm_size(unsigned gen
, uint32_t bytes
)
838 uint32_t slm_size
= 0;
840 /* Shared Local Memory is specified as powers of two, and encoded in
841 * INTERFACE_DESCRIPTOR_DATA with the following representations:
843 * Size | 0 kB | 1 kB | 2 kB | 4 kB | 8 kB | 16 kB | 32 kB | 64 kB |
844 * -------------------------------------------------------------------
845 * Gen7-8 | 0 | none | none | 1 | 2 | 4 | 8 | 16 |
846 * -------------------------------------------------------------------
847 * Gen9+ | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
849 assert(bytes
<= 64 * 1024);
852 /* Shared Local Memory Size is specified as powers of two. */
853 slm_size
= util_next_power_of_two(bytes
);
856 /* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
857 slm_size
= ffs(MAX2(slm_size
, 1024)) - 10;
859 /* Use a minimum of 4kB; convert to the pre-Gen9 representation. */
860 slm_size
= MAX2(slm_size
, 4096) / 4096;