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27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
36 struct brw_geometry_program
;
37 union gl_constant_value
;
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
90 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
91 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 bool scalar_stage
[MESA_SHADER_STAGES
];
94 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
99 * Program key structures.
101 * When drawing, we look for the currently bound shaders in the program
102 * cache. This is essentially a hash table lookup, and these are the keys.
104 * Sometimes OpenGL features specified as state need to be simulated via
105 * shader code, due to a mismatch between the API and the hardware. This
106 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
107 * in the program key so it's considered when searching for a program. If
108 * we haven't seen a particular combination before, we have to recompile a
109 * new specialized version.
111 * Shader compilation should not look up state in gl_context directly, but
112 * instead use the copy in the program key. This guarantees recompiles will
118 enum PACKED gen6_gather_sampler_wa
{
119 WA_SIGN
= 1, /* whether we need to sign extend */
120 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
121 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
125 * Sampler information needed by VS, WM, and GS program cache keys.
127 struct brw_sampler_prog_key_data
{
129 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
131 uint16_t swizzles
[MAX_SAMPLERS
];
133 uint32_t gl_clamp_mask
[3];
136 * For RG32F, gather4's channel select is broken.
138 uint32_t gather_channel_quirk_mask
;
141 * Whether this sampler uses the compressed multisample surface layout.
143 uint32_t compressed_multisample_layout_mask
;
146 * Whether this sampler is using 16x multisampling. If so fetching from
147 * this sampler will be handled with a different instruction, ld2dms_w
153 * For Sandybridge, which shader w/a we need for gather quirks.
155 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
159 /** The program key for Vertex Shaders. */
160 struct brw_vs_prog_key
{
161 unsigned program_string_id
;
164 * Per-attribute workaround flags
166 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
168 bool copy_edgeflag
:1;
170 bool clamp_vertex_color
:1;
173 * How many user clipping planes are being uploaded to the vertex shader as
176 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
179 unsigned nr_userclip_plane_consts
:4;
182 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
183 * are going to be replaced with point coordinates (as a consequence of a
184 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
185 * our SF thread requires exact matching between VS outputs and FS inputs,
186 * these texture coordinates will need to be unconditionally included in
187 * the VUE, even if they aren't written by the vertex shader.
189 uint8_t point_coord_replace
;
191 struct brw_sampler_prog_key_data tex
;
194 /** The program key for Tessellation Evaluation Shaders. */
195 struct brw_tes_prog_key
197 unsigned program_string_id
;
199 struct brw_sampler_prog_key_data tex
;
202 /** The program key for Geometry Shaders. */
203 struct brw_gs_prog_key
205 unsigned program_string_id
;
207 struct brw_sampler_prog_key_data tex
;
210 /** The program key for Fragment/Pixel Shaders. */
211 struct brw_wm_prog_key
{
215 bool persample_shading
:1;
217 unsigned nr_color_regions
:5;
218 bool replicate_alpha
:1;
219 bool render_to_fbo
:1;
220 bool clamp_fragment_color
:1;
221 bool compute_pos_offset
:1;
222 bool compute_sample_id
:1;
224 bool high_quality_derivatives
:1;
226 uint16_t drawable_height
;
227 uint64_t input_slots_valid
;
228 unsigned program_string_id
;
229 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
230 float alpha_test_ref
;
232 struct brw_sampler_prog_key_data tex
;
235 struct brw_cs_prog_key
{
236 uint32_t program_string_id
;
237 struct brw_sampler_prog_key_data tex
;
241 * Image metadata structure as laid out in the shader parameter
242 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
243 * able to use them. That's okay because the padding and any unused
244 * entries [most of them except when we're doing untyped surface
245 * access] will be removed by the uniform packing pass.
247 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
248 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
249 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
250 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
251 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
252 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
253 #define BRW_IMAGE_PARAM_SIZE 24
255 struct brw_image_param
{
256 /** Surface binding table index. */
257 uint32_t surface_idx
;
259 /** Offset applied to the X and Y surface coordinates. */
262 /** Surface X, Y and Z dimensions. */
265 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
266 * pixels, vertical slice stride in pixels.
270 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
274 * Right shift to apply for bit 6 address swizzling. Two different
275 * swizzles can be specified and will be applied one after the other. The
276 * resulting address will be:
278 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
279 * (addr >> swizzling[1])))
281 * Use \c 0xff if any of the swizzles is not required.
283 uint32_t swizzling
[2];
286 struct brw_stage_prog_data
{
288 /** size of our binding table. */
292 * surface indices for the various groups of surfaces
294 uint32_t pull_constants_start
;
295 uint32_t texture_start
;
296 uint32_t gather_texture_start
;
300 uint32_t image_start
;
301 uint32_t shader_time_start
;
305 GLuint nr_params
; /**< number of float params/constants */
306 GLuint nr_pull_params
;
307 unsigned nr_image_params
;
309 unsigned curb_read_length
;
310 unsigned total_scratch
;
311 unsigned total_shared
;
314 * Register where the thread expects to find input data from the URB
315 * (typically uniforms, followed by vertex or fragment attributes).
317 unsigned dispatch_grf_start_reg
;
319 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
321 /* Pointers to tracked values (only valid once
322 * _mesa_load_state_parameters has been called at runtime).
324 const union gl_constant_value
**param
;
325 const union gl_constant_value
**pull_param
;
327 /** Image metadata passed to the shader as uniforms. */
328 struct brw_image_param
*image_param
;
331 /* Data about a particular attempt to compile a program. Note that
332 * there can be many of these, each in a different GL state
333 * corresponding to a different brw_wm_prog_key struct, with different
336 struct brw_wm_prog_data
{
337 struct brw_stage_prog_data base
;
339 GLuint num_varying_inputs
;
341 GLuint dispatch_grf_start_reg_16
;
343 GLuint reg_blocks_16
;
347 * surface indices the WM-specific surfaces
349 uint32_t render_target_start
;
353 uint8_t computed_depth_mode
;
354 bool computed_stencil
;
356 bool early_fragment_tests
;
359 bool uses_pos_offset
;
363 uint32_t prog_offset_16
;
366 * Mask of which interpolation modes are required by the fragment shader.
367 * Used in hardware setup on gen6+.
369 uint32_t barycentric_interp_modes
;
372 * Map from gl_varying_slot to the position within the FS setup data
373 * payload where the varying's attribute vertex deltas should be delivered.
374 * For varying slots that are not used by the FS, the value is -1.
376 int urb_setup
[VARYING_SLOT_MAX
];
379 struct brw_cs_prog_data
{
380 struct brw_stage_prog_data base
;
382 GLuint dispatch_grf_start_reg_16
;
383 unsigned local_size
[3];
386 bool uses_num_work_groups
;
387 unsigned local_invocation_id_regs
;
391 * surface indices the CS-specific surfaces
393 uint32_t work_groups_start
;
399 * Enum representing the i965-specific vertex results that don't correspond
400 * exactly to any element of gl_varying_slot. The values of this enum are
401 * assigned such that they don't conflict with gl_varying_slot.
405 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
406 BRW_VARYING_SLOT_PAD
,
408 * Technically this is not a varying but just a placeholder that
409 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
410 * builtin variable to be compiled correctly. see compile_sf_prog() for
413 BRW_VARYING_SLOT_PNTC
,
414 BRW_VARYING_SLOT_COUNT
418 * Data structure recording the relationship between the gl_varying_slot enum
419 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
420 * single octaword within the VUE (128 bits).
422 * Note that each BRW register contains 256 bits (2 octawords), so when
423 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
424 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
425 * in a vertex shader), each register corresponds to a single VUE slot, since
426 * it contains data for two separate vertices.
430 * Bitfield representing all varying slots that are (a) stored in this VUE
431 * map, and (b) actually written by the shader. Does not include any of
432 * the additional varying slots defined in brw_varying_slot.
434 GLbitfield64 slots_valid
;
437 * Is this VUE map for a separate shader pipeline?
439 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
440 * without the linker having a chance to dead code eliminate unused varyings.
442 * This means that we have to use a fixed slot layout, based on the output's
443 * location field, rather than assigning slots in a compact contiguous block.
448 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
449 * not stored in a slot (because they are not written, or because
450 * additional processing is applied before storing them in the VUE), the
453 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
456 * Map from VUE slot to gl_varying_slot value. For slots that do not
457 * directly correspond to a gl_varying_slot, the value comes from
460 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
462 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
465 * Total number of VUE slots in use
470 * Number of per-patch VUE slots. Only valid for tessellation control
471 * shader outputs and tessellation evaluation shader inputs.
473 int num_per_patch_slots
;
476 * Number of per-vertex VUE slots. Only valid for tessellation control
477 * shader outputs and tessellation evaluation shader inputs.
479 int num_per_vertex_slots
;
482 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
485 * Convert a VUE slot number into a byte offset within the VUE.
487 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
493 * Convert a vertex output (brw_varying_slot) into a byte offset within the
497 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
499 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
502 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
503 struct brw_vue_map
*vue_map
,
504 GLbitfield64 slots_valid
,
505 bool separate_shader
);
507 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
508 const GLbitfield64 slots_valid
,
509 const GLbitfield is_patch
);
511 enum shader_dispatch_mode
{
512 DISPATCH_MODE_4X1_SINGLE
= 0,
513 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
514 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
515 DISPATCH_MODE_SIMD8
= 3,
519 * @defgroup Tessellator parameter enumerations.
521 * These correspond to the hardware values in 3DSTATE_TE, and are provided
522 * as part of the tessellation evaluation shader.
526 enum brw_tess_partitioning
{
527 BRW_TESS_PARTITIONING_INTEGER
= 0,
528 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
529 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
532 enum brw_tess_output_topology
{
533 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
534 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
535 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
536 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
539 enum brw_tess_domain
{
540 BRW_TESS_DOMAIN_QUAD
= 0,
541 BRW_TESS_DOMAIN_TRI
= 1,
542 BRW_TESS_DOMAIN_ISOLINE
= 2,
546 struct brw_vue_prog_data
{
547 struct brw_stage_prog_data base
;
548 struct brw_vue_map vue_map
;
550 /** Should the hardware deliver input VUE handles for URB pull loads? */
551 bool include_vue_handles
;
553 GLuint urb_read_length
;
556 /* Used for calculating urb partitions. In the VS, this is the size of the
557 * URB entry used for both input and output to the thread. In the GS, this
558 * is the size of the URB entry used for output.
560 GLuint urb_entry_size
;
562 enum shader_dispatch_mode dispatch_mode
;
565 struct brw_vs_prog_data
{
566 struct brw_vue_prog_data base
;
568 GLbitfield64 inputs_read
;
570 unsigned nr_attributes
;
573 bool uses_instanceid
;
576 struct brw_tcs_prog_data
578 struct brw_vue_prog_data base
;
580 /** Number vertices in output patch */
585 struct brw_tes_prog_data
587 struct brw_vue_prog_data base
;
589 enum brw_tess_partitioning partitioning
;
590 enum brw_tess_output_topology output_topology
;
591 enum brw_tess_domain domain
;
594 struct brw_gs_prog_data
596 struct brw_vue_prog_data base
;
599 * Size of an output vertex, measured in HWORDS (32 bytes).
601 unsigned output_vertex_size_hwords
;
603 unsigned output_topology
;
606 * Size of the control data (cut bits or StreamID bits), in hwords (32
607 * bytes). 0 if there is no control data.
609 unsigned control_data_header_size_hwords
;
612 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
613 * if the control data is StreamID bits, or
614 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
615 * Ignored if control_data_header_size is 0.
617 unsigned control_data_format
;
619 bool include_primitive_id
;
622 * The number of vertices emitted, if constant - otherwise -1.
624 int static_vertex_count
;
629 * Gen6 transform feedback enabled flag.
631 bool gen6_xfb_enabled
;
634 * Gen6: Provoking vertex convention for odd-numbered triangles
640 * Gen6: Number of varyings that are output to transform feedback.
642 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
645 * Gen6: Map from the index of a transform feedback binding table entry to the
646 * gl_varying_slot that should be streamed out through that binding table
649 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
652 * Gen6: Map from the index of a transform feedback binding table entry to the
653 * swizzles that should be used when streaming out data through that
654 * binding table entry.
656 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
663 * Compile a vertex shader.
665 * Returns the final assembly and the program's size.
668 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
670 const struct brw_vs_prog_key
*key
,
671 struct brw_vs_prog_data
*prog_data
,
672 const struct nir_shader
*shader
,
673 gl_clip_plane
*clip_planes
,
674 bool use_legacy_snorm_formula
,
675 int shader_time_index
,
676 unsigned *final_assembly_size
,
680 * Compile a tessellation evaluation shader.
682 * Returns the final assembly and the program's size.
685 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
687 const struct brw_tes_prog_key
*key
,
688 struct brw_tes_prog_data
*prog_data
,
689 const struct nir_shader
*shader
,
690 struct gl_shader_program
*shader_prog
,
691 int shader_time_index
,
692 unsigned *final_assembly_size
,
696 * Compile a vertex shader.
698 * Returns the final assembly and the program's size.
701 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
703 const struct brw_gs_prog_key
*key
,
704 struct brw_gs_prog_data
*prog_data
,
705 const struct nir_shader
*shader
,
706 struct gl_shader_program
*shader_prog
,
707 int shader_time_index
,
708 unsigned *final_assembly_size
,
712 * Compile a fragment shader.
714 * Returns the final assembly and the program's size.
717 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
719 const struct brw_wm_prog_key
*key
,
720 struct brw_wm_prog_data
*prog_data
,
721 const struct nir_shader
*shader
,
722 struct gl_program
*prog
,
723 int shader_time_index8
,
724 int shader_time_index16
,
726 unsigned *final_assembly_size
,
730 * Compile a compute shader.
732 * Returns the final assembly and the program's size.
735 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
737 const struct brw_cs_prog_key
*key
,
738 struct brw_cs_prog_data
*prog_data
,
739 const struct nir_shader
*shader
,
740 int shader_time_index
,
741 unsigned *final_assembly_size
,
745 * Fill out local id payload for compute shader according to cs_prog_data.
748 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*cs_prog_data
,
749 void *buffer
, uint32_t threads
, uint32_t stride
);