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27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
36 struct brw_geometry_program
;
37 union gl_constant_value
;
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
90 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
91 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 bool scalar_stage
[MESA_SHADER_STAGES
];
94 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
97 * Apply workarounds for SIN and COS output range problems.
98 * This can negatively impact performance.
105 * Program key structures.
107 * When drawing, we look for the currently bound shaders in the program
108 * cache. This is essentially a hash table lookup, and these are the keys.
110 * Sometimes OpenGL features specified as state need to be simulated via
111 * shader code, due to a mismatch between the API and the hardware. This
112 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
113 * in the program key so it's considered when searching for a program. If
114 * we haven't seen a particular combination before, we have to recompile a
115 * new specialized version.
117 * Shader compilation should not look up state in gl_context directly, but
118 * instead use the copy in the program key. This guarantees recompiles will
124 enum PACKED gen6_gather_sampler_wa
{
125 WA_SIGN
= 1, /* whether we need to sign extend */
126 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
127 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
131 * Sampler information needed by VS, WM, and GS program cache keys.
133 struct brw_sampler_prog_key_data
{
135 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
137 uint16_t swizzles
[MAX_SAMPLERS
];
139 uint32_t gl_clamp_mask
[3];
142 * For RG32F, gather4's channel select is broken.
144 uint32_t gather_channel_quirk_mask
;
147 * Whether this sampler uses the compressed multisample surface layout.
149 uint32_t compressed_multisample_layout_mask
;
152 * Whether this sampler is using 16x multisampling. If so fetching from
153 * this sampler will be handled with a different instruction, ld2dms_w
159 * For Sandybridge, which shader w/a we need for gather quirks.
161 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
165 /** The program key for Vertex Shaders. */
166 struct brw_vs_prog_key
{
167 unsigned program_string_id
;
170 * Per-attribute workaround flags
172 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
174 bool copy_edgeflag
:1;
176 bool clamp_vertex_color
:1;
179 * How many user clipping planes are being uploaded to the vertex shader as
182 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
185 unsigned nr_userclip_plane_consts
:4;
188 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
189 * are going to be replaced with point coordinates (as a consequence of a
190 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
191 * our SF thread requires exact matching between VS outputs and FS inputs,
192 * these texture coordinates will need to be unconditionally included in
193 * the VUE, even if they aren't written by the vertex shader.
195 uint8_t point_coord_replace
;
197 struct brw_sampler_prog_key_data tex
;
200 /** The program key for Tessellation Control Shaders. */
201 struct brw_tcs_prog_key
203 unsigned program_string_id
;
205 GLenum tes_primitive_mode
;
207 unsigned input_vertices
;
209 /** A bitfield of per-patch outputs written. */
210 uint32_t patch_outputs_written
;
212 /** A bitfield of per-vertex outputs written. */
213 uint64_t outputs_written
;
215 struct brw_sampler_prog_key_data tex
;
218 /** The program key for Tessellation Evaluation Shaders. */
219 struct brw_tes_prog_key
221 unsigned program_string_id
;
223 /** A bitfield of per-patch inputs read. */
224 uint32_t patch_inputs_read
;
226 /** A bitfield of per-vertex inputs read. */
227 uint64_t inputs_read
;
229 struct brw_sampler_prog_key_data tex
;
232 /** The program key for Geometry Shaders. */
233 struct brw_gs_prog_key
235 unsigned program_string_id
;
237 struct brw_sampler_prog_key_data tex
;
240 /** The program key for Fragment/Pixel Shaders. */
241 struct brw_wm_prog_key
{
245 unsigned nr_color_regions
:5;
246 bool replicate_alpha
:1;
247 bool render_to_fbo
:1;
248 bool clamp_fragment_color
:1;
249 bool persample_interp
:1;
250 bool multisample_fbo
:1;
252 bool high_quality_derivatives
:1;
253 bool force_dual_color_blend
:1;
255 uint16_t drawable_height
;
256 uint64_t input_slots_valid
;
257 unsigned program_string_id
;
258 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
259 float alpha_test_ref
;
261 struct brw_sampler_prog_key_data tex
;
264 struct brw_cs_prog_key
{
265 uint32_t program_string_id
;
266 struct brw_sampler_prog_key_data tex
;
270 * Image metadata structure as laid out in the shader parameter
271 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
272 * able to use them. That's okay because the padding and any unused
273 * entries [most of them except when we're doing untyped surface
274 * access] will be removed by the uniform packing pass.
276 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
277 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
278 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
279 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
280 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
281 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
282 #define BRW_IMAGE_PARAM_SIZE 24
284 struct brw_image_param
{
285 /** Surface binding table index. */
286 uint32_t surface_idx
;
288 /** Offset applied to the X and Y surface coordinates. */
291 /** Surface X, Y and Z dimensions. */
294 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
295 * pixels, vertical slice stride in pixels.
299 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
303 * Right shift to apply for bit 6 address swizzling. Two different
304 * swizzles can be specified and will be applied one after the other. The
305 * resulting address will be:
307 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
308 * (addr >> swizzling[1])))
310 * Use \c 0xff if any of the swizzles is not required.
312 uint32_t swizzling
[2];
315 struct brw_stage_prog_data
{
317 /** size of our binding table. */
321 * surface indices for the various groups of surfaces
323 uint32_t pull_constants_start
;
324 uint32_t texture_start
;
325 uint32_t gather_texture_start
;
329 uint32_t image_start
;
330 uint32_t shader_time_start
;
334 GLuint nr_params
; /**< number of float params/constants */
335 GLuint nr_pull_params
;
336 unsigned nr_image_params
;
338 unsigned curb_read_length
;
339 unsigned total_scratch
;
340 unsigned total_shared
;
343 * Register where the thread expects to find input data from the URB
344 * (typically uniforms, followed by vertex or fragment attributes).
346 unsigned dispatch_grf_start_reg
;
348 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
350 /* Pointers to tracked values (only valid once
351 * _mesa_load_state_parameters has been called at runtime).
353 const union gl_constant_value
**param
;
354 const union gl_constant_value
**pull_param
;
356 /** Image metadata passed to the shader as uniforms. */
357 struct brw_image_param
*image_param
;
360 /* Data about a particular attempt to compile a program. Note that
361 * there can be many of these, each in a different GL state
362 * corresponding to a different brw_wm_prog_key struct, with different
365 struct brw_wm_prog_data
{
366 struct brw_stage_prog_data base
;
368 GLuint num_varying_inputs
;
370 uint8_t reg_blocks_0
;
371 uint8_t reg_blocks_2
;
373 uint8_t dispatch_grf_start_reg_2
;
374 uint32_t prog_offset_2
;
378 * surface indices the WM-specific surfaces
380 uint32_t render_target_start
;
384 uint8_t computed_depth_mode
;
385 bool computed_stencil
;
387 bool early_fragment_tests
;
391 bool persample_dispatch
;
392 bool uses_pos_offset
;
397 bool uses_sample_mask
;
401 * Mask of which interpolation modes are required by the fragment shader.
402 * Used in hardware setup on gen6+.
404 uint32_t barycentric_interp_modes
;
407 * Mask of which FS inputs are marked flat by the shader source. This is
408 * needed for setting up 3DSTATE_SF/SBE.
410 uint32_t flat_inputs
;
413 * Map from gl_varying_slot to the position within the FS setup data
414 * payload where the varying's attribute vertex deltas should be delivered.
415 * For varying slots that are not used by the FS, the value is -1.
417 int urb_setup
[VARYING_SLOT_MAX
];
420 struct brw_cs_prog_data
{
421 struct brw_stage_prog_data base
;
423 GLuint dispatch_grf_start_reg_16
;
424 unsigned local_size
[3];
427 bool uses_num_work_groups
;
428 unsigned local_invocation_id_regs
;
432 * surface indices the CS-specific surfaces
434 uint32_t work_groups_start
;
440 * Enum representing the i965-specific vertex results that don't correspond
441 * exactly to any element of gl_varying_slot. The values of this enum are
442 * assigned such that they don't conflict with gl_varying_slot.
446 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
447 BRW_VARYING_SLOT_PAD
,
449 * Technically this is not a varying but just a placeholder that
450 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
451 * builtin variable to be compiled correctly. see compile_sf_prog() for
454 BRW_VARYING_SLOT_PNTC
,
455 BRW_VARYING_SLOT_COUNT
459 * Data structure recording the relationship between the gl_varying_slot enum
460 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
461 * single octaword within the VUE (128 bits).
463 * Note that each BRW register contains 256 bits (2 octawords), so when
464 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
465 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
466 * in a vertex shader), each register corresponds to a single VUE slot, since
467 * it contains data for two separate vertices.
471 * Bitfield representing all varying slots that are (a) stored in this VUE
472 * map, and (b) actually written by the shader. Does not include any of
473 * the additional varying slots defined in brw_varying_slot.
475 GLbitfield64 slots_valid
;
478 * Is this VUE map for a separate shader pipeline?
480 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
481 * without the linker having a chance to dead code eliminate unused varyings.
483 * This means that we have to use a fixed slot layout, based on the output's
484 * location field, rather than assigning slots in a compact contiguous block.
489 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
490 * not stored in a slot (because they are not written, or because
491 * additional processing is applied before storing them in the VUE), the
494 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
497 * Map from VUE slot to gl_varying_slot value. For slots that do not
498 * directly correspond to a gl_varying_slot, the value comes from
501 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
503 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
506 * Total number of VUE slots in use
511 * Number of per-patch VUE slots. Only valid for tessellation control
512 * shader outputs and tessellation evaluation shader inputs.
514 int num_per_patch_slots
;
517 * Number of per-vertex VUE slots. Only valid for tessellation control
518 * shader outputs and tessellation evaluation shader inputs.
520 int num_per_vertex_slots
;
523 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
526 * Convert a VUE slot number into a byte offset within the VUE.
528 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
534 * Convert a vertex output (brw_varying_slot) into a byte offset within the
538 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
540 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
543 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
544 struct brw_vue_map
*vue_map
,
545 GLbitfield64 slots_valid
,
546 bool separate_shader
);
548 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
549 const GLbitfield64 slots_valid
,
550 const GLbitfield is_patch
);
552 enum shader_dispatch_mode
{
553 DISPATCH_MODE_4X1_SINGLE
= 0,
554 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
555 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
556 DISPATCH_MODE_SIMD8
= 3,
560 * @defgroup Tessellator parameter enumerations.
562 * These correspond to the hardware values in 3DSTATE_TE, and are provided
563 * as part of the tessellation evaluation shader.
567 enum brw_tess_partitioning
{
568 BRW_TESS_PARTITIONING_INTEGER
= 0,
569 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
570 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
573 enum brw_tess_output_topology
{
574 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
575 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
576 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
577 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
580 enum brw_tess_domain
{
581 BRW_TESS_DOMAIN_QUAD
= 0,
582 BRW_TESS_DOMAIN_TRI
= 1,
583 BRW_TESS_DOMAIN_ISOLINE
= 2,
587 struct brw_vue_prog_data
{
588 struct brw_stage_prog_data base
;
589 struct brw_vue_map vue_map
;
591 /** Should the hardware deliver input VUE handles for URB pull loads? */
592 bool include_vue_handles
;
594 GLuint urb_read_length
;
597 uint32_t cull_distance_mask
;
599 /* Used for calculating urb partitions. In the VS, this is the size of the
600 * URB entry used for both input and output to the thread. In the GS, this
601 * is the size of the URB entry used for output.
603 GLuint urb_entry_size
;
605 enum shader_dispatch_mode dispatch_mode
;
608 struct brw_vs_prog_data
{
609 struct brw_vue_prog_data base
;
611 GLbitfield64 inputs_read
;
613 unsigned nr_attributes
;
614 unsigned nr_attribute_slots
;
617 bool uses_instanceid
;
618 bool uses_basevertex
;
619 bool uses_baseinstance
;
623 struct brw_tcs_prog_data
625 struct brw_vue_prog_data base
;
627 /** Number vertices in output patch */
632 struct brw_tes_prog_data
634 struct brw_vue_prog_data base
;
636 enum brw_tess_partitioning partitioning
;
637 enum brw_tess_output_topology output_topology
;
638 enum brw_tess_domain domain
;
641 struct brw_gs_prog_data
643 struct brw_vue_prog_data base
;
645 unsigned vertices_in
;
648 * Size of an output vertex, measured in HWORDS (32 bytes).
650 unsigned output_vertex_size_hwords
;
652 unsigned output_topology
;
655 * Size of the control data (cut bits or StreamID bits), in hwords (32
656 * bytes). 0 if there is no control data.
658 unsigned control_data_header_size_hwords
;
661 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
662 * if the control data is StreamID bits, or
663 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
664 * Ignored if control_data_header_size is 0.
666 unsigned control_data_format
;
668 bool include_primitive_id
;
671 * The number of vertices emitted, if constant - otherwise -1.
673 int static_vertex_count
;
678 * Gen6 transform feedback enabled flag.
680 bool gen6_xfb_enabled
;
683 * Gen6: Provoking vertex convention for odd-numbered triangles
689 * Gen6: Number of varyings that are output to transform feedback.
691 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
694 * Gen6: Map from the index of a transform feedback binding table entry to the
695 * gl_varying_slot that should be streamed out through that binding table
698 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
701 * Gen6: Map from the index of a transform feedback binding table entry to the
702 * swizzles that should be used when streaming out data through that
703 * binding table entry.
705 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
711 struct brw_compiler
*
712 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
715 * Compile a vertex shader.
717 * Returns the final assembly and the program's size.
720 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
722 const struct brw_vs_prog_key
*key
,
723 struct brw_vs_prog_data
*prog_data
,
724 const struct nir_shader
*shader
,
725 gl_clip_plane
*clip_planes
,
726 bool use_legacy_snorm_formula
,
727 int shader_time_index
,
728 unsigned *final_assembly_size
,
732 * Compile a tessellation control shader.
734 * Returns the final assembly and the program's size.
737 brw_compile_tcs(const struct brw_compiler
*compiler
,
740 const struct brw_tcs_prog_key
*key
,
741 struct brw_tcs_prog_data
*prog_data
,
742 const struct nir_shader
*nir
,
743 int shader_time_index
,
744 unsigned *final_assembly_size
,
748 * Compile a tessellation evaluation shader.
750 * Returns the final assembly and the program's size.
753 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
755 const struct brw_tes_prog_key
*key
,
756 struct brw_tes_prog_data
*prog_data
,
757 const struct nir_shader
*shader
,
758 struct gl_shader_program
*shader_prog
,
759 int shader_time_index
,
760 unsigned *final_assembly_size
,
764 * Compile a vertex shader.
766 * Returns the final assembly and the program's size.
769 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
771 const struct brw_gs_prog_key
*key
,
772 struct brw_gs_prog_data
*prog_data
,
773 const struct nir_shader
*shader
,
774 struct gl_shader_program
*shader_prog
,
775 int shader_time_index
,
776 unsigned *final_assembly_size
,
780 * Compile a fragment shader.
782 * Returns the final assembly and the program's size.
785 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
787 const struct brw_wm_prog_key
*key
,
788 struct brw_wm_prog_data
*prog_data
,
789 const struct nir_shader
*shader
,
790 struct gl_program
*prog
,
791 int shader_time_index8
,
792 int shader_time_index16
,
795 unsigned *final_assembly_size
,
799 * Compile a compute shader.
801 * Returns the final assembly and the program's size.
804 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
806 const struct brw_cs_prog_key
*key
,
807 struct brw_cs_prog_data
*prog_data
,
808 const struct nir_shader
*shader
,
809 int shader_time_index
,
810 unsigned *final_assembly_size
,
814 * Fill out local id payload for compute shader according to cs_prog_data.
817 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*cs_prog_data
,
818 void *buffer
, uint32_t threads
, uint32_t stride
);