src/mesa/drivers/dri/i965/brw_compiler.h

   1 /*
   2  * Copyright © 2010 - 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdio.h>
  27 #include "brw_device_info.h"
  28 #include "main/mtypes.h"
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 struct ra_regs;
  35 struct nir_shader;
  36 struct brw_geometry_program;
  37 union gl_constant_value;
  38
  39 struct brw_compiler {
  40    const struct brw_device_info *devinfo;
  41
  42    struct {
  43       struct ra_regs *regs;
  44
  45       /**
  46        * Array of the ra classes for the unaligned contiguous register
  47        * block sizes used.
  48        */
  49       int *classes;
  50
  51       /**
  52        * Mapping for register-allocated objects in *regs to the first
  53        * GRF for that object.
  54        */
  55       uint8_t *ra_reg_to_grf;
  56    } vec4_reg_set;
  57
  58    struct {
  59       struct ra_regs *regs;
  60
  61       /**
  62        * Array of the ra classes for the unaligned contiguous register
  63        * block sizes used, indexed by register size.
  64        */
  65       int classes[16];
  66
  67       /**
  68        * Mapping from classes to ra_reg ranges.  Each of the per-size
  69        * classes corresponds to a range of ra_reg nodes.  This array stores
  70        * those ranges in the form of first ra_reg in each class and the
  71        * total number of ra_reg elements in the last array element.  This
  72        * way the range of the i'th class is given by:
  73        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  74        */
  75       int class_to_ra_reg_range[17];
  76
  77       /**
  78        * Mapping for register-allocated objects in *regs to the first
  79        * GRF for that object.
  80        */
  81       uint8_t *ra_reg_to_grf;
  82
  83       /**
  84        * ra class for the aligned pairs we use for PLN, which doesn't
  85        * appear in *classes.
  86        */
  87       int aligned_pairs_class;
  88    } fs_reg_sets[3];
  89
  90    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  91    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92
  93    bool scalar_stage[MESA_SHADER_STAGES];
  94    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  95
  96    /**
  97     * Apply workarounds for SIN and COS output range problems.
  98     * This can negatively impact performance.
  99     */
 100    bool precise_trig;
 101 };
 102
 103
 104 /**
 105  * Program key structures.
 106  *
 107  * When drawing, we look for the currently bound shaders in the program
 108  * cache.  This is essentially a hash table lookup, and these are the keys.
 109  *
 110  * Sometimes OpenGL features specified as state need to be simulated via
 111  * shader code, due to a mismatch between the API and the hardware.  This
 112  * is often referred to as "non-orthagonal state" or "NOS".  We store NOS
 113  * in the program key so it's considered when searching for a program.  If
 114  * we haven't seen a particular combination before, we have to recompile a
 115  * new specialized version.
 116  *
 117  * Shader compilation should not look up state in gl_context directly, but
 118  * instead use the copy in the program key.  This guarantees recompiles will
 119  * happen correctly.
 120  *
 121  *  @{
 122  */
 123
 124 enum PACKED gen6_gather_sampler_wa {
 125    WA_SIGN = 1,      /* whether we need to sign extend */
 126    WA_8BIT = 2,      /* if we have an 8bit format needing wa */
 127    WA_16BIT = 4,     /* if we have a 16bit format needing wa */
 128 };
 129
 130 /**
 131  * Sampler information needed by VS, WM, and GS program cache keys.
 132  */
 133 struct brw_sampler_prog_key_data {
 134    /**
 135     * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
 136     */
 137    uint16_t swizzles[MAX_SAMPLERS];
 138
 139    uint32_t gl_clamp_mask[3];
 140
 141    /**
 142     * For RG32F, gather4's channel select is broken.
 143     */
 144    uint32_t gather_channel_quirk_mask;
 145
 146    /**
 147     * Whether this sampler uses the compressed multisample surface layout.
 148     */
 149    uint32_t compressed_multisample_layout_mask;
 150
 151    /**
 152     * Whether this sampler is using 16x multisampling. If so fetching from
 153     * this sampler will be handled with a different instruction, ld2dms_w
 154     * instead of ld2dms.
 155     */
 156    uint32_t msaa_16;
 157
 158    /**
 159     * For Sandybridge, which shader w/a we need for gather quirks.
 160     */
 161    enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
 162
 163    /**
 164     * Texture units that have a YUV image bound.
 165     */
 166    uint32_t y_u_v_image_mask;
 167    uint32_t y_uv_image_mask;
 168    uint32_t yx_xuxv_image_mask;
 169 };
 170
 171
 172 /** The program key for Vertex Shaders. */
 173 struct brw_vs_prog_key {
 174    unsigned program_string_id;
 175
 176    /*
 177     * Per-attribute workaround flags
 178     */
 179    uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
 180
 181    bool copy_edgeflag:1;
 182
 183    bool clamp_vertex_color:1;
 184
 185    /**
 186     * How many user clipping planes are being uploaded to the vertex shader as
 187     * push constants.
 188     *
 189     * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
 190     * clip distances.
 191     */
 192    unsigned nr_userclip_plane_consts:4;
 193
 194    /**
 195     * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
 196     * are going to be replaced with point coordinates (as a consequence of a
 197     * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)).  Because
 198     * our SF thread requires exact matching between VS outputs and FS inputs,
 199     * these texture coordinates will need to be unconditionally included in
 200     * the VUE, even if they aren't written by the vertex shader.
 201     */
 202    uint8_t point_coord_replace;
 203
 204    struct brw_sampler_prog_key_data tex;
 205 };
 206
 207 /** The program key for Tessellation Control Shaders. */
 208 struct brw_tcs_prog_key
 209 {
 210    unsigned program_string_id;
 211
 212    GLenum tes_primitive_mode;
 213
 214    unsigned input_vertices;
 215
 216    /** A bitfield of per-patch outputs written. */
 217    uint32_t patch_outputs_written;
 218
 219    /** A bitfield of per-vertex outputs written. */
 220    uint64_t outputs_written;
 221
 222    struct brw_sampler_prog_key_data tex;
 223 };
 224
 225 /** The program key for Tessellation Evaluation Shaders. */
 226 struct brw_tes_prog_key
 227 {
 228    unsigned program_string_id;
 229
 230    /** A bitfield of per-patch inputs read. */
 231    uint32_t patch_inputs_read;
 232
 233    /** A bitfield of per-vertex inputs read. */
 234    uint64_t inputs_read;
 235
 236    struct brw_sampler_prog_key_data tex;
 237 };
 238
 239 /** The program key for Geometry Shaders. */
 240 struct brw_gs_prog_key
 241 {
 242    unsigned program_string_id;
 243
 244    struct brw_sampler_prog_key_data tex;
 245 };
 246
 247 /** The program key for Fragment/Pixel Shaders. */
 248 struct brw_wm_prog_key {
 249    uint8_t iz_lookup;
 250    bool stats_wm:1;
 251    bool flat_shade:1;
 252    unsigned nr_color_regions:5;
 253    bool replicate_alpha:1;
 254    bool clamp_fragment_color:1;
 255    bool persample_interp:1;
 256    bool multisample_fbo:1;
 257    unsigned line_aa:2;
 258    bool high_quality_derivatives:1;
 259    bool force_dual_color_blend:1;
 260
 261    uint16_t drawable_height;
 262    uint64_t input_slots_valid;
 263    unsigned program_string_id;
 264    GLenum alpha_test_func;          /* < For Gen4/5 MRT alpha test */
 265    float alpha_test_ref;
 266
 267    struct brw_sampler_prog_key_data tex;
 268 };
 269
 270 struct brw_cs_prog_key {
 271    uint32_t program_string_id;
 272    struct brw_sampler_prog_key_data tex;
 273 };
 274
 275 /*
 276  * Image metadata structure as laid out in the shader parameter
 277  * buffer.  Entries have to be 16B-aligned for the vec4 back-end to be
 278  * able to use them.  That's okay because the padding and any unused
 279  * entries [most of them except when we're doing untyped surface
 280  * access] will be removed by the uniform packing pass.
 281  */
 282 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET      0
 283 #define BRW_IMAGE_PARAM_OFFSET_OFFSET           4
 284 #define BRW_IMAGE_PARAM_SIZE_OFFSET             8
 285 #define BRW_IMAGE_PARAM_STRIDE_OFFSET           12
 286 #define BRW_IMAGE_PARAM_TILING_OFFSET           16
 287 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        20
 288 #define BRW_IMAGE_PARAM_SIZE                    24
 289
 290 struct brw_image_param {
 291    /** Surface binding table index. */
 292    uint32_t surface_idx;
 293
 294    /** Offset applied to the X and Y surface coordinates. */
 295    uint32_t offset[2];
 296
 297    /** Surface X, Y and Z dimensions. */
 298    uint32_t size[3];
 299
 300    /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
 301     * pixels, vertical slice stride in pixels.
 302     */
 303    uint32_t stride[4];
 304
 305    /** Log2 of the tiling modulus in the X, Y and Z dimension. */
 306    uint32_t tiling[3];
 307
 308    /**
 309     * Right shift to apply for bit 6 address swizzling.  Two different
 310     * swizzles can be specified and will be applied one after the other.  The
 311     * resulting address will be:
 312     *
 313     *  addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
 314     *                              (addr >> swizzling[1])))
 315     *
 316     * Use \c 0xff if any of the swizzles is not required.
 317     */
 318    uint32_t swizzling[2];
 319 };
 320
 321 struct brw_stage_prog_data {
 322    struct {
 323       /** size of our binding table. */
 324       uint32_t size_bytes;
 325
 326       /** @{
 327        * surface indices for the various groups of surfaces
 328        */
 329       uint32_t pull_constants_start;
 330       uint32_t texture_start;
 331       uint32_t gather_texture_start;
 332       uint32_t ubo_start;
 333       uint32_t ssbo_start;
 334       uint32_t abo_start;
 335       uint32_t image_start;
 336       uint32_t shader_time_start;
 337       uint32_t plane_start[3];
 338       /** @} */
 339    } binding_table;
 340
 341    GLuint nr_params;       /**< number of float params/constants */
 342    GLuint nr_pull_params;
 343    unsigned nr_image_params;
 344
 345    unsigned curb_read_length;
 346    unsigned total_scratch;
 347    unsigned total_shared;
 348
 349    /**
 350     * Register where the thread expects to find input data from the URB
 351     * (typically uniforms, followed by vertex or fragment attributes).
 352     */
 353    unsigned dispatch_grf_start_reg;
 354
 355    bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
 356
 357    /* Pointers to tracked values (only valid once
 358     * _mesa_load_state_parameters has been called at runtime).
 359     */
 360    const union gl_constant_value **param;
 361    const union gl_constant_value **pull_param;
 362
 363    /** Image metadata passed to the shader as uniforms. */
 364    struct brw_image_param *image_param;
 365 };
 366
 367 /* Data about a particular attempt to compile a program.  Note that
 368  * there can be many of these, each in a different GL state
 369  * corresponding to a different brw_wm_prog_key struct, with different
 370  * compiled programs.
 371  */
 372 struct brw_wm_prog_data {
 373    struct brw_stage_prog_data base;
 374
 375    GLuint num_varying_inputs;
 376
 377    uint8_t reg_blocks_0;
 378    uint8_t reg_blocks_2;
 379
 380    uint8_t dispatch_grf_start_reg_2;
 381    uint32_t prog_offset_2;
 382
 383    struct {
 384       /** @{
 385        * surface indices the WM-specific surfaces
 386        */
 387       uint32_t render_target_start;
 388       /** @} */
 389    } binding_table;
 390
 391    uint8_t computed_depth_mode;
 392    bool computed_stencil;
 393
 394    bool early_fragment_tests;
 395    bool dispatch_8;
 396    bool dispatch_16;
 397    bool dual_src_blend;
 398    bool persample_dispatch;
 399    bool uses_pos_offset;
 400    bool uses_omask;
 401    bool uses_kill;
 402    bool uses_src_depth;
 403    bool uses_src_w;
 404    bool uses_sample_mask;
 405    bool pulls_bary;
 406
 407    /**
 408     * Mask of which interpolation modes are required by the fragment shader.
 409     * Used in hardware setup on gen6+.
 410     */
 411    uint32_t barycentric_interp_modes;
 412
 413    /**
 414     * Mask of which FS inputs are marked flat by the shader source.  This is
 415     * needed for setting up 3DSTATE_SF/SBE.
 416     */
 417    uint32_t flat_inputs;
 418
 419    /**
 420     * Map from gl_varying_slot to the position within the FS setup data
 421     * payload where the varying's attribute vertex deltas should be delivered.
 422     * For varying slots that are not used by the FS, the value is -1.
 423     */
 424    int urb_setup[VARYING_SLOT_MAX];
 425 };
 426
 427 struct brw_cs_prog_data {
 428    struct brw_stage_prog_data base;
 429
 430    GLuint dispatch_grf_start_reg_16;
 431    unsigned local_size[3];
 432    unsigned simd_size;
 433    unsigned threads;
 434    bool uses_barrier;
 435    bool uses_num_work_groups;
 436    unsigned local_invocation_id_regs;
 437    int thread_local_id_index;
 438
 439    struct {
 440       /** @{
 441        * surface indices the CS-specific surfaces
 442        */
 443       uint32_t work_groups_start;
 444       /** @} */
 445    } binding_table;
 446 };
 447
 448 /**
 449  * Enum representing the i965-specific vertex results that don't correspond
 450  * exactly to any element of gl_varying_slot.  The values of this enum are
 451  * assigned such that they don't conflict with gl_varying_slot.
 452  */
 453 typedef enum
 454 {
 455    BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
 456    BRW_VARYING_SLOT_PAD,
 457    /**
 458     * Technically this is not a varying but just a placeholder that
 459     * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
 460     * builtin variable to be compiled correctly. see compile_sf_prog() for
 461     * more info.
 462     */
 463    BRW_VARYING_SLOT_PNTC,
 464    BRW_VARYING_SLOT_COUNT
 465 } brw_varying_slot;
 466
 467 /**
 468  * Data structure recording the relationship between the gl_varying_slot enum
 469  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
 470  * single octaword within the VUE (128 bits).
 471  *
 472  * Note that each BRW register contains 256 bits (2 octawords), so when
 473  * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
 474  * consecutive VUE slots.  When accessing the VUE in URB_INTERLEAVED mode (as
 475  * in a vertex shader), each register corresponds to a single VUE slot, since
 476  * it contains data for two separate vertices.
 477  */
 478 struct brw_vue_map {
 479    /**
 480     * Bitfield representing all varying slots that are (a) stored in this VUE
 481     * map, and (b) actually written by the shader.  Does not include any of
 482     * the additional varying slots defined in brw_varying_slot.
 483     */
 484    GLbitfield64 slots_valid;
 485
 486    /**
 487     * Is this VUE map for a separate shader pipeline?
 488     *
 489     * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
 490     * without the linker having a chance to dead code eliminate unused varyings.
 491     *
 492     * This means that we have to use a fixed slot layout, based on the output's
 493     * location field, rather than assigning slots in a compact contiguous block.
 494     */
 495    bool separate;
 496
 497    /**
 498     * Map from gl_varying_slot value to VUE slot.  For gl_varying_slots that are
 499     * not stored in a slot (because they are not written, or because
 500     * additional processing is applied before storing them in the VUE), the
 501     * value is -1.
 502     */
 503    signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
 504
 505    /**
 506     * Map from VUE slot to gl_varying_slot value.  For slots that do not
 507     * directly correspond to a gl_varying_slot, the value comes from
 508     * brw_varying_slot.
 509     *
 510     * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
 511     */
 512    signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
 513
 514    /**
 515     * Total number of VUE slots in use
 516     */
 517    int num_slots;
 518
 519    /**
 520     * Number of per-patch VUE slots. Only valid for tessellation control
 521     * shader outputs and tessellation evaluation shader inputs.
 522     */
 523    int num_per_patch_slots;
 524
 525    /**
 526     * Number of per-vertex VUE slots. Only valid for tessellation control
 527     * shader outputs and tessellation evaluation shader inputs.
 528     */
 529    int num_per_vertex_slots;
 530 };
 531
 532 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
 533
 534 /**
 535  * Convert a VUE slot number into a byte offset within the VUE.
 536  */
 537 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
 538 {
 539    return 16*slot;
 540 }
 541
 542 /**
 543  * Convert a vertex output (brw_varying_slot) into a byte offset within the
 544  * VUE.
 545  */
 546 static inline
 547 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
 548 {
 549    return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
 550 }
 551
 552 void brw_compute_vue_map(const struct brw_device_info *devinfo,
 553                          struct brw_vue_map *vue_map,
 554                          GLbitfield64 slots_valid,
 555                          bool separate_shader);
 556
 557 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
 558                               const GLbitfield64 slots_valid,
 559                               const GLbitfield is_patch);
 560
 561 enum shader_dispatch_mode {
 562    DISPATCH_MODE_4X1_SINGLE = 0,
 563    DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
 564    DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
 565    DISPATCH_MODE_SIMD8 = 3,
 566 };
 567
 568 /**
 569  * @defgroup Tessellator parameter enumerations.
 570  *
 571  * These correspond to the hardware values in 3DSTATE_TE, and are provided
 572  * as part of the tessellation evaluation shader.
 573  *
 574  * @{
 575  */
 576 enum brw_tess_partitioning {
 577    BRW_TESS_PARTITIONING_INTEGER         = 0,
 578    BRW_TESS_PARTITIONING_ODD_FRACTIONAL  = 1,
 579    BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
 580 };
 581
 582 enum brw_tess_output_topology {
 583    BRW_TESS_OUTPUT_TOPOLOGY_POINT   = 0,
 584    BRW_TESS_OUTPUT_TOPOLOGY_LINE    = 1,
 585    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW  = 2,
 586    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
 587 };
 588
 589 enum brw_tess_domain {
 590    BRW_TESS_DOMAIN_QUAD    = 0,
 591    BRW_TESS_DOMAIN_TRI     = 1,
 592    BRW_TESS_DOMAIN_ISOLINE = 2,
 593 };
 594 /** @} */
 595
 596 struct brw_vue_prog_data {
 597    struct brw_stage_prog_data base;
 598    struct brw_vue_map vue_map;
 599
 600    /** Should the hardware deliver input VUE handles for URB pull loads? */
 601    bool include_vue_handles;
 602
 603    GLuint urb_read_length;
 604    GLuint total_grf;
 605
 606    uint32_t cull_distance_mask;
 607
 608    /* Used for calculating urb partitions.  In the VS, this is the size of the
 609     * URB entry used for both input and output to the thread.  In the GS, this
 610     * is the size of the URB entry used for output.
 611     */
 612    GLuint urb_entry_size;
 613
 614    enum shader_dispatch_mode dispatch_mode;
 615 };
 616
 617 struct brw_vs_prog_data {
 618    struct brw_vue_prog_data base;
 619
 620    GLbitfield64 inputs_read;
 621
 622    unsigned nr_attributes;
 623    unsigned nr_attribute_slots;
 624
 625    bool uses_vertexid;
 626    bool uses_instanceid;
 627    bool uses_basevertex;
 628    bool uses_baseinstance;
 629    bool uses_drawid;
 630 };
 631
 632 struct brw_tcs_prog_data
 633 {
 634    struct brw_vue_prog_data base;
 635
 636    /** Number vertices in output patch */
 637    int instances;
 638 };
 639
 640
 641 struct brw_tes_prog_data
 642 {
 643    struct brw_vue_prog_data base;
 644
 645    enum brw_tess_partitioning partitioning;
 646    enum brw_tess_output_topology output_topology;
 647    enum brw_tess_domain domain;
 648 };
 649
 650 struct brw_gs_prog_data
 651 {
 652    struct brw_vue_prog_data base;
 653
 654    unsigned vertices_in;
 655
 656    /**
 657     * Size of an output vertex, measured in HWORDS (32 bytes).
 658     */
 659    unsigned output_vertex_size_hwords;
 660
 661    unsigned output_topology;
 662
 663    /**
 664     * Size of the control data (cut bits or StreamID bits), in hwords (32
 665     * bytes).  0 if there is no control data.
 666     */
 667    unsigned control_data_header_size_hwords;
 668
 669    /**
 670     * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
 671     * if the control data is StreamID bits, or
 672     * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
 673     * Ignored if control_data_header_size is 0.
 674     */
 675    unsigned control_data_format;
 676
 677    bool include_primitive_id;
 678
 679    /**
 680     * The number of vertices emitted, if constant - otherwise -1.
 681     */
 682    int static_vertex_count;
 683
 684    int invocations;
 685
 686    /**
 687     * Gen6 transform feedback enabled flag.
 688     */
 689    bool gen6_xfb_enabled;
 690
 691    /**
 692     * Gen6: Provoking vertex convention for odd-numbered triangles
 693     * in tristrips.
 694     */
 695    GLuint pv_first:1;
 696
 697    /**
 698     * Gen6: Number of varyings that are output to transform feedback.
 699     */
 700    GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
 701
 702    /**
 703     * Gen6: Map from the index of a transform feedback binding table entry to the
 704     * gl_varying_slot that should be streamed out through that binding table
 705     * entry.
 706     */
 707    unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
 708
 709    /**
 710     * Gen6: Map from the index of a transform feedback binding table entry to the
 711     * swizzles that should be used when streaming out data through that
 712     * binding table entry.
 713     */
 714    unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
 715 };
 716
 717
 718 /** @} */
 719
 720 struct brw_compiler *
 721 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
 722
 723 /**
 724  * Compile a vertex shader.
 725  *
 726  * Returns the final assembly and the program's size.
 727  */
 728 const unsigned *
 729 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
 730                void *mem_ctx,
 731                const struct brw_vs_prog_key *key,
 732                struct brw_vs_prog_data *prog_data,
 733                const struct nir_shader *shader,
 734                gl_clip_plane *clip_planes,
 735                bool use_legacy_snorm_formula,
 736                int shader_time_index,
 737                unsigned *final_assembly_size,
 738                char **error_str);
 739
 740 /**
 741  * Compile a tessellation control shader.
 742  *
 743  * Returns the final assembly and the program's size.
 744  */
 745 const unsigned *
 746 brw_compile_tcs(const struct brw_compiler *compiler,
 747                 void *log_data,
 748                 void *mem_ctx,
 749                 const struct brw_tcs_prog_key *key,
 750                 struct brw_tcs_prog_data *prog_data,
 751                 const struct nir_shader *nir,
 752                 int shader_time_index,
 753                 unsigned *final_assembly_size,
 754                 char **error_str);
 755
 756 /**
 757  * Compile a tessellation evaluation shader.
 758  *
 759  * Returns the final assembly and the program's size.
 760  */
 761 const unsigned *
 762 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
 763                 void *mem_ctx,
 764                 const struct brw_tes_prog_key *key,
 765                 struct brw_tes_prog_data *prog_data,
 766                 const struct nir_shader *shader,
 767                 struct gl_shader_program *shader_prog,
 768                 int shader_time_index,
 769                 unsigned *final_assembly_size,
 770                 char **error_str);
 771
 772 /**
 773  * Compile a vertex shader.
 774  *
 775  * Returns the final assembly and the program's size.
 776  */
 777 const unsigned *
 778 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
 779                void *mem_ctx,
 780                const struct brw_gs_prog_key *key,
 781                struct brw_gs_prog_data *prog_data,
 782                const struct nir_shader *shader,
 783                struct gl_shader_program *shader_prog,
 784                int shader_time_index,
 785                unsigned *final_assembly_size,
 786                char **error_str);
 787
 788 /**
 789  * Compile a fragment shader.
 790  *
 791  * Returns the final assembly and the program's size.
 792  */
 793 const unsigned *
 794 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
 795                void *mem_ctx,
 796                const struct brw_wm_prog_key *key,
 797                struct brw_wm_prog_data *prog_data,
 798                const struct nir_shader *shader,
 799                struct gl_program *prog,
 800                int shader_time_index8,
 801                int shader_time_index16,
 802                bool allow_spilling,
 803                bool use_rep_send,
 804                unsigned *final_assembly_size,
 805                char **error_str);
 806
 807 /**
 808  * Compile a compute shader.
 809  *
 810  * Returns the final assembly and the program's size.
 811  */
 812 const unsigned *
 813 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
 814                void *mem_ctx,
 815                const struct brw_cs_prog_key *key,
 816                struct brw_cs_prog_data *prog_data,
 817                const struct nir_shader *shader,
 818                int shader_time_index,
 819                unsigned *final_assembly_size,
 820                char **error_str);
 821
 822 /**
 823  * Fill out local id payload for compute shader according to cs_prog_data.
 824  */
 825 void
 826 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
 827                              void *buffer, uint32_t threads, uint32_t stride);
 828
 829 #ifdef __cplusplus
 830 } /* extern "C" */
 831 #endif