src/mesa/drivers/dri/i965/brw_compiler.h

   1 /*
   2  * Copyright © 2010 - 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdio.h>
  27 #include "brw_device_info.h"
  28 #include "main/mtypes.h"
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 struct ra_regs;
  35 struct nir_shader;
  36 struct brw_geometry_program;
  37 union gl_constant_value;
  38
  39 struct brw_compiler {
  40    const struct brw_device_info *devinfo;
  41
  42    struct {
  43       struct ra_regs *regs;
  44
  45       /**
  46        * Array of the ra classes for the unaligned contiguous register
  47        * block sizes used.
  48        */
  49       int *classes;
  50
  51       /**
  52        * Mapping for register-allocated objects in *regs to the first
  53        * GRF for that object.
  54        */
  55       uint8_t *ra_reg_to_grf;
  56    } vec4_reg_set;
  57
  58    struct {
  59       struct ra_regs *regs;
  60
  61       /**
  62        * Array of the ra classes for the unaligned contiguous register
  63        * block sizes used, indexed by register size.
  64        */
  65       int classes[16];
  66
  67       /**
  68        * Mapping from classes to ra_reg ranges.  Each of the per-size
  69        * classes corresponds to a range of ra_reg nodes.  This array stores
  70        * those ranges in the form of first ra_reg in each class and the
  71        * total number of ra_reg elements in the last array element.  This
  72        * way the range of the i'th class is given by:
  73        * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
  74        */
  75       int class_to_ra_reg_range[17];
  76
  77       /**
  78        * Mapping for register-allocated objects in *regs to the first
  79        * GRF for that object.
  80        */
  81       uint8_t *ra_reg_to_grf;
  82
  83       /**
  84        * ra class for the aligned pairs we use for PLN, which doesn't
  85        * appear in *classes.
  86        */
  87       int aligned_pairs_class;
  88    } fs_reg_sets[2];
  89
  90    void (*shader_debug_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  91    void (*shader_perf_log)(void *, const char *str, ...) PRINTFLIKE(2, 3);
  92
  93    bool scalar_stage[MESA_SHADER_STAGES];
  94    struct gl_shader_compiler_options glsl_compiler_options[MESA_SHADER_STAGES];
  95 };
  96
  97
  98 /**
  99  * Program key structures.
 100  *
 101  * When drawing, we look for the currently bound shaders in the program
 102  * cache.  This is essentially a hash table lookup, and these are the keys.
 103  *
 104  * Sometimes OpenGL features specified as state need to be simulated via
 105  * shader code, due to a mismatch between the API and the hardware.  This
 106  * is often referred to as "non-orthagonal state" or "NOS".  We store NOS
 107  * in the program key so it's considered when searching for a program.  If
 108  * we haven't seen a particular combination before, we have to recompile a
 109  * new specialized version.
 110  *
 111  * Shader compilation should not look up state in gl_context directly, but
 112  * instead use the copy in the program key.  This guarantees recompiles will
 113  * happen correctly.
 114  *
 115  *  @{
 116  */
 117
 118 enum PACKED gen6_gather_sampler_wa {
 119    WA_SIGN = 1,      /* whether we need to sign extend */
 120    WA_8BIT = 2,      /* if we have an 8bit format needing wa */
 121    WA_16BIT = 4,     /* if we have a 16bit format needing wa */
 122 };
 123
 124 /**
 125  * Sampler information needed by VS, WM, and GS program cache keys.
 126  */
 127 struct brw_sampler_prog_key_data {
 128    /**
 129     * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
 130     */
 131    uint16_t swizzles[MAX_SAMPLERS];
 132
 133    uint32_t gl_clamp_mask[3];
 134
 135    /**
 136     * For RG32F, gather4's channel select is broken.
 137     */
 138    uint32_t gather_channel_quirk_mask;
 139
 140    /**
 141     * Whether this sampler uses the compressed multisample surface layout.
 142     */
 143    uint32_t compressed_multisample_layout_mask;
 144
 145    /**
 146     * Whether this sampler is using 16x multisampling. If so fetching from
 147     * this sampler will be handled with a different instruction, ld2dms_w
 148     * instead of ld2dms.
 149     */
 150    uint32_t msaa_16;
 151
 152    /**
 153     * For Sandybridge, which shader w/a we need for gather quirks.
 154     */
 155    enum gen6_gather_sampler_wa gen6_gather_wa[MAX_SAMPLERS];
 156 };
 157
 158
 159 /** The program key for Vertex Shaders. */
 160 struct brw_vs_prog_key {
 161    unsigned program_string_id;
 162
 163    /*
 164     * Per-attribute workaround flags
 165     */
 166    uint8_t gl_attrib_wa_flags[VERT_ATTRIB_MAX];
 167
 168    bool copy_edgeflag:1;
 169
 170    bool clamp_vertex_color:1;
 171
 172    /**
 173     * How many user clipping planes are being uploaded to the vertex shader as
 174     * push constants.
 175     *
 176     * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
 177     * clip distances.
 178     */
 179    unsigned nr_userclip_plane_consts:4;
 180
 181    /**
 182     * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
 183     * are going to be replaced with point coordinates (as a consequence of a
 184     * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)).  Because
 185     * our SF thread requires exact matching between VS outputs and FS inputs,
 186     * these texture coordinates will need to be unconditionally included in
 187     * the VUE, even if they aren't written by the vertex shader.
 188     */
 189    uint8_t point_coord_replace;
 190
 191    struct brw_sampler_prog_key_data tex;
 192 };
 193
 194 /** The program key for Tessellation Control Shaders. */
 195 struct brw_tcs_prog_key
 196 {
 197    unsigned program_string_id;
 198
 199    GLenum tes_primitive_mode;
 200
 201    unsigned input_vertices;
 202
 203    struct brw_sampler_prog_key_data tex;
 204 };
 205
 206 /** The program key for Tessellation Evaluation Shaders. */
 207 struct brw_tes_prog_key
 208 {
 209    unsigned program_string_id;
 210
 211    struct brw_sampler_prog_key_data tex;
 212 };
 213
 214 /** The program key for Geometry Shaders. */
 215 struct brw_gs_prog_key
 216 {
 217    unsigned program_string_id;
 218
 219    struct brw_sampler_prog_key_data tex;
 220 };
 221
 222 /** The program key for Fragment/Pixel Shaders. */
 223 struct brw_wm_prog_key {
 224    uint8_t iz_lookup;
 225    bool stats_wm:1;
 226    bool flat_shade:1;
 227    bool persample_shading:1;
 228    bool persample_2x:1;
 229    unsigned nr_color_regions:5;
 230    bool replicate_alpha:1;
 231    bool render_to_fbo:1;
 232    bool clamp_fragment_color:1;
 233    bool compute_pos_offset:1;
 234    bool compute_sample_id:1;
 235    unsigned line_aa:2;
 236    bool high_quality_derivatives:1;
 237
 238    uint16_t drawable_height;
 239    uint64_t input_slots_valid;
 240    unsigned program_string_id;
 241    GLenum alpha_test_func;          /* < For Gen4/5 MRT alpha test */
 242    float alpha_test_ref;
 243
 244    struct brw_sampler_prog_key_data tex;
 245 };
 246
 247 struct brw_cs_prog_key {
 248    uint32_t program_string_id;
 249    struct brw_sampler_prog_key_data tex;
 250 };
 251
 252 /*
 253  * Image metadata structure as laid out in the shader parameter
 254  * buffer.  Entries have to be 16B-aligned for the vec4 back-end to be
 255  * able to use them.  That's okay because the padding and any unused
 256  * entries [most of them except when we're doing untyped surface
 257  * access] will be removed by the uniform packing pass.
 258  */
 259 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET      0
 260 #define BRW_IMAGE_PARAM_OFFSET_OFFSET           4
 261 #define BRW_IMAGE_PARAM_SIZE_OFFSET             8
 262 #define BRW_IMAGE_PARAM_STRIDE_OFFSET           12
 263 #define BRW_IMAGE_PARAM_TILING_OFFSET           16
 264 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET        20
 265 #define BRW_IMAGE_PARAM_SIZE                    24
 266
 267 struct brw_image_param {
 268    /** Surface binding table index. */
 269    uint32_t surface_idx;
 270
 271    /** Offset applied to the X and Y surface coordinates. */
 272    uint32_t offset[2];
 273
 274    /** Surface X, Y and Z dimensions. */
 275    uint32_t size[3];
 276
 277    /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
 278     * pixels, vertical slice stride in pixels.
 279     */
 280    uint32_t stride[4];
 281
 282    /** Log2 of the tiling modulus in the X, Y and Z dimension. */
 283    uint32_t tiling[3];
 284
 285    /**
 286     * Right shift to apply for bit 6 address swizzling.  Two different
 287     * swizzles can be specified and will be applied one after the other.  The
 288     * resulting address will be:
 289     *
 290     *  addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
 291     *                              (addr >> swizzling[1])))
 292     *
 293     * Use \c 0xff if any of the swizzles is not required.
 294     */
 295    uint32_t swizzling[2];
 296 };
 297
 298 struct brw_stage_prog_data {
 299    struct {
 300       /** size of our binding table. */
 301       uint32_t size_bytes;
 302
 303       /** @{
 304        * surface indices for the various groups of surfaces
 305        */
 306       uint32_t pull_constants_start;
 307       uint32_t texture_start;
 308       uint32_t gather_texture_start;
 309       uint32_t ubo_start;
 310       uint32_t ssbo_start;
 311       uint32_t abo_start;
 312       uint32_t image_start;
 313       uint32_t shader_time_start;
 314       /** @} */
 315    } binding_table;
 316
 317    GLuint nr_params;       /**< number of float params/constants */
 318    GLuint nr_pull_params;
 319    unsigned nr_image_params;
 320
 321    unsigned curb_read_length;
 322    unsigned total_scratch;
 323    unsigned total_shared;
 324
 325    /**
 326     * Register where the thread expects to find input data from the URB
 327     * (typically uniforms, followed by vertex or fragment attributes).
 328     */
 329    unsigned dispatch_grf_start_reg;
 330
 331    bool use_alt_mode; /**< Use ALT floating point mode?  Otherwise, IEEE. */
 332
 333    /* Pointers to tracked values (only valid once
 334     * _mesa_load_state_parameters has been called at runtime).
 335     */
 336    const union gl_constant_value **param;
 337    const union gl_constant_value **pull_param;
 338
 339    /** Image metadata passed to the shader as uniforms. */
 340    struct brw_image_param *image_param;
 341 };
 342
 343 /* Data about a particular attempt to compile a program.  Note that
 344  * there can be many of these, each in a different GL state
 345  * corresponding to a different brw_wm_prog_key struct, with different
 346  * compiled programs.
 347  */
 348 struct brw_wm_prog_data {
 349    struct brw_stage_prog_data base;
 350
 351    GLuint num_varying_inputs;
 352
 353    GLuint dispatch_grf_start_reg_16;
 354    GLuint reg_blocks;
 355    GLuint reg_blocks_16;
 356
 357    struct {
 358       /** @{
 359        * surface indices the WM-specific surfaces
 360        */
 361       uint32_t render_target_start;
 362       /** @} */
 363    } binding_table;
 364
 365    uint8_t computed_depth_mode;
 366    bool computed_stencil;
 367
 368    bool early_fragment_tests;
 369    bool no_8;
 370    bool dual_src_blend;
 371    bool uses_pos_offset;
 372    bool uses_omask;
 373    bool uses_kill;
 374    bool pulls_bary;
 375    uint32_t prog_offset_16;
 376
 377    /**
 378     * Mask of which interpolation modes are required by the fragment shader.
 379     * Used in hardware setup on gen6+.
 380     */
 381    uint32_t barycentric_interp_modes;
 382
 383    /**
 384     * Map from gl_varying_slot to the position within the FS setup data
 385     * payload where the varying's attribute vertex deltas should be delivered.
 386     * For varying slots that are not used by the FS, the value is -1.
 387     */
 388    int urb_setup[VARYING_SLOT_MAX];
 389 };
 390
 391 struct brw_cs_prog_data {
 392    struct brw_stage_prog_data base;
 393
 394    GLuint dispatch_grf_start_reg_16;
 395    unsigned local_size[3];
 396    unsigned simd_size;
 397    bool uses_barrier;
 398    bool uses_num_work_groups;
 399    unsigned local_invocation_id_regs;
 400
 401    struct {
 402       /** @{
 403        * surface indices the CS-specific surfaces
 404        */
 405       uint32_t work_groups_start;
 406       /** @} */
 407    } binding_table;
 408 };
 409
 410 /**
 411  * Enum representing the i965-specific vertex results that don't correspond
 412  * exactly to any element of gl_varying_slot.  The values of this enum are
 413  * assigned such that they don't conflict with gl_varying_slot.
 414  */
 415 typedef enum
 416 {
 417    BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
 418    BRW_VARYING_SLOT_PAD,
 419    /**
 420     * Technically this is not a varying but just a placeholder that
 421     * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
 422     * builtin variable to be compiled correctly. see compile_sf_prog() for
 423     * more info.
 424     */
 425    BRW_VARYING_SLOT_PNTC,
 426    BRW_VARYING_SLOT_COUNT
 427 } brw_varying_slot;
 428
 429 /**
 430  * Data structure recording the relationship between the gl_varying_slot enum
 431  * and "slots" within the vertex URB entry (VUE).  A "slot" is defined as a
 432  * single octaword within the VUE (128 bits).
 433  *
 434  * Note that each BRW register contains 256 bits (2 octawords), so when
 435  * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
 436  * consecutive VUE slots.  When accessing the VUE in URB_INTERLEAVED mode (as
 437  * in a vertex shader), each register corresponds to a single VUE slot, since
 438  * it contains data for two separate vertices.
 439  */
 440 struct brw_vue_map {
 441    /**
 442     * Bitfield representing all varying slots that are (a) stored in this VUE
 443     * map, and (b) actually written by the shader.  Does not include any of
 444     * the additional varying slots defined in brw_varying_slot.
 445     */
 446    GLbitfield64 slots_valid;
 447
 448    /**
 449     * Is this VUE map for a separate shader pipeline?
 450     *
 451     * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
 452     * without the linker having a chance to dead code eliminate unused varyings.
 453     *
 454     * This means that we have to use a fixed slot layout, based on the output's
 455     * location field, rather than assigning slots in a compact contiguous block.
 456     */
 457    bool separate;
 458
 459    /**
 460     * Map from gl_varying_slot value to VUE slot.  For gl_varying_slots that are
 461     * not stored in a slot (because they are not written, or because
 462     * additional processing is applied before storing them in the VUE), the
 463     * value is -1.
 464     */
 465    signed char varying_to_slot[VARYING_SLOT_TESS_MAX];
 466
 467    /**
 468     * Map from VUE slot to gl_varying_slot value.  For slots that do not
 469     * directly correspond to a gl_varying_slot, the value comes from
 470     * brw_varying_slot.
 471     *
 472     * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
 473     */
 474    signed char slot_to_varying[VARYING_SLOT_TESS_MAX];
 475
 476    /**
 477     * Total number of VUE slots in use
 478     */
 479    int num_slots;
 480
 481    /**
 482     * Number of per-patch VUE slots. Only valid for tessellation control
 483     * shader outputs and tessellation evaluation shader inputs.
 484     */
 485    int num_per_patch_slots;
 486
 487    /**
 488     * Number of per-vertex VUE slots. Only valid for tessellation control
 489     * shader outputs and tessellation evaluation shader inputs.
 490     */
 491    int num_per_vertex_slots;
 492 };
 493
 494 void brw_print_vue_map(FILE *fp, const struct brw_vue_map *vue_map);
 495
 496 /**
 497  * Convert a VUE slot number into a byte offset within the VUE.
 498  */
 499 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
 500 {
 501    return 16*slot;
 502 }
 503
 504 /**
 505  * Convert a vertex output (brw_varying_slot) into a byte offset within the
 506  * VUE.
 507  */
 508 static inline
 509 GLuint brw_varying_to_offset(const struct brw_vue_map *vue_map, GLuint varying)
 510 {
 511    return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
 512 }
 513
 514 void brw_compute_vue_map(const struct brw_device_info *devinfo,
 515                          struct brw_vue_map *vue_map,
 516                          GLbitfield64 slots_valid,
 517                          bool separate_shader);
 518
 519 void brw_compute_tess_vue_map(struct brw_vue_map *const vue_map,
 520                               const GLbitfield64 slots_valid,
 521                               const GLbitfield is_patch);
 522
 523 enum shader_dispatch_mode {
 524    DISPATCH_MODE_4X1_SINGLE = 0,
 525    DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
 526    DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
 527    DISPATCH_MODE_SIMD8 = 3,
 528 };
 529
 530 /**
 531  * @defgroup Tessellator parameter enumerations.
 532  *
 533  * These correspond to the hardware values in 3DSTATE_TE, and are provided
 534  * as part of the tessellation evaluation shader.
 535  *
 536  * @{
 537  */
 538 enum brw_tess_partitioning {
 539    BRW_TESS_PARTITIONING_INTEGER         = 0,
 540    BRW_TESS_PARTITIONING_ODD_FRACTIONAL  = 1,
 541    BRW_TESS_PARTITIONING_EVEN_FRACTIONAL = 2,
 542 };
 543
 544 enum brw_tess_output_topology {
 545    BRW_TESS_OUTPUT_TOPOLOGY_POINT   = 0,
 546    BRW_TESS_OUTPUT_TOPOLOGY_LINE    = 1,
 547    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW  = 2,
 548    BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW = 3,
 549 };
 550
 551 enum brw_tess_domain {
 552    BRW_TESS_DOMAIN_QUAD    = 0,
 553    BRW_TESS_DOMAIN_TRI     = 1,
 554    BRW_TESS_DOMAIN_ISOLINE = 2,
 555 };
 556 /** @} */
 557
 558 struct brw_vue_prog_data {
 559    struct brw_stage_prog_data base;
 560    struct brw_vue_map vue_map;
 561
 562    /** Should the hardware deliver input VUE handles for URB pull loads? */
 563    bool include_vue_handles;
 564
 565    GLuint urb_read_length;
 566    GLuint total_grf;
 567
 568    /* Used for calculating urb partitions.  In the VS, this is the size of the
 569     * URB entry used for both input and output to the thread.  In the GS, this
 570     * is the size of the URB entry used for output.
 571     */
 572    GLuint urb_entry_size;
 573
 574    enum shader_dispatch_mode dispatch_mode;
 575 };
 576
 577 struct brw_vs_prog_data {
 578    struct brw_vue_prog_data base;
 579
 580    GLbitfield64 inputs_read;
 581
 582    unsigned nr_attributes;
 583
 584    bool uses_vertexid;
 585    bool uses_instanceid;
 586 };
 587
 588 struct brw_tcs_prog_data
 589 {
 590    struct brw_vue_prog_data base;
 591
 592    /** Number vertices in output patch */
 593    int instances;
 594 };
 595
 596
 597 struct brw_tes_prog_data
 598 {
 599    struct brw_vue_prog_data base;
 600
 601    enum brw_tess_partitioning partitioning;
 602    enum brw_tess_output_topology output_topology;
 603    enum brw_tess_domain domain;
 604 };
 605
 606 struct brw_gs_prog_data
 607 {
 608    struct brw_vue_prog_data base;
 609
 610    /**
 611     * Size of an output vertex, measured in HWORDS (32 bytes).
 612     */
 613    unsigned output_vertex_size_hwords;
 614
 615    unsigned output_topology;
 616
 617    /**
 618     * Size of the control data (cut bits or StreamID bits), in hwords (32
 619     * bytes).  0 if there is no control data.
 620     */
 621    unsigned control_data_header_size_hwords;
 622
 623    /**
 624     * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
 625     * if the control data is StreamID bits, or
 626     * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
 627     * Ignored if control_data_header_size is 0.
 628     */
 629    unsigned control_data_format;
 630
 631    bool include_primitive_id;
 632
 633    /**
 634     * The number of vertices emitted, if constant - otherwise -1.
 635     */
 636    int static_vertex_count;
 637
 638    int invocations;
 639
 640    /**
 641     * Gen6 transform feedback enabled flag.
 642     */
 643    bool gen6_xfb_enabled;
 644
 645    /**
 646     * Gen6: Provoking vertex convention for odd-numbered triangles
 647     * in tristrips.
 648     */
 649    GLuint pv_first:1;
 650
 651    /**
 652     * Gen6: Number of varyings that are output to transform feedback.
 653     */
 654    GLuint num_transform_feedback_bindings:7; /* 0-BRW_MAX_SOL_BINDINGS */
 655
 656    /**
 657     * Gen6: Map from the index of a transform feedback binding table entry to the
 658     * gl_varying_slot that should be streamed out through that binding table
 659     * entry.
 660     */
 661    unsigned char transform_feedback_bindings[64 /* BRW_MAX_SOL_BINDINGS */];
 662
 663    /**
 664     * Gen6: Map from the index of a transform feedback binding table entry to the
 665     * swizzles that should be used when streaming out data through that
 666     * binding table entry.
 667     */
 668    unsigned char transform_feedback_swizzles[64 /* BRW_MAX_SOL_BINDINGS */];
 669 };
 670
 671
 672 /** @} */
 673
 674 /**
 675  * Compile a vertex shader.
 676  *
 677  * Returns the final assembly and the program's size.
 678  */
 679 const unsigned *
 680 brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
 681                void *mem_ctx,
 682                const struct brw_vs_prog_key *key,
 683                struct brw_vs_prog_data *prog_data,
 684                const struct nir_shader *shader,
 685                gl_clip_plane *clip_planes,
 686                bool use_legacy_snorm_formula,
 687                int shader_time_index,
 688                unsigned *final_assembly_size,
 689                char **error_str);
 690
 691 /**
 692  * Compile a tessellation control shader.
 693  *
 694  * Returns the final assembly and the program's size.
 695  */
 696 const unsigned *
 697 brw_compile_tcs(const struct brw_compiler *compiler,
 698                 void *log_data,
 699                 void *mem_ctx,
 700                 const struct brw_tcs_prog_key *key,
 701                 struct brw_tcs_prog_data *prog_data,
 702                 const struct nir_shader *nir,
 703                 int shader_time_index,
 704                 unsigned *final_assembly_size,
 705                 char **error_str);
 706
 707 /**
 708  * Compile a tessellation evaluation shader.
 709  *
 710  * Returns the final assembly and the program's size.
 711  */
 712 const unsigned *
 713 brw_compile_tes(const struct brw_compiler *compiler, void *log_data,
 714                 void *mem_ctx,
 715                 const struct brw_tes_prog_key *key,
 716                 struct brw_tes_prog_data *prog_data,
 717                 const struct nir_shader *shader,
 718                 struct gl_shader_program *shader_prog,
 719                 int shader_time_index,
 720                 unsigned *final_assembly_size,
 721                 char **error_str);
 722
 723 /**
 724  * Compile a vertex shader.
 725  *
 726  * Returns the final assembly and the program's size.
 727  */
 728 const unsigned *
 729 brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
 730                void *mem_ctx,
 731                const struct brw_gs_prog_key *key,
 732                struct brw_gs_prog_data *prog_data,
 733                const struct nir_shader *shader,
 734                struct gl_shader_program *shader_prog,
 735                int shader_time_index,
 736                unsigned *final_assembly_size,
 737                char **error_str);
 738
 739 /**
 740  * Compile a fragment shader.
 741  *
 742  * Returns the final assembly and the program's size.
 743  */
 744 const unsigned *
 745 brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
 746                void *mem_ctx,
 747                const struct brw_wm_prog_key *key,
 748                struct brw_wm_prog_data *prog_data,
 749                const struct nir_shader *shader,
 750                struct gl_program *prog,
 751                int shader_time_index8,
 752                int shader_time_index16,
 753                bool use_rep_send,
 754                unsigned *final_assembly_size,
 755                char **error_str);
 756
 757 /**
 758  * Compile a compute shader.
 759  *
 760  * Returns the final assembly and the program's size.
 761  */
 762 const unsigned *
 763 brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
 764                void *mem_ctx,
 765                const struct brw_cs_prog_key *key,
 766                struct brw_cs_prog_data *prog_data,
 767                const struct nir_shader *shader,
 768                int shader_time_index,
 769                unsigned *final_assembly_size,
 770                char **error_str);
 771
 772 /**
 773  * Fill out local id payload for compute shader according to cs_prog_data.
 774  */
 775 void
 776 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
 777                              void *buffer, uint32_t threads, uint32_t stride);
 778
 779 #ifdef __cplusplus
 780 } /* extern "C" */
 781 #endif