2 * Copyright © 2010 - 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "brw_device_info.h"
28 #include "main/mtypes.h"
36 struct brw_geometry_program
;
37 union gl_constant_value
;
40 const struct brw_device_info
*devinfo
;
46 * Array of the ra classes for the unaligned contiguous register
52 * Mapping for register-allocated objects in *regs to the first
53 * GRF for that object.
55 uint8_t *ra_reg_to_grf
;
62 * Array of the ra classes for the unaligned contiguous register
63 * block sizes used, indexed by register size.
68 * Mapping from classes to ra_reg ranges. Each of the per-size
69 * classes corresponds to a range of ra_reg nodes. This array stores
70 * those ranges in the form of first ra_reg in each class and the
71 * total number of ra_reg elements in the last array element. This
72 * way the range of the i'th class is given by:
73 * [ class_to_ra_reg_range[i], class_to_ra_reg_range[i+1] )
75 int class_to_ra_reg_range
[17];
78 * Mapping for register-allocated objects in *regs to the first
79 * GRF for that object.
81 uint8_t *ra_reg_to_grf
;
84 * ra class for the aligned pairs we use for PLN, which doesn't
87 int aligned_pairs_class
;
90 void (*shader_debug_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
91 void (*shader_perf_log
)(void *, const char *str
, ...) PRINTFLIKE(2, 3);
93 bool scalar_stage
[MESA_SHADER_STAGES
];
94 struct gl_shader_compiler_options glsl_compiler_options
[MESA_SHADER_STAGES
];
97 * Apply workarounds for SIN and COS output range problems.
98 * This can negatively impact performance.
103 struct brw_compiler
*
104 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
108 * Program key structures.
110 * When drawing, we look for the currently bound shaders in the program
111 * cache. This is essentially a hash table lookup, and these are the keys.
113 * Sometimes OpenGL features specified as state need to be simulated via
114 * shader code, due to a mismatch between the API and the hardware. This
115 * is often referred to as "non-orthagonal state" or "NOS". We store NOS
116 * in the program key so it's considered when searching for a program. If
117 * we haven't seen a particular combination before, we have to recompile a
118 * new specialized version.
120 * Shader compilation should not look up state in gl_context directly, but
121 * instead use the copy in the program key. This guarantees recompiles will
127 enum PACKED gen6_gather_sampler_wa
{
128 WA_SIGN
= 1, /* whether we need to sign extend */
129 WA_8BIT
= 2, /* if we have an 8bit format needing wa */
130 WA_16BIT
= 4, /* if we have a 16bit format needing wa */
134 * Sampler information needed by VS, WM, and GS program cache keys.
136 struct brw_sampler_prog_key_data
{
138 * EXT_texture_swizzle and DEPTH_TEXTURE_MODE swizzles.
140 uint16_t swizzles
[MAX_SAMPLERS
];
142 uint32_t gl_clamp_mask
[3];
145 * For RG32F, gather4's channel select is broken.
147 uint32_t gather_channel_quirk_mask
;
150 * Whether this sampler uses the compressed multisample surface layout.
152 uint32_t compressed_multisample_layout_mask
;
155 * Whether this sampler is using 16x multisampling. If so fetching from
156 * this sampler will be handled with a different instruction, ld2dms_w
162 * For Sandybridge, which shader w/a we need for gather quirks.
164 enum gen6_gather_sampler_wa gen6_gather_wa
[MAX_SAMPLERS
];
168 /** The program key for Vertex Shaders. */
169 struct brw_vs_prog_key
{
170 unsigned program_string_id
;
173 * Per-attribute workaround flags
175 uint8_t gl_attrib_wa_flags
[VERT_ATTRIB_MAX
];
177 bool copy_edgeflag
:1;
179 bool clamp_vertex_color
:1;
182 * How many user clipping planes are being uploaded to the vertex shader as
185 * These are used for lowering legacy gl_ClipVertex/gl_Position clipping to
188 unsigned nr_userclip_plane_consts
:4;
191 * For pre-Gen6 hardware, a bitfield indicating which texture coordinates
192 * are going to be replaced with point coordinates (as a consequence of a
193 * call to glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE)). Because
194 * our SF thread requires exact matching between VS outputs and FS inputs,
195 * these texture coordinates will need to be unconditionally included in
196 * the VUE, even if they aren't written by the vertex shader.
198 uint8_t point_coord_replace
;
200 struct brw_sampler_prog_key_data tex
;
203 /** The program key for Tessellation Control Shaders. */
204 struct brw_tcs_prog_key
206 unsigned program_string_id
;
208 GLenum tes_primitive_mode
;
210 unsigned input_vertices
;
212 /** A bitfield of per-patch outputs written. */
213 uint32_t patch_outputs_written
;
215 /** A bitfield of per-vertex outputs written. */
216 uint64_t outputs_written
;
218 struct brw_sampler_prog_key_data tex
;
221 /** The program key for Tessellation Evaluation Shaders. */
222 struct brw_tes_prog_key
224 unsigned program_string_id
;
226 /** A bitfield of per-patch inputs read. */
227 uint32_t patch_inputs_read
;
229 /** A bitfield of per-vertex inputs read. */
230 uint64_t inputs_read
;
232 struct brw_sampler_prog_key_data tex
;
235 /** The program key for Geometry Shaders. */
236 struct brw_gs_prog_key
238 unsigned program_string_id
;
240 struct brw_sampler_prog_key_data tex
;
243 /** The program key for Fragment/Pixel Shaders. */
244 struct brw_wm_prog_key
{
248 bool persample_shading
:1;
250 unsigned nr_color_regions
:5;
251 bool replicate_alpha
:1;
252 bool render_to_fbo
:1;
253 bool clamp_fragment_color
:1;
254 bool compute_pos_offset
:1;
255 bool compute_sample_id
:1;
257 bool high_quality_derivatives
:1;
258 bool force_dual_color_blend
:1;
260 uint16_t drawable_height
;
261 uint64_t input_slots_valid
;
262 unsigned program_string_id
;
263 GLenum alpha_test_func
; /* < For Gen4/5 MRT alpha test */
264 float alpha_test_ref
;
266 struct brw_sampler_prog_key_data tex
;
269 struct brw_cs_prog_key
{
270 uint32_t program_string_id
;
271 struct brw_sampler_prog_key_data tex
;
275 * Image metadata structure as laid out in the shader parameter
276 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
277 * able to use them. That's okay because the padding and any unused
278 * entries [most of them except when we're doing untyped surface
279 * access] will be removed by the uniform packing pass.
281 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
282 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
283 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
284 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
285 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
286 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
287 #define BRW_IMAGE_PARAM_SIZE 24
289 struct brw_image_param
{
290 /** Surface binding table index. */
291 uint32_t surface_idx
;
293 /** Offset applied to the X and Y surface coordinates. */
296 /** Surface X, Y and Z dimensions. */
299 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
300 * pixels, vertical slice stride in pixels.
304 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
308 * Right shift to apply for bit 6 address swizzling. Two different
309 * swizzles can be specified and will be applied one after the other. The
310 * resulting address will be:
312 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
313 * (addr >> swizzling[1])))
315 * Use \c 0xff if any of the swizzles is not required.
317 uint32_t swizzling
[2];
320 struct brw_stage_prog_data
{
322 /** size of our binding table. */
326 * surface indices for the various groups of surfaces
328 uint32_t pull_constants_start
;
329 uint32_t texture_start
;
330 uint32_t gather_texture_start
;
334 uint32_t image_start
;
335 uint32_t shader_time_start
;
339 GLuint nr_params
; /**< number of float params/constants */
340 GLuint nr_pull_params
;
341 unsigned nr_image_params
;
343 unsigned curb_read_length
;
344 unsigned total_scratch
;
345 unsigned total_shared
;
348 * Register where the thread expects to find input data from the URB
349 * (typically uniforms, followed by vertex or fragment attributes).
351 unsigned dispatch_grf_start_reg
;
353 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
355 /* Pointers to tracked values (only valid once
356 * _mesa_load_state_parameters has been called at runtime).
358 const union gl_constant_value
**param
;
359 const union gl_constant_value
**pull_param
;
361 /** Image metadata passed to the shader as uniforms. */
362 struct brw_image_param
*image_param
;
365 /* Data about a particular attempt to compile a program. Note that
366 * there can be many of these, each in a different GL state
367 * corresponding to a different brw_wm_prog_key struct, with different
370 struct brw_wm_prog_data
{
371 struct brw_stage_prog_data base
;
373 GLuint num_varying_inputs
;
375 GLuint dispatch_grf_start_reg_16
;
377 GLuint reg_blocks_16
;
381 * surface indices the WM-specific surfaces
383 uint32_t render_target_start
;
387 uint8_t computed_depth_mode
;
388 bool computed_stencil
;
390 bool early_fragment_tests
;
393 bool uses_pos_offset
;
398 bool uses_sample_mask
;
400 uint32_t prog_offset_16
;
403 * Mask of which interpolation modes are required by the fragment shader.
404 * Used in hardware setup on gen6+.
406 uint32_t barycentric_interp_modes
;
409 * Map from gl_varying_slot to the position within the FS setup data
410 * payload where the varying's attribute vertex deltas should be delivered.
411 * For varying slots that are not used by the FS, the value is -1.
413 int urb_setup
[VARYING_SLOT_MAX
];
416 struct brw_cs_prog_data
{
417 struct brw_stage_prog_data base
;
419 GLuint dispatch_grf_start_reg_16
;
420 unsigned local_size
[3];
423 bool uses_num_work_groups
;
424 unsigned local_invocation_id_regs
;
428 * surface indices the CS-specific surfaces
430 uint32_t work_groups_start
;
436 * Enum representing the i965-specific vertex results that don't correspond
437 * exactly to any element of gl_varying_slot. The values of this enum are
438 * assigned such that they don't conflict with gl_varying_slot.
442 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
443 BRW_VARYING_SLOT_PAD
,
445 * Technically this is not a varying but just a placeholder that
446 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
447 * builtin variable to be compiled correctly. see compile_sf_prog() for
450 BRW_VARYING_SLOT_PNTC
,
451 BRW_VARYING_SLOT_COUNT
455 * Data structure recording the relationship between the gl_varying_slot enum
456 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
457 * single octaword within the VUE (128 bits).
459 * Note that each BRW register contains 256 bits (2 octawords), so when
460 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
461 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
462 * in a vertex shader), each register corresponds to a single VUE slot, since
463 * it contains data for two separate vertices.
467 * Bitfield representing all varying slots that are (a) stored in this VUE
468 * map, and (b) actually written by the shader. Does not include any of
469 * the additional varying slots defined in brw_varying_slot.
471 GLbitfield64 slots_valid
;
474 * Is this VUE map for a separate shader pipeline?
476 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
477 * without the linker having a chance to dead code eliminate unused varyings.
479 * This means that we have to use a fixed slot layout, based on the output's
480 * location field, rather than assigning slots in a compact contiguous block.
485 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
486 * not stored in a slot (because they are not written, or because
487 * additional processing is applied before storing them in the VUE), the
490 signed char varying_to_slot
[VARYING_SLOT_TESS_MAX
];
493 * Map from VUE slot to gl_varying_slot value. For slots that do not
494 * directly correspond to a gl_varying_slot, the value comes from
497 * For slots that are not in use, the value is BRW_VARYING_SLOT_PAD.
499 signed char slot_to_varying
[VARYING_SLOT_TESS_MAX
];
502 * Total number of VUE slots in use
507 * Number of per-patch VUE slots. Only valid for tessellation control
508 * shader outputs and tessellation evaluation shader inputs.
510 int num_per_patch_slots
;
513 * Number of per-vertex VUE slots. Only valid for tessellation control
514 * shader outputs and tessellation evaluation shader inputs.
516 int num_per_vertex_slots
;
519 void brw_print_vue_map(FILE *fp
, const struct brw_vue_map
*vue_map
);
522 * Convert a VUE slot number into a byte offset within the VUE.
524 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
530 * Convert a vertex output (brw_varying_slot) into a byte offset within the
534 GLuint
brw_varying_to_offset(const struct brw_vue_map
*vue_map
, GLuint varying
)
536 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
539 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
540 struct brw_vue_map
*vue_map
,
541 GLbitfield64 slots_valid
,
542 bool separate_shader
);
544 void brw_compute_tess_vue_map(struct brw_vue_map
*const vue_map
,
545 const GLbitfield64 slots_valid
,
546 const GLbitfield is_patch
);
548 enum shader_dispatch_mode
{
549 DISPATCH_MODE_4X1_SINGLE
= 0,
550 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
551 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
552 DISPATCH_MODE_SIMD8
= 3,
556 * @defgroup Tessellator parameter enumerations.
558 * These correspond to the hardware values in 3DSTATE_TE, and are provided
559 * as part of the tessellation evaluation shader.
563 enum brw_tess_partitioning
{
564 BRW_TESS_PARTITIONING_INTEGER
= 0,
565 BRW_TESS_PARTITIONING_ODD_FRACTIONAL
= 1,
566 BRW_TESS_PARTITIONING_EVEN_FRACTIONAL
= 2,
569 enum brw_tess_output_topology
{
570 BRW_TESS_OUTPUT_TOPOLOGY_POINT
= 0,
571 BRW_TESS_OUTPUT_TOPOLOGY_LINE
= 1,
572 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
= 2,
573 BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW
= 3,
576 enum brw_tess_domain
{
577 BRW_TESS_DOMAIN_QUAD
= 0,
578 BRW_TESS_DOMAIN_TRI
= 1,
579 BRW_TESS_DOMAIN_ISOLINE
= 2,
583 struct brw_vue_prog_data
{
584 struct brw_stage_prog_data base
;
585 struct brw_vue_map vue_map
;
587 /** Should the hardware deliver input VUE handles for URB pull loads? */
588 bool include_vue_handles
;
590 GLuint urb_read_length
;
593 /* Used for calculating urb partitions. In the VS, this is the size of the
594 * URB entry used for both input and output to the thread. In the GS, this
595 * is the size of the URB entry used for output.
597 GLuint urb_entry_size
;
599 enum shader_dispatch_mode dispatch_mode
;
602 struct brw_vs_prog_data
{
603 struct brw_vue_prog_data base
;
605 GLbitfield64 inputs_read
;
607 unsigned nr_attributes
;
610 bool uses_instanceid
;
611 bool uses_basevertex
;
612 bool uses_baseinstance
;
616 struct brw_tcs_prog_data
618 struct brw_vue_prog_data base
;
620 /** Number vertices in output patch */
625 struct brw_tes_prog_data
627 struct brw_vue_prog_data base
;
629 enum brw_tess_partitioning partitioning
;
630 enum brw_tess_output_topology output_topology
;
631 enum brw_tess_domain domain
;
634 struct brw_gs_prog_data
636 struct brw_vue_prog_data base
;
638 unsigned vertices_in
;
641 * Size of an output vertex, measured in HWORDS (32 bytes).
643 unsigned output_vertex_size_hwords
;
645 unsigned output_topology
;
648 * Size of the control data (cut bits or StreamID bits), in hwords (32
649 * bytes). 0 if there is no control data.
651 unsigned control_data_header_size_hwords
;
654 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
655 * if the control data is StreamID bits, or
656 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
657 * Ignored if control_data_header_size is 0.
659 unsigned control_data_format
;
661 bool include_primitive_id
;
664 * The number of vertices emitted, if constant - otherwise -1.
666 int static_vertex_count
;
671 * Gen6 transform feedback enabled flag.
673 bool gen6_xfb_enabled
;
676 * Gen6: Provoking vertex convention for odd-numbered triangles
682 * Gen6: Number of varyings that are output to transform feedback.
684 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
687 * Gen6: Map from the index of a transform feedback binding table entry to the
688 * gl_varying_slot that should be streamed out through that binding table
691 unsigned char transform_feedback_bindings
[64 /* BRW_MAX_SOL_BINDINGS */];
694 * Gen6: Map from the index of a transform feedback binding table entry to the
695 * swizzles that should be used when streaming out data through that
696 * binding table entry.
698 unsigned char transform_feedback_swizzles
[64 /* BRW_MAX_SOL_BINDINGS */];
704 struct brw_compiler
*
705 brw_compiler_create(void *mem_ctx
, const struct brw_device_info
*devinfo
);
708 * Compile a vertex shader.
710 * Returns the final assembly and the program's size.
713 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
715 const struct brw_vs_prog_key
*key
,
716 struct brw_vs_prog_data
*prog_data
,
717 const struct nir_shader
*shader
,
718 gl_clip_plane
*clip_planes
,
719 bool use_legacy_snorm_formula
,
720 int shader_time_index
,
721 unsigned *final_assembly_size
,
725 * Compile a tessellation control shader.
727 * Returns the final assembly and the program's size.
730 brw_compile_tcs(const struct brw_compiler
*compiler
,
733 const struct brw_tcs_prog_key
*key
,
734 struct brw_tcs_prog_data
*prog_data
,
735 const struct nir_shader
*nir
,
736 int shader_time_index
,
737 unsigned *final_assembly_size
,
741 * Compile a tessellation evaluation shader.
743 * Returns the final assembly and the program's size.
746 brw_compile_tes(const struct brw_compiler
*compiler
, void *log_data
,
748 const struct brw_tes_prog_key
*key
,
749 struct brw_tes_prog_data
*prog_data
,
750 const struct nir_shader
*shader
,
751 struct gl_shader_program
*shader_prog
,
752 int shader_time_index
,
753 unsigned *final_assembly_size
,
757 * Compile a vertex shader.
759 * Returns the final assembly and the program's size.
762 brw_compile_gs(const struct brw_compiler
*compiler
, void *log_data
,
764 const struct brw_gs_prog_key
*key
,
765 struct brw_gs_prog_data
*prog_data
,
766 const struct nir_shader
*shader
,
767 struct gl_shader_program
*shader_prog
,
768 int shader_time_index
,
769 unsigned *final_assembly_size
,
773 * Compile a fragment shader.
775 * Returns the final assembly and the program's size.
778 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
780 const struct brw_wm_prog_key
*key
,
781 struct brw_wm_prog_data
*prog_data
,
782 const struct nir_shader
*shader
,
783 struct gl_program
*prog
,
784 int shader_time_index8
,
785 int shader_time_index16
,
787 unsigned *final_assembly_size
,
791 * Compile a compute shader.
793 * Returns the final assembly and the program's size.
796 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
798 const struct brw_cs_prog_key
*key
,
799 struct brw_cs_prog_data
*prog_data
,
800 const struct nir_shader
*shader
,
801 int shader_time_index
,
802 unsigned *final_assembly_size
,
806 * Fill out local id payload for compute shader according to cs_prog_data.
809 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*cs_prog_data
,
810 void *buffer
, uint32_t threads
, uint32_t stride
);